1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Bruno Cardoso Lopes and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Function.h"
21 #include "llvm/Intrinsics.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/CodeGen/SSARegMap.h"
29 #include "llvm/CodeGen/ValueTypes.h"
30 #include "llvm/Support/Debug.h"
36 const char *MipsTargetLowering::
37 getTargetNodeName(unsigned Opcode) const
41 case MipsISD::JmpLink : return "MipsISD::JmpLink";
42 case MipsISD::Hi : return "MipsISD::Hi";
43 case MipsISD::Lo : return "MipsISD::Lo";
44 case MipsISD::Ret : return "MipsISD::Ret";
45 default : return NULL;
50 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
52 // Mips does not have i1 type, so use i32 for
53 // setcc operations results (slt, sgt, ...).
54 setSetCCResultType(MVT::i32);
55 setSetCCResultContents(ZeroOrOneSetCCResult);
57 // Set up the register classes
58 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
61 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
62 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
63 setOperationAction(ISD::RET, MVT::Other, Custom);
65 // Load extented operations for i1 types must be promoted
66 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
67 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
68 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
70 // Store operations for i1 types must be promoted
71 setStoreXAction(MVT::i1, Promote);
73 // Mips does not have these NodeTypes below.
74 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
75 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
76 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
77 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
78 setOperationAction(ISD::SELECT, MVT::i32, Expand);
80 // Mips not supported intrinsics.
81 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
82 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
83 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
85 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
86 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
87 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
88 setOperationAction(ISD::ROTL , MVT::i32, Expand);
89 setOperationAction(ISD::ROTR , MVT::i32, Expand);
90 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
92 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
93 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
94 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
96 // We don't have line number support yet.
97 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
98 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
99 setOperationAction(ISD::LABEL, MVT::Other, Expand);
101 // Use the default for now
102 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
103 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
105 setStackPointerRegisterToSaveRestore(Mips::SP);
106 computeRegisterProperties();
110 SDOperand MipsTargetLowering::
111 LowerOperation(SDOperand Op, SelectionDAG &DAG)
113 switch (Op.getOpcode())
115 case ISD::CALL: return LowerCALL(Op, DAG);
116 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
117 case ISD::RET: return LowerRET(Op, DAG);
118 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
119 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
120 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
125 //===----------------------------------------------------------------------===//
126 // Lower helper functions
127 //===----------------------------------------------------------------------===//
129 // AddLiveIn - This helper function adds the specified physical register to the
130 // MachineFunction as a live in value. It also creates a corresponding
131 // virtual register for it.
133 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
135 assert(RC->contains(PReg) && "Not the correct regclass!");
136 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
137 MF.addLiveIn(PReg, VReg);
141 // Set up a frame object for the return address.
142 //SDOperand MipsTargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
143 // if (ReturnAddrIndex == 0) {
144 // MachineFunction &MF = DAG.getMachineFunction();
145 // ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, 0);
148 // return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
152 //===----------------------------------------------------------------------===//
153 // Misc Lower Operation implementation
154 //===----------------------------------------------------------------------===//
155 SDOperand MipsTargetLowering::
156 LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
158 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
160 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
161 SDOperand Hi = DAG.getNode(MipsISD::Hi, MVT::i32, GA);
162 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
164 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
167 SDOperand MipsTargetLowering::
168 LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG)
170 assert(0 && "TLS not implemented for MIPS.");
173 //===----------------------------------------------------------------------===//
174 // Calling Convention Implementation
176 // The lower operations present on calling convention works on this order:
177 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
178 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
179 // LowerRET (virt regs --> phys regs)
180 // LowerCALL (phys regs --> virt regs)
182 //===----------------------------------------------------------------------===//
184 #include "MipsGenCallingConv.inc"
186 //===----------------------------------------------------------------------===//
187 // CALL Calling Convention Implementation
188 //===----------------------------------------------------------------------===//
190 /// Mips custom CALL implementation
191 SDOperand MipsTargetLowering::
192 LowerCALL(SDOperand Op, SelectionDAG &DAG)
194 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
196 // By now, only CallingConv::C implemented
200 assert(0 && "Unsupported calling convention");
201 case CallingConv::Fast:
203 return LowerCCCCallTo(Op, DAG, CallingConv);
207 /// LowerCCCCallTo - functions arguments are copied from virtual
208 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
209 /// CALLSEQ_END are emitted.
210 /// TODO: isVarArg, isTailCall, sret, GOT, linkage types.
211 SDOperand MipsTargetLowering::
212 LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
214 MachineFunction &MF = DAG.getMachineFunction();
215 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
217 SDOperand Chain = Op.getOperand(0);
218 SDOperand Callee = Op.getOperand(4);
219 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
221 MachineFrameInfo *MFI = MF.getFrameInfo();
223 // Analyze operands of the call, assigning locations to each operand.
224 SmallVector<CCValAssign, 16> ArgLocs;
225 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
227 // To meet ABI, Mips must always allocate 16 bytes on
228 // the stack (even if less than 4 are used as arguments)
229 int VTsize = MVT::getSizeInBits(MVT::i32)/8;
230 MFI->CreateFixedObject(VTsize, -(VTsize*3));
232 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
234 // Get a count of how many bytes are to be pushed on the stack.
235 unsigned NumBytes = CCInfo.getNextStackOffset();
236 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
239 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
240 SmallVector<SDOperand, 8> MemOpChains;
244 // Walk the register/memloc assignments, inserting copies/loads.
245 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
246 CCValAssign &VA = ArgLocs[i];
248 // Arguments start after the 5 first operands of ISD::CALL
249 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
251 // Promote the value if needed.
252 switch (VA.getLocInfo()) {
253 default: assert(0 && "Unknown loc info!");
254 case CCValAssign::Full: break;
255 case CCValAssign::SExt:
256 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
258 case CCValAssign::ZExt:
259 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
261 case CCValAssign::AExt:
262 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
266 // Arguments that can be passed on register,
267 // must be kept at RegsToPass vector
269 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
272 assert(VA.isMemLoc());
274 if (StackPtr.Val == 0)
275 StackPtr = DAG.getRegister(StackReg, getPointerTy());
277 // Create the frame index object for this incoming parameter
278 // This guarantees that when allocating Local Area our room
279 // will not be overwritten.
280 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
281 -(16 + VA.getLocMemOffset()) );
283 SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy());
285 // emit ISD::STORE whichs stores the
286 // parameter value to a stack Location
287 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
291 // Transform all store nodes into one single node because
292 // all store nodes are independent of each other.
293 if (!MemOpChains.empty())
294 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
295 &MemOpChains[0], MemOpChains.size());
297 // Build a sequence of copy-to-reg nodes chained together with token
298 // chain and flag operands which copy the outgoing args into registers.
299 // The InFlag in necessary since all emited instructions must be
302 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
303 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
304 RegsToPass[i].second, InFlag);
305 InFlag = Chain.getValue(1);
308 // If the callee is a GlobalAddress node (quite common, every direct
309 // call is) turn it into a TargetGlobalAddress node so that legalize
311 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
312 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
314 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
315 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
317 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
318 // = Chain, Callee, Reg#1, Reg#2, ...
320 // Returns a chain & a flag for retval copy to use.
321 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
322 SmallVector<SDOperand, 8> Ops;
323 Ops.push_back(Chain);
324 Ops.push_back(Callee);
326 // Add argument registers to the end of the list so that they are
327 // known live into the call.
328 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
329 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
330 RegsToPass[i].second.getValueType()));
333 Ops.push_back(InFlag);
335 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
336 InFlag = Chain.getValue(1);
338 // Create the CALLSEQ_END node.
339 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
341 Ops.push_back(Chain);
342 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
343 Ops.push_back(InFlag);
344 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
345 InFlag = Chain.getValue(1);
347 // Handle result values, copying them out of physregs into vregs that we
349 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
352 /// LowerCallResult - Lower the result values of an ISD::CALL into the
353 /// appropriate copies out of appropriate physical registers. This assumes that
354 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
355 /// being lowered. Returns a SDNode with the same number of values as the
357 SDNode *MipsTargetLowering::
358 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
359 unsigned CallingConv, SelectionDAG &DAG) {
361 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
363 // Assign locations to each value returned by this call.
364 SmallVector<CCValAssign, 16> RVLocs;
365 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
367 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
368 SmallVector<SDOperand, 8> ResultVals;
374 // Copy all of the result registers out of their specified physreg.
375 for (unsigned i = 0; i != RVLocs.size(); ++i) {
376 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
377 RVLocs[i].getValVT(), InFlag).getValue(1);
378 InFlag = Chain.getValue(2);
379 ResultVals.push_back(Chain.getValue(0));
382 // Merge everything together with a MERGE_VALUES node.
383 ResultVals.push_back(Chain);
384 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
385 &ResultVals[0], ResultVals.size()).Val;
388 //===----------------------------------------------------------------------===//
389 // FORMAL_ARGUMENTS Calling Convention Implementation
390 //===----------------------------------------------------------------------===//
392 /// Mips custom FORMAL_ARGUMENTS implementation
393 SDOperand MipsTargetLowering::
394 LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
396 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
400 assert(0 && "Unsupported calling convention");
402 return LowerCCCArguments(Op, DAG);
406 /// LowerCCCArguments - transform physical registers into
407 /// virtual registers and generate load operations for
408 /// arguments places on the stack.
409 /// TODO: isVarArg, sret
410 SDOperand MipsTargetLowering::
411 LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
413 SDOperand Root = Op.getOperand(0);
414 MachineFunction &MF = DAG.getMachineFunction();
415 MachineFrameInfo *MFI = MF.getFrameInfo();
417 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
418 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
420 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
422 // Assign locations to all of the incoming arguments.
423 SmallVector<CCValAssign, 16> ArgLocs;
424 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
426 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
427 SmallVector<SDOperand, 8> ArgValues;
430 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
432 CCValAssign &VA = ArgLocs[i];
434 // Arguments stored on registers
436 MVT::ValueType RegVT = VA.getLocVT();
437 TargetRegisterClass *RC;
439 if (RegVT == MVT::i32)
440 RC = Mips::CPURegsRegisterClass;
442 assert(0 && "support only Mips::CPURegsRegisterClass");
445 // Transform the arguments stored on
446 // physical registers into virtual ones
447 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
448 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
450 // If this is an 8 or 16-bit value, it is really passed promoted
451 // to 32 bits. Insert an assert[sz]ext to capture this, then
452 // truncate to the right size.
453 if (VA.getLocInfo() == CCValAssign::SExt)
454 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
455 DAG.getValueType(VA.getValVT()));
456 else if (VA.getLocInfo() == CCValAssign::ZExt)
457 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
458 DAG.getValueType(VA.getValVT()));
460 if (VA.getLocInfo() != CCValAssign::Full)
461 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
463 ArgValues.push_back(ArgValue);
465 // To meet ABI, when VARARGS are passed on registers, the registers
466 // containt must be written to the their always reserved home location
470 if (StackPtr.Val == 0)
471 StackPtr = DAG.getRegister(StackReg, getPointerTy());
473 // Create the frame index object for this incoming parameter
474 // The first 16 bytes are reserved.
475 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
477 SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy());
479 // emit ISD::STORE whichs stores the
480 // parameter value to a stack Location
481 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
486 assert(VA.isMemLoc());
488 // Create the frame index object for this incoming parameter...
489 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
490 (16 + VA.getLocMemOffset()));
492 // Create load nodes to retrieve arguments from the stack
493 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
494 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
497 ArgValues.push_back(Root);
499 // Return the new list of results.
500 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
501 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
504 //===----------------------------------------------------------------------===//
505 // Return Value Calling Convention Implementation
506 //===----------------------------------------------------------------------===//
508 SDOperand MipsTargetLowering::
509 LowerRET(SDOperand Op, SelectionDAG &DAG)
511 // CCValAssign - represent the assignment of
512 // the return value to a location
513 SmallVector<CCValAssign, 16> RVLocs;
514 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
515 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
517 // CCState - Info about the registers and stack slot.
518 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
520 // Analize return values of ISD::RET
521 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
523 // If this is the first return lowered for this function, add
524 // the regs to the liveout set for the function.
525 if (DAG.getMachineFunction().liveout_empty()) {
526 for (unsigned i = 0; i != RVLocs.size(); ++i)
527 if (RVLocs[i].isRegLoc())
528 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
531 // The chain is always operand #0
532 SDOperand Chain = Op.getOperand(0);
535 // Copy the result values into the output registers.
536 for (unsigned i = 0; i != RVLocs.size(); ++i) {
537 CCValAssign &VA = RVLocs[i];
538 assert(VA.isRegLoc() && "Can only return in registers!");
540 // ISD::RET => ret chain, (regnum1,val1), ...
541 // So i*2+1 index only the regnums
542 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(),
543 Op.getOperand(i*2+1), Flag);
545 // guarantee that all emitted copies are
546 // stuck together, avoiding something bad
547 Flag = Chain.getValue(1);
550 // Return on Mips is always a "jr $ra"
552 return DAG.getNode(MipsISD::Ret, MVT::Other,
553 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
555 return DAG.getNode(MipsISD::Ret, MVT::Other,
556 Chain, DAG.getRegister(Mips::RA, MVT::i32));