1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
16 //#include <algorithm>
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsTargetObjectFile.h"
21 #include "MipsSubtarget.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/CodeGen/CallingConvLower.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
38 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
40 case MipsISD::JmpLink: return "MipsISD::JmpLink";
41 case MipsISD::Hi: return "MipsISD::Hi";
42 case MipsISD::Lo: return "MipsISD::Lo";
43 case MipsISD::GPRel: return "MipsISD::GPRel";
44 case MipsISD::Ret: return "MipsISD::Ret";
45 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
46 case MipsISD::FPCmp: return "MipsISD::FPCmp";
47 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
48 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
49 case MipsISD::FPRound: return "MipsISD::FPRound";
50 case MipsISD::MAdd: return "MipsISD::MAdd";
51 case MipsISD::MAddu: return "MipsISD::MAddu";
52 case MipsISD::MSub: return "MipsISD::MSub";
53 case MipsISD::MSubu: return "MipsISD::MSubu";
54 case MipsISD::DivRem: return "MipsISD::DivRem";
55 case MipsISD::DivRemU: return "MipsISD::DivRemU";
56 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
57 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
63 MipsTargetLowering(MipsTargetMachine &TM)
64 : TargetLowering(TM, new MipsTargetObjectFile()) {
65 Subtarget = &TM.getSubtarget<MipsSubtarget>();
67 // Mips does not have i1 type, so use i32 for
68 // setcc operations results (slt, sgt, ...).
69 setBooleanContents(ZeroOrOneBooleanContent);
71 // Set up the register classes
72 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
73 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
75 // When dealing with single precision only, use libcalls
76 if (!Subtarget->isSingleFloat())
77 if (!Subtarget->isFP64bit())
78 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
80 // Load extented operations for i1 types must be promoted
81 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
82 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
85 // MIPS doesn't have extending float->double load/store
86 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
87 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
89 // Used by legalize types to correctly generate the setcc result.
90 // Without this, every float setcc comes with a AND/OR with the result,
91 // we don't want this, since the fpcmp result goes to a flag register,
92 // which is used implicitly by brcond and select operations.
93 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
95 // Mips Custom Operations
96 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
97 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
98 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
99 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
100 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
101 setOperationAction(ISD::SELECT, MVT::f32, Custom);
102 setOperationAction(ISD::SELECT, MVT::f64, Custom);
103 setOperationAction(ISD::SELECT, MVT::i32, Custom);
104 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
105 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
106 setOperationAction(ISD::VASTART, MVT::Other, Custom);
108 setOperationAction(ISD::SDIV, MVT::i32, Expand);
109 setOperationAction(ISD::SREM, MVT::i32, Expand);
110 setOperationAction(ISD::UDIV, MVT::i32, Expand);
111 setOperationAction(ISD::UREM, MVT::i32, Expand);
113 // Operations not directly supported by Mips.
114 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
115 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
116 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
117 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
118 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
120 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
121 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
122 setOperationAction(ISD::ROTL, MVT::i32, Expand);
124 if (!Subtarget->isMips32r2())
125 setOperationAction(ISD::ROTR, MVT::i32, Expand);
127 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
128 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
129 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
130 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
131 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
132 setOperationAction(ISD::FSIN, MVT::f32, Expand);
133 setOperationAction(ISD::FSIN, MVT::f64, Expand);
134 setOperationAction(ISD::FCOS, MVT::f32, Expand);
135 setOperationAction(ISD::FCOS, MVT::f64, Expand);
136 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
137 setOperationAction(ISD::FPOW, MVT::f32, Expand);
138 setOperationAction(ISD::FPOW, MVT::f64, Expand);
139 setOperationAction(ISD::FLOG, MVT::f32, Expand);
140 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
141 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
142 setOperationAction(ISD::FEXP, MVT::f32, Expand);
144 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
145 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
147 setOperationAction(ISD::VAARG, MVT::Other, Expand);
148 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
149 setOperationAction(ISD::VAEND, MVT::Other, Expand);
151 // Use the default for now
152 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
153 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
154 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
156 if (Subtarget->isSingleFloat())
157 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
159 if (!Subtarget->hasSEInReg()) {
160 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
161 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
164 if (!Subtarget->hasBitCount())
165 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
167 if (!Subtarget->hasSwap())
168 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
170 setTargetDAGCombine(ISD::ADDE);
171 setTargetDAGCombine(ISD::SUBE);
172 setTargetDAGCombine(ISD::SDIVREM);
173 setTargetDAGCombine(ISD::UDIVREM);
174 setTargetDAGCombine(ISD::SETCC);
176 setMinFunctionAlignment(2);
178 setStackPointerRegisterToSaveRestore(Mips::SP);
179 computeRegisterProperties();
181 setExceptionPointerRegister(Mips::A0);
182 setExceptionSelectorRegister(Mips::A1);
185 MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
190 // Transforms a subgraph in CurDAG if the following pattern is found:
191 // (addc multLo, Lo0), (adde multHi, Hi0),
193 // multHi/Lo: product of multiplication
194 // Lo0: initial value of Lo register
195 // Hi0: initial value of Hi register
196 // Return true if pattern matching was successful.
197 static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
198 // ADDENode's second operand must be a flag output of an ADDC node in order
199 // for the matching to be successful.
200 SDNode* ADDCNode = ADDENode->getOperand(2).getNode();
202 if (ADDCNode->getOpcode() != ISD::ADDC)
205 SDValue MultHi = ADDENode->getOperand(0);
206 SDValue MultLo = ADDCNode->getOperand(0);
207 SDNode* MultNode = MultHi.getNode();
208 unsigned MultOpc = MultHi.getOpcode();
210 // MultHi and MultLo must be generated by the same node,
211 if (MultLo.getNode() != MultNode)
214 // and it must be a multiplication.
215 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
218 // MultLo amd MultHi must be the first and second output of MultNode
220 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
223 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
224 // of the values of MultNode, in which case MultNode will be removed in later
226 // If there exist users other than ADDENode or ADDCNode, this function returns
227 // here, which will result in MultNode being mapped to a single MULT
228 // instruction node rather than a pair of MULT and MADD instructions being
230 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
233 SDValue Chain = CurDAG->getEntryNode();
234 DebugLoc dl = ADDENode->getDebugLoc();
236 // create MipsMAdd(u) node
237 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
239 SDValue MAdd = CurDAG->getNode(MultOpc, dl,
241 MultNode->getOperand(0),// Factor 0
242 MultNode->getOperand(1),// Factor 1
243 ADDCNode->getOperand(1),// Lo0
244 ADDENode->getOperand(1));// Hi0
246 // create CopyFromReg nodes
247 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
249 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
251 CopyFromLo.getValue(2));
253 // replace uses of adde and addc here
254 if (!SDValue(ADDCNode, 0).use_empty())
255 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
257 if (!SDValue(ADDENode, 0).use_empty())
258 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
264 // Transforms a subgraph in CurDAG if the following pattern is found:
265 // (addc Lo0, multLo), (sube Hi0, multHi),
267 // multHi/Lo: product of multiplication
268 // Lo0: initial value of Lo register
269 // Hi0: initial value of Hi register
270 // Return true if pattern matching was successful.
271 static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
272 // SUBENode's second operand must be a flag output of an SUBC node in order
273 // for the matching to be successful.
274 SDNode* SUBCNode = SUBENode->getOperand(2).getNode();
276 if (SUBCNode->getOpcode() != ISD::SUBC)
279 SDValue MultHi = SUBENode->getOperand(1);
280 SDValue MultLo = SUBCNode->getOperand(1);
281 SDNode* MultNode = MultHi.getNode();
282 unsigned MultOpc = MultHi.getOpcode();
284 // MultHi and MultLo must be generated by the same node,
285 if (MultLo.getNode() != MultNode)
288 // and it must be a multiplication.
289 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
292 // MultLo amd MultHi must be the first and second output of MultNode
294 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
297 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
298 // of the values of MultNode, in which case MultNode will be removed in later
300 // If there exist users other than SUBENode or SUBCNode, this function returns
301 // here, which will result in MultNode being mapped to a single MULT
302 // instruction node rather than a pair of MULT and MSUB instructions being
304 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
307 SDValue Chain = CurDAG->getEntryNode();
308 DebugLoc dl = SUBENode->getDebugLoc();
310 // create MipsSub(u) node
311 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
313 SDValue MSub = CurDAG->getNode(MultOpc, dl,
315 MultNode->getOperand(0),// Factor 0
316 MultNode->getOperand(1),// Factor 1
317 SUBCNode->getOperand(0),// Lo0
318 SUBENode->getOperand(0));// Hi0
320 // create CopyFromReg nodes
321 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
323 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
325 CopyFromLo.getValue(2));
327 // replace uses of sube and subc here
328 if (!SDValue(SUBCNode, 0).use_empty())
329 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
331 if (!SDValue(SUBENode, 0).use_empty())
332 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
337 static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
338 TargetLowering::DAGCombinerInfo &DCI,
339 const MipsSubtarget* Subtarget) {
340 if (DCI.isBeforeLegalize())
343 if (Subtarget->isMips32() && SelectMadd(N, &DAG))
344 return SDValue(N, 0);
349 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
350 TargetLowering::DAGCombinerInfo &DCI,
351 const MipsSubtarget* Subtarget) {
352 if (DCI.isBeforeLegalize())
355 if (Subtarget->isMips32() && SelectMsub(N, &DAG))
356 return SDValue(N, 0);
361 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG,
362 TargetLowering::DAGCombinerInfo &DCI,
363 const MipsSubtarget* Subtarget) {
364 if (DCI.isBeforeLegalizeOps())
367 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
369 DebugLoc dl = N->getDebugLoc();
371 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
372 N->getOperand(0), N->getOperand(1));
373 SDValue InChain = DAG.getEntryNode();
374 SDValue InGlue = DivRem;
377 if (N->hasAnyUseOfValue(0)) {
378 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, Mips::LO, MVT::i32,
380 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
381 InChain = CopyFromLo.getValue(1);
382 InGlue = CopyFromLo.getValue(2);
386 if (N->hasAnyUseOfValue(1)) {
387 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
388 Mips::HI, MVT::i32, InGlue);
389 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
395 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
397 default: llvm_unreachable("Unknown fp condition code!");
399 case ISD::SETOEQ: return Mips::FCOND_OEQ;
400 case ISD::SETUNE: return Mips::FCOND_UNE;
402 case ISD::SETOLT: return Mips::FCOND_OLT;
404 case ISD::SETOGT: return Mips::FCOND_OGT;
406 case ISD::SETOLE: return Mips::FCOND_OLE;
408 case ISD::SETOGE: return Mips::FCOND_OGE;
409 case ISD::SETULT: return Mips::FCOND_ULT;
410 case ISD::SETULE: return Mips::FCOND_ULE;
411 case ISD::SETUGT: return Mips::FCOND_UGT;
412 case ISD::SETUGE: return Mips::FCOND_UGE;
413 case ISD::SETUO: return Mips::FCOND_UN;
414 case ISD::SETO: return Mips::FCOND_OR;
416 case ISD::SETONE: return Mips::FCOND_ONE;
417 case ISD::SETUEQ: return Mips::FCOND_UEQ;
422 // Returns true if condition code has to be inverted.
423 static bool InvertFPCondCode(Mips::CondCode CC) {
424 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
427 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
430 assert(false && "Illegal Condition Code");
434 // Creates and returns an FPCmp node from a setcc node.
435 // Returns Op if setcc is not a floating point comparison.
436 static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) {
437 // must be a SETCC node
438 if (Op.getOpcode() != ISD::SETCC)
441 SDValue LHS = Op.getOperand(0);
443 if (!LHS.getValueType().isFloatingPoint())
446 SDValue RHS = Op.getOperand(1);
447 DebugLoc dl = Op.getDebugLoc();
449 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
450 // node if necessary.
451 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
453 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
454 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
457 // Creates and returns a CMovFPT/F node.
458 static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True,
459 SDValue False, DebugLoc DL) {
460 bool invert = InvertFPCondCode((Mips::CondCode)
461 cast<ConstantSDNode>(Cond.getOperand(2))
464 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
465 True.getValueType(), True, False, Cond);
468 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG,
469 TargetLowering::DAGCombinerInfo &DCI,
470 const MipsSubtarget* Subtarget) {
471 if (DCI.isBeforeLegalizeOps())
474 SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0));
476 if (Cond.getOpcode() != MipsISD::FPCmp)
479 SDValue True = DAG.getConstant(1, MVT::i32);
480 SDValue False = DAG.getConstant(0, MVT::i32);
482 return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc());
485 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
487 SelectionDAG &DAG = DCI.DAG;
488 unsigned opc = N->getOpcode();
493 return PerformADDECombine(N, DAG, DCI, Subtarget);
495 return PerformSUBECombine(N, DAG, DCI, Subtarget);
498 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
500 return PerformSETCCCombine(N, DAG, DCI, Subtarget);
506 SDValue MipsTargetLowering::
507 LowerOperation(SDValue Op, SelectionDAG &DAG) const
509 switch (Op.getOpcode())
511 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
512 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
513 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
514 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
515 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
516 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
517 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
518 case ISD::SELECT: return LowerSELECT(Op, DAG);
519 case ISD::VASTART: return LowerVASTART(Op, DAG);
520 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
525 //===----------------------------------------------------------------------===//
526 // Lower helper functions
527 //===----------------------------------------------------------------------===//
529 // AddLiveIn - This helper function adds the specified physical register to the
530 // MachineFunction as a live in value. It also creates a corresponding
531 // virtual register for it.
533 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
535 assert(RC->contains(PReg) && "Not the correct regclass!");
536 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
537 MF.getRegInfo().addLiveIn(PReg, VReg);
541 // Get fp branch code (not opcode) from condition code.
542 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
543 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
544 return Mips::BRANCH_T;
546 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
547 return Mips::BRANCH_F;
549 return Mips::BRANCH_INVALID;
553 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
554 MachineBasicBlock *BB) const {
555 // There is no need to expand CMov instructions if target has
556 // conditional moves.
557 if (Subtarget->hasCondMov())
560 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
561 bool isFPCmp = false;
562 DebugLoc dl = MI->getDebugLoc();
565 switch (MI->getOpcode()) {
566 default: assert(false && "Unexpected instr type to insert");
591 // To "insert" a SELECT_CC instruction, we actually have to insert the
592 // diamond control-flow pattern. The incoming instruction knows the
593 // destination vreg to set, the condition code register to branch on, the
594 // true/false values to select between, and a branch opcode to use.
595 const BasicBlock *LLVM_BB = BB->getBasicBlock();
596 MachineFunction::iterator It = BB;
603 // bNE r1, r0, copy1MBB
604 // fallthrough --> copy0MBB
605 MachineBasicBlock *thisMBB = BB;
606 MachineFunction *F = BB->getParent();
607 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
608 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
609 F->insert(It, copy0MBB);
610 F->insert(It, sinkMBB);
612 // Transfer the remainder of BB and its successor edges to sinkMBB.
613 sinkMBB->splice(sinkMBB->begin(), BB,
614 llvm::next(MachineBasicBlock::iterator(MI)),
616 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
618 // Next, add the true and fallthrough blocks as its successors.
619 BB->addSuccessor(copy0MBB);
620 BB->addSuccessor(sinkMBB);
622 // Emit the right instruction according to the type of the operands compared
624 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
626 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
627 .addReg(Mips::ZERO).addMBB(sinkMBB);
632 // # fallthrough to sinkMBB
635 // Update machine-CFG edges
636 BB->addSuccessor(sinkMBB);
639 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
644 BuildMI(*BB, BB->begin(), dl,
645 TII->get(Mips::PHI), MI->getOperand(0).getReg())
646 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
647 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
649 BuildMI(*BB, BB->begin(), dl,
650 TII->get(Mips::PHI), MI->getOperand(0).getReg())
651 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
652 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
654 MI->eraseFromParent(); // The pseudo instruction is gone now.
658 //===----------------------------------------------------------------------===//
659 // Misc Lower Operation implementation
660 //===----------------------------------------------------------------------===//
661 SDValue MipsTargetLowering::
662 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
664 unsigned StackAlignment =
665 getTargetMachine().getFrameLowering()->getStackAlignment();
666 assert(StackAlignment >=
667 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() &&
668 "Cannot lower if the alignment of the allocated space is larger than \
669 that of the stack.");
671 SDValue Chain = Op.getOperand(0);
672 SDValue Size = Op.getOperand(1);
673 DebugLoc dl = Op.getDebugLoc();
675 // Get a reference from Mips stack pointer
676 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
678 // Subtract the dynamic size from the actual stack size to
679 // obtain the new stack size.
680 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
682 // The Sub result contains the new stack start address, so it
683 // must be placed in the stack pointer register.
684 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub,
686 // Retrieve updated $sp. There is a glue input to prevent instructions that
687 // clobber $sp from being inserted between copytoreg and copyfromreg.
688 SDValue NewSP = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32,
691 // The stack space reserved by alloca is located right above the argument
692 // area. It is aligned on a boundary that is a multiple of StackAlignment.
693 MachineFunction &MF = DAG.getMachineFunction();
694 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
695 unsigned SPOffset = (MipsFI->getMaxCallFrameSize() + StackAlignment - 1) /
696 StackAlignment * StackAlignment;
697 SDValue AllocPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
698 DAG.getConstant(SPOffset, MVT::i32));
700 // This node always has two return values: a new stack pointer
702 SDValue Ops[2] = { AllocPtr, NewSP.getValue(1) };
703 return DAG.getMergeValues(Ops, 2, dl);
706 SDValue MipsTargetLowering::
707 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
709 // The first operand is the chain, the second is the condition, the third is
710 // the block to branch to if the condition is true.
711 SDValue Chain = Op.getOperand(0);
712 SDValue Dest = Op.getOperand(2);
713 DebugLoc dl = Op.getDebugLoc();
715 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
717 // Return if flag is not set by a floating point comparison.
718 if (CondRes.getOpcode() != MipsISD::FPCmp)
721 SDValue CCNode = CondRes.getOperand(2);
723 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
724 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
726 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
730 SDValue MipsTargetLowering::
731 LowerSELECT(SDValue Op, SelectionDAG &DAG) const
733 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
735 // Return if flag is not set by a floating point comparison.
736 if (Cond.getOpcode() != MipsISD::FPCmp)
739 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
743 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
744 SelectionDAG &DAG) const {
745 // FIXME there isn't actually debug info here
746 DebugLoc dl = Op.getDebugLoc();
747 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
749 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
750 SDVTList VTs = DAG.getVTList(MVT::i32);
752 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
754 // %gp_rel relocation
755 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
756 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
758 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
759 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
760 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
762 // %hi/%lo relocation
763 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
765 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
767 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
768 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
769 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
771 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
773 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
774 DAG.getEntryNode(), GA, MachinePointerInfo(),
776 // On functions and global targets not internal linked only
777 // a load from got/GP is necessary for PIC to work.
778 if (!GV->hasInternalLinkage() &&
779 (!GV->hasLocalLinkage() || isa<Function>(GV)))
781 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
783 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
784 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
787 llvm_unreachable("Dont know how to handle GlobalAddress");
791 SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
792 SelectionDAG &DAG) const {
793 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
794 // FIXME there isn't actually debug info here
795 DebugLoc dl = Op.getDebugLoc();
797 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
798 // %hi/%lo relocation
799 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true,
801 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true,
803 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
804 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
805 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
808 SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true,
810 SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true,
812 SDValue Load = DAG.getLoad(MVT::i32, dl,
813 DAG.getEntryNode(), BAGOTOffset,
814 MachinePointerInfo(), false, false, 0);
815 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset);
816 return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
819 SDValue MipsTargetLowering::
820 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
822 llvm_unreachable("TLS not implemented for MIPS.");
823 return SDValue(); // Not reached
826 SDValue MipsTargetLowering::
827 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
831 // FIXME there isn't actually debug info here
832 DebugLoc dl = Op.getDebugLoc();
833 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
834 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI;
836 EVT PtrVT = Op.getValueType();
837 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
839 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
842 SDValue Ops[] = { JTI };
843 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
844 } else // Emit Load from Global Pointer
845 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI,
846 MachinePointerInfo(),
849 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
851 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo);
852 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
857 SDValue MipsTargetLowering::
858 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
861 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
862 const Constant *C = N->getConstVal();
863 // FIXME there isn't actually debug info here
864 DebugLoc dl = Op.getDebugLoc();
867 // FIXME: we should reference the constant pool using small data sections,
868 // but the asm printer currently doesn't support this feature without
869 // hacking it. This feature should come soon so we can uncomment the
871 //if (IsInSmallSection(C->getType())) {
872 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
873 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
874 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
876 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
877 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
878 N->getOffset(), MipsII::MO_ABS_HI);
879 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
880 N->getOffset(), MipsII::MO_ABS_LO);
881 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
882 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
883 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
885 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
886 N->getOffset(), MipsII::MO_GOT);
887 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(),
888 CP, MachinePointerInfo::getConstantPool(),
890 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
891 N->getOffset(), MipsII::MO_ABS_LO);
892 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
893 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
899 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
900 MachineFunction &MF = DAG.getMachineFunction();
901 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
903 DebugLoc dl = Op.getDebugLoc();
904 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
907 // vastart just stores the address of the VarArgsFrameIndex slot into the
908 // memory location argument.
909 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
910 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
911 MachinePointerInfo(SV),
915 static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG) {
916 // FIXME: Use ext/ins instructions if target architecture is Mips32r2.
917 DebugLoc dl = Op.getDebugLoc();
918 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0));
919 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1));
920 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op0,
921 DAG.getConstant(0x7fffffff, MVT::i32));
922 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op1,
923 DAG.getConstant(0x80000000, MVT::i32));
924 SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1);
925 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Result);
928 static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool isLittle) {
930 // Use ext/ins instructions if target architecture is Mips32r2.
931 // Eliminate redundant mfc1 and mtc1 instructions.
932 unsigned LoIdx = 0, HiIdx = 1;
935 std::swap(LoIdx, HiIdx);
937 DebugLoc dl = Op.getDebugLoc();
938 SDValue Word0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
940 DAG.getConstant(LoIdx, MVT::i32));
941 SDValue Hi0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
942 Op.getOperand(0), DAG.getConstant(HiIdx, MVT::i32));
943 SDValue Hi1 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
944 Op.getOperand(1), DAG.getConstant(HiIdx, MVT::i32));
945 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi0,
946 DAG.getConstant(0x7fffffff, MVT::i32));
947 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi1,
948 DAG.getConstant(0x80000000, MVT::i32));
949 SDValue Word1 = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1);
952 std::swap(Word0, Word1);
954 return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1);
957 SDValue MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)
959 EVT Ty = Op.getValueType();
961 assert(Ty == MVT::f32 || Ty == MVT::f64);
964 return LowerFCOPYSIGN32(Op, DAG);
966 return LowerFCOPYSIGN64(Op, DAG, Subtarget->isLittle());
969 //===----------------------------------------------------------------------===//
970 // Calling Convention Implementation
971 //===----------------------------------------------------------------------===//
973 #include "MipsGenCallingConv.inc"
975 //===----------------------------------------------------------------------===//
976 // TODO: Implement a generic logic using tblgen that can support this.
977 // Mips O32 ABI rules:
979 // i32 - Passed in A0, A1, A2, A3 and stack
980 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
981 // an argument. Otherwise, passed in A1, A2, A3 and stack.
982 // f64 - Only passed in two aliased f32 registers if no int reg has been used
983 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
984 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
987 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
988 //===----------------------------------------------------------------------===//
990 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
991 MVT LocVT, CCValAssign::LocInfo LocInfo,
992 ISD::ArgFlagsTy ArgFlags, CCState &State) {
994 static const unsigned IntRegsSize=4, FloatRegsSize=2;
996 static const unsigned IntRegs[] = {
997 Mips::A0, Mips::A1, Mips::A2, Mips::A3
999 static const unsigned F32Regs[] = {
1000 Mips::F12, Mips::F14
1002 static const unsigned F64Regs[] = {
1007 if (ArgFlags.isByVal()) {
1008 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo,
1009 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags);
1010 unsigned NextReg = (State.getNextStackOffset() + 3) / 4;
1011 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize);
1012 r < std::min(IntRegsSize, NextReg); ++r)
1013 State.AllocateReg(IntRegs[r]);
1017 // Promote i8 and i16
1018 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
1020 if (ArgFlags.isSExt())
1021 LocInfo = CCValAssign::SExt;
1022 else if (ArgFlags.isZExt())
1023 LocInfo = CCValAssign::ZExt;
1025 LocInfo = CCValAssign::AExt;
1030 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
1031 // is true: function is vararg, argument is 3rd or higher, there is previous
1032 // argument which is not f32 or f64.
1033 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
1034 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
1035 unsigned OrigAlign = ArgFlags.getOrigAlign();
1036 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
1038 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
1039 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1040 // If this is the first part of an i64 arg,
1041 // the allocated register must be either A0 or A2.
1042 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
1043 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1045 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
1046 // Allocate int register and shadow next int register. If first
1047 // available register is Mips::A1 or Mips::A3, shadow it too.
1048 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1049 if (Reg == Mips::A1 || Reg == Mips::A3)
1050 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1051 State.AllocateReg(IntRegs, IntRegsSize);
1053 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
1054 // we are guaranteed to find an available float register
1055 if (ValVT == MVT::f32) {
1056 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
1057 // Shadow int register
1058 State.AllocateReg(IntRegs, IntRegsSize);
1060 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
1061 // Shadow int registers
1062 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
1063 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
1064 State.AllocateReg(IntRegs, IntRegsSize);
1065 State.AllocateReg(IntRegs, IntRegsSize);
1068 llvm_unreachable("Cannot handle this ValVT.");
1070 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
1071 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign);
1074 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
1076 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1078 return false; // CC must always match
1081 //===----------------------------------------------------------------------===//
1082 // Call Calling Convention Implementation
1083 //===----------------------------------------------------------------------===//
1085 static const unsigned O32IntRegsSize = 4;
1087 static const unsigned O32IntRegs[] = {
1088 Mips::A0, Mips::A1, Mips::A2, Mips::A3
1091 // Write ByVal Arg to arg registers and stack.
1093 WriteByValArg(SDValue& Chain, DebugLoc dl,
1094 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass,
1095 SmallVector<SDValue, 8>& MemOpChains, int& LastFI,
1096 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
1097 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
1099 unsigned FirstWord = VA.getLocMemOffset() / 4;
1100 unsigned NumWords = (Flags.getByValSize() + 3) / 4;
1101 unsigned LastWord = FirstWord + NumWords;
1104 // copy the first 4 words of byval arg to registers A0 - A3
1105 for (CurWord = FirstWord; CurWord < std::min(LastWord, O32IntRegsSize);
1107 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
1108 DAG.getConstant((CurWord - FirstWord) * 4,
1110 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr,
1111 MachinePointerInfo(),
1113 MemOpChains.push_back(LoadVal.getValue(1));
1114 unsigned DstReg = O32IntRegs[CurWord];
1115 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
1118 // copy remaining part of byval arg to stack.
1119 if (CurWord < LastWord) {
1120 unsigned SizeInBytes = (LastWord - CurWord) * 4;
1121 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
1122 DAG.getConstant((CurWord - FirstWord) * 4,
1124 LastFI = MFI->CreateFixedObject(SizeInBytes, CurWord * 4, true);
1125 SDValue Dst = DAG.getFrameIndex(LastFI, PtrType);
1126 Chain = DAG.getMemcpy(Chain, dl, Dst, Src,
1127 DAG.getConstant(SizeInBytes, MVT::i32),
1129 /*isVolatile=*/false, /*AlwaysInline=*/false,
1130 MachinePointerInfo(0), MachinePointerInfo(0));
1131 MemOpChains.push_back(Chain);
1135 /// LowerCall - functions arguments are copied from virtual regs to
1136 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
1137 /// TODO: isTailCall.
1139 MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1140 CallingConv::ID CallConv, bool isVarArg,
1142 const SmallVectorImpl<ISD::OutputArg> &Outs,
1143 const SmallVectorImpl<SDValue> &OutVals,
1144 const SmallVectorImpl<ISD::InputArg> &Ins,
1145 DebugLoc dl, SelectionDAG &DAG,
1146 SmallVectorImpl<SDValue> &InVals) const {
1147 // MIPs target does not yet support tail call optimization.
1150 MachineFunction &MF = DAG.getMachineFunction();
1151 MachineFrameInfo *MFI = MF.getFrameInfo();
1152 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
1153 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1154 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1156 // Analyze operands of the call, assigning locations to each operand.
1157 SmallVector<CCValAssign, 16> ArgLocs;
1158 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1161 if (Subtarget->isABI_O32())
1162 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
1164 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
1166 // Get a count of how many bytes are to be pushed on the stack.
1167 unsigned NumBytes = CCInfo.getNextStackOffset();
1168 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1170 // With EABI is it possible to have 16 args on registers.
1171 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
1172 SmallVector<SDValue, 8> MemOpChains;
1174 // If this is the first call, create a stack frame object that points to
1175 // a location to which .cprestore saves $gp. The offset of this frame object
1176 // is set to 0, since we know nothing about the size of the argument area at
1178 if (IsPIC && !MipsFI->getGPFI())
1179 MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true));
1181 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0;
1183 // Walk the register/memloc assignments, inserting copies/loads.
1184 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1185 SDValue Arg = OutVals[i];
1186 CCValAssign &VA = ArgLocs[i];
1188 // Promote the value if needed.
1189 switch (VA.getLocInfo()) {
1190 default: llvm_unreachable("Unknown loc info!");
1191 case CCValAssign::Full:
1192 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
1193 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
1194 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
1195 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
1196 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1197 Arg, DAG.getConstant(0, MVT::i32));
1198 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1199 Arg, DAG.getConstant(1, MVT::i32));
1200 if (!Subtarget->isLittle())
1202 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
1203 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
1208 case CCValAssign::SExt:
1209 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1211 case CCValAssign::ZExt:
1212 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1214 case CCValAssign::AExt:
1215 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1219 // Arguments that can be passed on register must be kept at
1220 // RegsToPass vector
1221 if (VA.isRegLoc()) {
1222 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1226 // Register can't get to this point...
1227 assert(VA.isMemLoc());
1230 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1231 if (Flags.isByVal()) {
1232 assert(Subtarget->isABI_O32() &&
1233 "No support for ByVal args by ABIs other than O32 yet.");
1234 assert(Flags.getByValSize() &&
1235 "ByVal args of size 0 should have been ignored by front-end.");
1236 WriteByValArg(Chain, dl, RegsToPass, MemOpChains, LastFI, MFI, DAG, Arg,
1237 VA, Flags, getPointerTy());
1241 // Create the frame index object for this incoming parameter
1242 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1243 VA.getLocMemOffset(), true);
1244 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
1246 // emit ISD::STORE whichs stores the
1247 // parameter value to a stack Location
1248 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
1249 MachinePointerInfo(),
1253 // Transform all store nodes into one single node because all store
1254 // nodes are independent of each other.
1255 if (!MemOpChains.empty())
1256 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1257 &MemOpChains[0], MemOpChains.size());
1259 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1260 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1261 // node so that legalize doesn't hack it.
1262 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
1263 bool LoadSymAddr = false;
1266 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1267 if (IsPIC && G->getGlobal()->hasInternalLinkage()) {
1268 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
1269 getPointerTy(), 0,MipsII:: MO_GOT);
1270 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
1271 0, MipsII::MO_ABS_LO);
1273 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
1274 getPointerTy(), 0, OpFlag);
1279 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1280 Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
1281 getPointerTy(), OpFlag);
1287 // Create nodes that load address of callee and copy it to T9
1290 // Load callee address
1291 SDValue LoadValue = DAG.getLoad(MVT::i32, dl, Chain, Callee,
1292 MachinePointerInfo::getGOT(),
1295 // Use GOT+LO if callee has internal linkage.
1296 if (CalleeLo.getNode()) {
1297 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CalleeLo);
1298 Callee = DAG.getNode(ISD::ADD, dl, MVT::i32, LoadValue, Lo);
1302 // Use chain output from LoadValue
1303 Chain = LoadValue.getValue(1);
1307 Chain = DAG.getCopyToReg(Chain, dl, Mips::T9, Callee, SDValue(0, 0));
1308 InFlag = Chain.getValue(1);
1309 Callee = DAG.getRegister(Mips::T9, MVT::i32);
1312 // Build a sequence of copy-to-reg nodes chained together with token
1313 // chain and flag operands which copy the outgoing args into registers.
1314 // The InFlag in necessary since all emitted instructions must be
1316 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1317 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1318 RegsToPass[i].second, InFlag);
1319 InFlag = Chain.getValue(1);
1322 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
1323 // = Chain, Callee, Reg#1, Reg#2, ...
1325 // Returns a chain & a flag for retval copy to use.
1326 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1327 SmallVector<SDValue, 8> Ops;
1328 Ops.push_back(Chain);
1329 Ops.push_back(Callee);
1331 // Add argument registers to the end of the list so that they are
1332 // known live into the call.
1333 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1334 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1335 RegsToPass[i].second.getValueType()));
1337 if (InFlag.getNode())
1338 Ops.push_back(InFlag);
1340 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
1341 InFlag = Chain.getValue(1);
1343 // Function can have an arbitrary number of calls, so
1344 // hold the LastArgStackLoc with the biggest offset.
1345 unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize();
1346 unsigned NextStackOffset = CCInfo.getNextStackOffset();
1348 // For O32, a minimum of four words (16 bytes) of argument space is
1350 if (Subtarget->isABI_O32())
1351 NextStackOffset = std::max(NextStackOffset, (unsigned)16);
1353 if (MaxCallFrameSize < NextStackOffset) {
1354 MipsFI->setMaxCallFrameSize(NextStackOffset);
1357 // $gp restore slot must be aligned.
1358 unsigned StackAlignment = TFL->getStackAlignment();
1359 NextStackOffset = (NextStackOffset + StackAlignment - 1) /
1360 StackAlignment * StackAlignment;
1361 int GPFI = MipsFI->getGPFI();
1362 MFI->setObjectOffset(GPFI, NextStackOffset);
1366 // Extend range of indices of frame objects for outgoing arguments that were
1367 // created during this function call. Skip this step if no such objects were
1370 MipsFI->extendOutArgFIRange(FirstFI, LastFI);
1372 // Create the CALLSEQ_END node.
1373 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1374 DAG.getIntPtrConstant(0, true), InFlag);
1375 InFlag = Chain.getValue(1);
1377 // Handle result values, copying them out of physregs into vregs that we
1379 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
1380 Ins, dl, DAG, InVals);
1383 /// LowerCallResult - Lower the result values of a call into the
1384 /// appropriate copies out of appropriate physical registers.
1386 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1387 CallingConv::ID CallConv, bool isVarArg,
1388 const SmallVectorImpl<ISD::InputArg> &Ins,
1389 DebugLoc dl, SelectionDAG &DAG,
1390 SmallVectorImpl<SDValue> &InVals) const {
1392 // Assign locations to each value returned by this call.
1393 SmallVector<CCValAssign, 16> RVLocs;
1394 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1395 RVLocs, *DAG.getContext());
1397 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
1399 // Copy all of the result registers out of their specified physreg.
1400 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1401 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
1402 RVLocs[i].getValVT(), InFlag).getValue(1);
1403 InFlag = Chain.getValue(2);
1404 InVals.push_back(Chain.getValue(0));
1410 //===----------------------------------------------------------------------===//
1411 // Formal Arguments Calling Convention Implementation
1412 //===----------------------------------------------------------------------===//
1413 static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl,
1414 std::vector<SDValue>& OutChains,
1415 SelectionDAG &DAG, unsigned NumWords, SDValue FIN,
1416 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags) {
1417 unsigned LocMem = VA.getLocMemOffset();
1418 unsigned FirstWord = LocMem / 4;
1420 // copy register A0 - A3 to frame object
1421 for (unsigned i = 0; i < NumWords; ++i) {
1422 unsigned CurWord = FirstWord + i;
1423 if (CurWord >= O32IntRegsSize)
1426 unsigned SrcReg = O32IntRegs[CurWord];
1427 unsigned Reg = AddLiveIn(MF, SrcReg, Mips::CPURegsRegisterClass);
1428 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN,
1429 DAG.getConstant(i * 4, MVT::i32));
1430 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32),
1431 StorePtr, MachinePointerInfo(), false,
1433 OutChains.push_back(Store);
1437 /// LowerFormalArguments - transform physical registers into virtual registers
1438 /// and generate load operations for arguments places on the stack.
1440 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
1441 CallingConv::ID CallConv,
1443 const SmallVectorImpl<ISD::InputArg>
1445 DebugLoc dl, SelectionDAG &DAG,
1446 SmallVectorImpl<SDValue> &InVals)
1448 MachineFunction &MF = DAG.getMachineFunction();
1449 MachineFrameInfo *MFI = MF.getFrameInfo();
1450 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1452 MipsFI->setVarArgsFrameIndex(0);
1454 // Used with vargs to acumulate store chains.
1455 std::vector<SDValue> OutChains;
1457 // Assign locations to all of the incoming arguments.
1458 SmallVector<CCValAssign, 16> ArgLocs;
1459 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1460 ArgLocs, *DAG.getContext());
1462 if (Subtarget->isABI_O32())
1463 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
1465 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
1467 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function.
1469 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1470 CCValAssign &VA = ArgLocs[i];
1472 // Arguments stored on registers
1473 if (VA.isRegLoc()) {
1474 EVT RegVT = VA.getLocVT();
1475 unsigned ArgReg = VA.getLocReg();
1476 TargetRegisterClass *RC = 0;
1478 if (RegVT == MVT::i32)
1479 RC = Mips::CPURegsRegisterClass;
1480 else if (RegVT == MVT::f32)
1481 RC = Mips::FGR32RegisterClass;
1482 else if (RegVT == MVT::f64) {
1483 if (!Subtarget->isSingleFloat())
1484 RC = Mips::AFGR64RegisterClass;
1486 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
1488 // Transform the arguments stored on
1489 // physical registers into virtual ones
1490 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
1491 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1493 // If this is an 8 or 16-bit value, it has been passed promoted
1494 // to 32 bits. Insert an assert[sz]ext to capture this, then
1495 // truncate to the right size.
1496 if (VA.getLocInfo() != CCValAssign::Full) {
1497 unsigned Opcode = 0;
1498 if (VA.getLocInfo() == CCValAssign::SExt)
1499 Opcode = ISD::AssertSext;
1500 else if (VA.getLocInfo() == CCValAssign::ZExt)
1501 Opcode = ISD::AssertZext;
1503 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
1504 DAG.getValueType(VA.getValVT()));
1505 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1508 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
1509 if (Subtarget->isABI_O32()) {
1510 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
1511 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue);
1512 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
1513 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
1514 VA.getLocReg()+1, RC);
1515 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
1516 if (!Subtarget->isLittle())
1517 std::swap(ArgValue, ArgValue2);
1518 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
1519 ArgValue, ArgValue2);
1523 InVals.push_back(ArgValue);
1524 } else { // VA.isRegLoc()
1527 assert(VA.isMemLoc());
1529 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1531 if (Flags.isByVal()) {
1532 assert(Subtarget->isABI_O32() &&
1533 "No support for ByVal args by ABIs other than O32 yet.");
1534 assert(Flags.getByValSize() &&
1535 "ByVal args of size 0 should have been ignored by front-end.");
1536 unsigned NumWords = (Flags.getByValSize() + 3) / 4;
1537 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(),
1539 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
1540 InVals.push_back(FIN);
1541 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags);
1546 // The stack pointer offset is relative to the caller stack frame.
1547 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1548 VA.getLocMemOffset(), true);
1550 // Create load nodes to retrieve arguments from the stack
1551 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
1552 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1553 MachinePointerInfo::getFixedStack(LastFI),
1558 // The mips ABIs for returning structs by value requires that we copy
1559 // the sret argument into $v0 for the return. Save the argument into
1560 // a virtual register so that we can access it from the return points.
1561 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1562 unsigned Reg = MipsFI->getSRetReturnReg();
1564 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1565 MipsFI->setSRetReturnReg(Reg);
1567 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1568 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1571 if (isVarArg && Subtarget->isABI_O32()) {
1572 // Record the frame index of the first variable argument
1573 // which is a value necessary to VASTART.
1574 unsigned NextStackOffset = CCInfo.getNextStackOffset();
1575 assert(NextStackOffset % 4 == 0 &&
1576 "NextStackOffset must be aligned to 4-byte boundaries.");
1577 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true);
1578 MipsFI->setVarArgsFrameIndex(LastFI);
1580 // If NextStackOffset is smaller than o32's 16-byte reserved argument area,
1581 // copy the integer registers that have not been used for argument passing
1582 // to the caller's stack frame.
1583 for (; NextStackOffset < 16; NextStackOffset += 4) {
1584 TargetRegisterClass *RC = Mips::CPURegsRegisterClass;
1585 unsigned Idx = NextStackOffset / 4;
1586 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), O32IntRegs[Idx], RC);
1587 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
1588 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true);
1589 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
1590 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
1591 MachinePointerInfo(),
1596 MipsFI->setLastInArgFI(LastFI);
1598 // All stores are grouped in one node to allow the matching between
1599 // the size of Ins and InVals. This only happens when on varg functions
1600 if (!OutChains.empty()) {
1601 OutChains.push_back(Chain);
1602 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1603 &OutChains[0], OutChains.size());
1609 //===----------------------------------------------------------------------===//
1610 // Return Value Calling Convention Implementation
1611 //===----------------------------------------------------------------------===//
1614 MipsTargetLowering::LowerReturn(SDValue Chain,
1615 CallingConv::ID CallConv, bool isVarArg,
1616 const SmallVectorImpl<ISD::OutputArg> &Outs,
1617 const SmallVectorImpl<SDValue> &OutVals,
1618 DebugLoc dl, SelectionDAG &DAG) const {
1620 // CCValAssign - represent the assignment of
1621 // the return value to a location
1622 SmallVector<CCValAssign, 16> RVLocs;
1624 // CCState - Info about the registers and stack slot.
1625 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1626 RVLocs, *DAG.getContext());
1628 // Analize return values.
1629 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
1631 // If this is the first return lowered for this function, add
1632 // the regs to the liveout set for the function.
1633 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1634 for (unsigned i = 0; i != RVLocs.size(); ++i)
1635 if (RVLocs[i].isRegLoc())
1636 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1641 // Copy the result values into the output registers.
1642 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1643 CCValAssign &VA = RVLocs[i];
1644 assert(VA.isRegLoc() && "Can only return in registers!");
1646 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1649 // guarantee that all emitted copies are
1650 // stuck together, avoiding something bad
1651 Flag = Chain.getValue(1);
1654 // The mips ABIs for returning structs by value requires that we copy
1655 // the sret argument into $v0 for the return. We saved the argument into
1656 // a virtual register in the entry block, so now we copy the value out
1658 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1659 MachineFunction &MF = DAG.getMachineFunction();
1660 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1661 unsigned Reg = MipsFI->getSRetReturnReg();
1664 llvm_unreachable("sret virtual register not created in the entry block");
1665 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1667 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1668 Flag = Chain.getValue(1);
1671 // Return on Mips is always a "jr $ra"
1673 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1674 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1676 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1677 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1680 //===----------------------------------------------------------------------===//
1681 // Mips Inline Assembly Support
1682 //===----------------------------------------------------------------------===//
1684 /// getConstraintType - Given a constraint letter, return the type of
1685 /// constraint it is for this target.
1686 MipsTargetLowering::ConstraintType MipsTargetLowering::
1687 getConstraintType(const std::string &Constraint) const
1689 // Mips specific constrainy
1690 // GCC config/mips/constraints.md
1692 // 'd' : An address register. Equivalent to r
1693 // unless generating MIPS16 code.
1694 // 'y' : Equivalent to r; retained for
1695 // backwards compatibility.
1696 // 'f' : Floating Point registers.
1697 if (Constraint.size() == 1) {
1698 switch (Constraint[0]) {
1703 return C_RegisterClass;
1707 return TargetLowering::getConstraintType(Constraint);
1710 /// Examine constraint type and operand type and determine a weight value.
1711 /// This object must already have been set up with the operand type
1712 /// and the current alternative constraint selected.
1713 TargetLowering::ConstraintWeight
1714 MipsTargetLowering::getSingleConstraintMatchWeight(
1715 AsmOperandInfo &info, const char *constraint) const {
1716 ConstraintWeight weight = CW_Invalid;
1717 Value *CallOperandVal = info.CallOperandVal;
1718 // If we don't have a value, we can't do a match,
1719 // but allow it at the lowest weight.
1720 if (CallOperandVal == NULL)
1722 const Type *type = CallOperandVal->getType();
1723 // Look at the constraint type.
1724 switch (*constraint) {
1726 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1730 if (type->isIntegerTy())
1731 weight = CW_Register;
1734 if (type->isFloatTy())
1735 weight = CW_Register;
1741 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1742 /// return a list of registers that can be used to satisfy the constraint.
1743 /// This should only be used for C_RegisterClass constraints.
1744 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1745 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
1747 if (Constraint.size() == 1) {
1748 switch (Constraint[0]) {
1750 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1753 return std::make_pair(0U, Mips::FGR32RegisterClass);
1755 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1756 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1759 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1762 /// Given a register class constraint, like 'r', if this corresponds directly
1763 /// to an LLVM register class, return a register of 0 and the register class
1765 std::vector<unsigned> MipsTargetLowering::
1766 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1769 if (Constraint.size() != 1)
1770 return std::vector<unsigned>();
1772 switch (Constraint[0]) {
1775 // GCC Mips Constraint Letters
1778 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1779 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1780 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1784 if (VT == MVT::f32) {
1785 if (Subtarget->isSingleFloat())
1786 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1787 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1788 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1789 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1790 Mips::F30, Mips::F31, 0);
1792 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1793 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1794 Mips::F28, Mips::F30, 0);
1798 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1799 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1800 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1801 Mips::D14, Mips::D15, 0);
1803 return std::vector<unsigned>();
1807 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1808 // The Mips target isn't yet aware of offsets.
1812 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
1813 if (VT != MVT::f32 && VT != MVT::f64)
1815 if (Imm.isNegZero())
1817 return Imm.isZero();