1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "MipsTargetObjectFile.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
37 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
39 case MipsISD::JmpLink : return "MipsISD::JmpLink";
40 case MipsISD::Hi : return "MipsISD::Hi";
41 case MipsISD::Lo : return "MipsISD::Lo";
42 case MipsISD::GPRel : return "MipsISD::GPRel";
43 case MipsISD::Ret : return "MipsISD::Ret";
44 case MipsISD::CMov : return "MipsISD::CMov";
45 case MipsISD::SelectCC : return "MipsISD::SelectCC";
46 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
47 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
48 case MipsISD::FPCmp : return "MipsISD::FPCmp";
49 case MipsISD::FPRound : return "MipsISD::FPRound";
50 default : return NULL;
55 MipsTargetLowering(MipsTargetMachine &TM)
56 : TargetLowering(TM, new MipsTargetObjectFile()) {
57 Subtarget = &TM.getSubtarget<MipsSubtarget>();
59 // Mips does not have i1 type, so use i32 for
60 // setcc operations results (slt, sgt, ...).
61 setBooleanContents(ZeroOrOneBooleanContent);
63 // JumpTable targets must use GOT when using PIC_
64 setUsesGlobalOffsetTable(true);
66 // Set up the register classes
67 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
68 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
70 // When dealing with single precision only, use libcalls
71 if (!Subtarget->isSingleFloat())
72 if (!Subtarget->isFP64bit())
73 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
76 addLegalFPImmediate(APFloat(+0.0f));
78 // Load extented operations for i1 types must be promoted
79 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
80 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
83 // MIPS doesn't have extending float->double load/store
84 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
85 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
87 // Used by legalize types to correctly generate the setcc result.
88 // Without this, every float setcc comes with a AND/OR with the result,
89 // we don't want this, since the fpcmp result goes to a flag register,
90 // which is used implicitly by brcond and select operations.
91 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
93 // Mips Custom Operations
94 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
95 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
96 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
97 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
98 setOperationAction(ISD::SELECT, MVT::f32, Custom);
99 setOperationAction(ISD::SELECT, MVT::f64, Custom);
100 setOperationAction(ISD::SELECT, MVT::i32, Custom);
101 setOperationAction(ISD::SETCC, MVT::f32, Custom);
102 setOperationAction(ISD::SETCC, MVT::f64, Custom);
103 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
104 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
105 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
107 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
108 // with operands comming from setcc fp comparions. This is necessary since
109 // the result from these setcc are in a flag registers (FCR31).
110 setOperationAction(ISD::AND, MVT::i32, Custom);
111 setOperationAction(ISD::OR, MVT::i32, Custom);
113 // Operations not directly supported by Mips.
114 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
115 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
116 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
117 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
118 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
120 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
121 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
122 setOperationAction(ISD::ROTL, MVT::i32, Expand);
123 setOperationAction(ISD::ROTR, MVT::i32, Expand);
124 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
125 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
126 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
127 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
128 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
129 setOperationAction(ISD::FSIN, MVT::f32, Expand);
130 setOperationAction(ISD::FCOS, MVT::f32, Expand);
131 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
132 setOperationAction(ISD::FPOW, MVT::f32, Expand);
133 setOperationAction(ISD::FLOG, MVT::f32, Expand);
134 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
135 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
136 setOperationAction(ISD::FEXP, MVT::f32, Expand);
138 // We don't have line number support yet.
139 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
140 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
141 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
142 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
144 // Use the default for now
145 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
146 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
147 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
149 if (Subtarget->isSingleFloat())
150 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
152 if (!Subtarget->hasSEInReg()) {
153 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
154 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
157 if (!Subtarget->hasBitCount())
158 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
160 if (!Subtarget->hasSwap())
161 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
163 setStackPointerRegisterToSaveRestore(Mips::SP);
164 computeRegisterProperties();
167 MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
171 /// getFunctionAlignment - Return the Log2 alignment of this function.
172 unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const {
176 SDValue MipsTargetLowering::
177 LowerOperation(SDValue Op, SelectionDAG &DAG)
179 switch (Op.getOpcode())
181 case ISD::AND: return LowerANDOR(Op, DAG);
182 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
183 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
184 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
185 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
186 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
187 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
188 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
189 case ISD::OR: return LowerANDOR(Op, DAG);
190 case ISD::SELECT: return LowerSELECT(Op, DAG);
191 case ISD::SETCC: return LowerSETCC(Op, DAG);
196 //===----------------------------------------------------------------------===//
197 // Lower helper functions
198 //===----------------------------------------------------------------------===//
200 // AddLiveIn - This helper function adds the specified physical register to the
201 // MachineFunction as a live in value. It also creates a corresponding
202 // virtual register for it.
204 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
206 assert(RC->contains(PReg) && "Not the correct regclass!");
207 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
208 MF.getRegInfo().addLiveIn(PReg, VReg);
212 // Get fp branch code (not opcode) from condition code.
213 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
214 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
215 return Mips::BRANCH_T;
217 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
218 return Mips::BRANCH_F;
220 return Mips::BRANCH_INVALID;
223 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
226 llvm_unreachable("Unknown branch code");
227 case Mips::BRANCH_T : return Mips::BC1T;
228 case Mips::BRANCH_F : return Mips::BC1F;
229 case Mips::BRANCH_TL : return Mips::BC1TL;
230 case Mips::BRANCH_FL : return Mips::BC1FL;
234 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
236 default: llvm_unreachable("Unknown fp condition code!");
238 case ISD::SETOEQ: return Mips::FCOND_EQ;
239 case ISD::SETUNE: return Mips::FCOND_OGL;
241 case ISD::SETOLT: return Mips::FCOND_OLT;
243 case ISD::SETOGT: return Mips::FCOND_OGT;
245 case ISD::SETOLE: return Mips::FCOND_OLE;
247 case ISD::SETOGE: return Mips::FCOND_OGE;
248 case ISD::SETULT: return Mips::FCOND_ULT;
249 case ISD::SETULE: return Mips::FCOND_ULE;
250 case ISD::SETUGT: return Mips::FCOND_UGT;
251 case ISD::SETUGE: return Mips::FCOND_UGE;
252 case ISD::SETUO: return Mips::FCOND_UN;
253 case ISD::SETO: return Mips::FCOND_OR;
255 case ISD::SETONE: return Mips::FCOND_NEQ;
256 case ISD::SETUEQ: return Mips::FCOND_UEQ;
261 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
262 MachineBasicBlock *BB,
263 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
264 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
265 bool isFPCmp = false;
266 DebugLoc dl = MI->getDebugLoc();
268 switch (MI->getOpcode()) {
269 default: assert(false && "Unexpected instr type to insert");
270 case Mips::Select_FCC:
271 case Mips::Select_FCC_S32:
272 case Mips::Select_FCC_D32:
273 isFPCmp = true; // FALL THROUGH
274 case Mips::Select_CC:
275 case Mips::Select_CC_S32:
276 case Mips::Select_CC_D32: {
277 // To "insert" a SELECT_CC instruction, we actually have to insert the
278 // diamond control-flow pattern. The incoming instruction knows the
279 // destination vreg to set, the condition code register to branch on, the
280 // true/false values to select between, and a branch opcode to use.
281 const BasicBlock *LLVM_BB = BB->getBasicBlock();
282 MachineFunction::iterator It = BB;
289 // bNE r1, r0, copy1MBB
290 // fallthrough --> copy0MBB
291 MachineBasicBlock *thisMBB = BB;
292 MachineFunction *F = BB->getParent();
293 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
294 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
296 // Emit the right instruction according to the type of the operands compared
298 // Find the condiction code present in the setcc operation.
299 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
300 // Get the branch opcode from the branch code.
301 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
302 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
304 BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
305 .addReg(Mips::ZERO).addMBB(sinkMBB);
307 F->insert(It, copy0MBB);
308 F->insert(It, sinkMBB);
309 // Update machine-CFG edges by first adding all successors of the current
310 // block to the new block which will contain the Phi node for the select.
311 // Also inform sdisel of the edge changes.
312 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
313 e = BB->succ_end(); i != e; ++i) {
314 EM->insert(std::make_pair(*i, sinkMBB));
315 sinkMBB->addSuccessor(*i);
317 // Next, remove all successors of the current block, and add the true
318 // and fallthrough blocks as its successors.
319 while(!BB->succ_empty())
320 BB->removeSuccessor(BB->succ_begin());
321 BB->addSuccessor(copy0MBB);
322 BB->addSuccessor(sinkMBB);
326 // # fallthrough to sinkMBB
329 // Update machine-CFG edges
330 BB->addSuccessor(sinkMBB);
333 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
336 BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg())
337 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
338 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
340 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
346 //===----------------------------------------------------------------------===//
347 // Misc Lower Operation implementation
348 //===----------------------------------------------------------------------===//
350 SDValue MipsTargetLowering::
351 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG)
353 if (!Subtarget->isMips1())
356 MachineFunction &MF = DAG.getMachineFunction();
357 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
359 SDValue Chain = DAG.getEntryNode();
360 DebugLoc dl = Op.getDebugLoc();
361 SDValue Src = Op.getOperand(0);
363 // Set the condition register
364 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
365 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
366 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
368 SDValue Cst = DAG.getConstant(3, MVT::i32);
369 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
370 Cst = DAG.getConstant(2, MVT::i32);
371 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
373 SDValue InFlag(0, 0);
374 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
376 // Emit the round instruction and bit convert to integer
377 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
378 Src, CondReg.getValue(1));
379 SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Trunc);
383 SDValue MipsTargetLowering::
384 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
386 SDValue Chain = Op.getOperand(0);
387 SDValue Size = Op.getOperand(1);
388 DebugLoc dl = Op.getDebugLoc();
390 // Get a reference from Mips stack pointer
391 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
393 // Subtract the dynamic size from the actual stack size to
394 // obtain the new stack size.
395 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
397 // The Sub result contains the new stack start address, so it
398 // must be placed in the stack pointer register.
399 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
401 // This node always has two return values: a new stack pointer
403 SDValue Ops[2] = { Sub, Chain };
404 return DAG.getMergeValues(Ops, 2, dl);
407 SDValue MipsTargetLowering::
408 LowerANDOR(SDValue Op, SelectionDAG &DAG)
410 SDValue LHS = Op.getOperand(0);
411 SDValue RHS = Op.getOperand(1);
412 DebugLoc dl = Op.getDebugLoc();
414 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
417 SDValue True = DAG.getConstant(1, MVT::i32);
418 SDValue False = DAG.getConstant(0, MVT::i32);
420 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
421 LHS, True, False, LHS.getOperand(2));
422 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
423 RHS, True, False, RHS.getOperand(2));
425 return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
428 SDValue MipsTargetLowering::
429 LowerBRCOND(SDValue Op, SelectionDAG &DAG)
431 // The first operand is the chain, the second is the condition, the third is
432 // the block to branch to if the condition is true.
433 SDValue Chain = Op.getOperand(0);
434 SDValue Dest = Op.getOperand(2);
435 DebugLoc dl = Op.getDebugLoc();
437 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
440 SDValue CondRes = Op.getOperand(1);
441 SDValue CCNode = CondRes.getOperand(2);
443 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
444 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
446 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
450 SDValue MipsTargetLowering::
451 LowerSETCC(SDValue Op, SelectionDAG &DAG)
453 // The operands to this are the left and right operands to compare (ops #0,
454 // and #1) and the condition code to compare them with (op #2) as a
456 SDValue LHS = Op.getOperand(0);
457 SDValue RHS = Op.getOperand(1);
458 DebugLoc dl = Op.getDebugLoc();
460 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
462 return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
463 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
466 SDValue MipsTargetLowering::
467 LowerSELECT(SDValue Op, SelectionDAG &DAG)
469 SDValue Cond = Op.getOperand(0);
470 SDValue True = Op.getOperand(1);
471 SDValue False = Op.getOperand(2);
472 DebugLoc dl = Op.getDebugLoc();
474 // if the incomming condition comes from a integer compare, the select
475 // operation must be SelectCC or a conditional move if the subtarget
477 if (Cond.getOpcode() != MipsISD::FPCmp) {
478 if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
480 return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(),
484 // if the incomming condition comes from fpcmp, the select
485 // operation must use FPSelectCC.
486 SDValue CCNode = Cond.getOperand(2);
487 return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
488 Cond, True, False, CCNode);
491 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
492 // FIXME there isn't actually debug info here
493 DebugLoc dl = Op.getDebugLoc();
494 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
496 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
497 SDVTList VTs = DAG.getVTList(MVT::i32);
499 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
501 // %gp_rel relocation
502 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
503 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32, 0,
505 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
506 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
507 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
509 // %hi/%lo relocation
510 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32, 0,
511 MipsII::MO_ABS_HILO);
512 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GA, 1);
513 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
514 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
517 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32, 0,
519 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
520 DAG.getEntryNode(), GA, NULL, 0);
521 // On functions and global targets not internal linked only
522 // a load from got/GP is necessary for PIC to work.
523 if (!GV->hasLocalLinkage() || isa<Function>(GV))
525 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
526 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
529 llvm_unreachable("Dont know how to handle GlobalAddress");
533 SDValue MipsTargetLowering::
534 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
536 llvm_unreachable("TLS not implemented for MIPS.");
537 return SDValue(); // Not reached
540 SDValue MipsTargetLowering::
541 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
545 // FIXME there isn't actually debug info here
546 DebugLoc dl = Op.getDebugLoc();
547 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
548 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HILO;
550 EVT PtrVT = Op.getValueType();
551 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
553 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
556 SDValue Ops[] = { JTI };
557 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
558 } else // Emit Load from Global Pointer
559 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
561 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
562 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
567 SDValue MipsTargetLowering::
568 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
571 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
572 Constant *C = N->getConstVal();
573 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
574 MipsII::MO_ABS_HILO);
575 // FIXME there isn't actually debug info here
576 DebugLoc dl = Op.getDebugLoc();
579 // FIXME: we should reference the constant pool using small data sections,
580 // but the asm printer currently doens't support this feature without
581 // hacking it. This feature should come soon so we can uncomment the
583 //if (IsInSmallSection(C->getType())) {
584 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
585 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
586 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
587 //} else { // %hi/%lo relocation
588 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
589 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
590 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
596 //===----------------------------------------------------------------------===//
597 // Calling Convention Implementation
598 //===----------------------------------------------------------------------===//
600 #include "MipsGenCallingConv.inc"
602 //===----------------------------------------------------------------------===//
603 // TODO: Implement a generic logic using tblgen that can support this.
604 // Mips O32 ABI rules:
606 // i32 - Passed in A0, A1, A2, A3 and stack
607 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
608 // an argument. Otherwise, passed in A1, A2, A3 and stack.
609 // f64 - Only passed in two aliased f32 registers if no int reg has been used
610 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
611 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
613 //===----------------------------------------------------------------------===//
615 static bool CC_MipsO32(unsigned ValNo, EVT ValVT,
616 EVT LocVT, CCValAssign::LocInfo LocInfo,
617 ISD::ArgFlagsTy ArgFlags, CCState &State) {
619 static const unsigned IntRegsSize=4, FloatRegsSize=2;
621 static const unsigned IntRegs[] = {
622 Mips::A0, Mips::A1, Mips::A2, Mips::A3
624 static const unsigned F32Regs[] = {
627 static const unsigned F64Regs[] = {
632 unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
633 bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0)));
635 // Promote i8 and i16
636 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
638 if (ArgFlags.isSExt())
639 LocInfo = CCValAssign::SExt;
640 else if (ArgFlags.isZExt())
641 LocInfo = CCValAssign::ZExt;
643 LocInfo = CCValAssign::AExt;
646 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) {
647 Reg = State.AllocateReg(IntRegs, IntRegsSize);
652 if (ValVT.isFloatingPoint() && !IntRegUsed) {
653 if (ValVT == MVT::f32)
654 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
656 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
659 if (ValVT == MVT::f64 && IntRegUsed) {
660 if (UnallocIntReg != IntRegsSize) {
661 // If we hit register A3 as the first not allocated, we must
662 // mark it as allocated (shadow) and use the stack instead.
663 if (IntRegs[UnallocIntReg] != (unsigned (Mips::A3)))
665 for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg)
666 State.AllocateReg(UnallocIntReg);
672 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
673 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
674 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
676 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
678 return false; // CC must always match
681 //===----------------------------------------------------------------------===//
682 // Call Calling Convention Implementation
683 //===----------------------------------------------------------------------===//
685 /// LowerCall - functions arguments are copied from virtual regs to
686 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
687 /// TODO: isVarArg, isTailCall.
689 MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
690 CallingConv::ID CallConv, bool isVarArg,
692 const SmallVectorImpl<ISD::OutputArg> &Outs,
693 const SmallVectorImpl<ISD::InputArg> &Ins,
694 DebugLoc dl, SelectionDAG &DAG,
695 SmallVectorImpl<SDValue> &InVals) {
697 MachineFunction &MF = DAG.getMachineFunction();
698 MachineFrameInfo *MFI = MF.getFrameInfo();
699 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
701 // Analyze operands of the call, assigning locations to each operand.
702 SmallVector<CCValAssign, 16> ArgLocs;
703 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
706 // To meet O32 ABI, Mips must always allocate 16 bytes on
707 // the stack (even if less than 4 are used as arguments)
708 if (Subtarget->isABI_O32()) {
709 int VTsize = EVT(MVT::i32).getSizeInBits()/8;
710 MFI->CreateFixedObject(VTsize, (VTsize*3));
711 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
713 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
715 // Get a count of how many bytes are to be pushed on the stack.
716 unsigned NumBytes = CCInfo.getNextStackOffset();
717 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
719 // With EABI is it possible to have 16 args on registers.
720 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
721 SmallVector<SDValue, 8> MemOpChains;
723 // First/LastArgStackLoc contains the first/last
724 // "at stack" argument location.
725 int LastArgStackLoc = 0;
726 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
728 // Walk the register/memloc assignments, inserting copies/loads.
729 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
730 SDValue Arg = Outs[i].Val;
731 CCValAssign &VA = ArgLocs[i];
733 // Promote the value if needed.
734 switch (VA.getLocInfo()) {
735 default: llvm_unreachable("Unknown loc info!");
736 case CCValAssign::Full:
737 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
738 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
739 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg);
740 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
741 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
742 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
743 DAG.getConstant(0, getPointerTy()));
744 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
745 DAG.getConstant(1, getPointerTy()));
746 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
747 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
752 case CCValAssign::SExt:
753 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
755 case CCValAssign::ZExt:
756 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
758 case CCValAssign::AExt:
759 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
763 // Arguments that can be passed on register must be kept at
766 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
770 // Register can't get to this point...
771 assert(VA.isMemLoc());
773 // Create the frame index object for this incoming parameter
774 // This guarantees that when allocating Local Area the firsts
775 // 16 bytes which are alwayes reserved won't be overwritten
776 // if O32 ABI is used. For EABI the first address is zero.
777 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
778 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
781 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
783 // emit ISD::STORE whichs stores the
784 // parameter value to a stack Location
785 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
788 // Transform all store nodes into one single node because all store
789 // nodes are independent of each other.
790 if (!MemOpChains.empty())
791 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
792 &MemOpChains[0], MemOpChains.size());
794 // Build a sequence of copy-to-reg nodes chained together with token
795 // chain and flag operands which copy the outgoing args into registers.
796 // The InFlag in necessary since all emited instructions must be
799 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
800 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
801 RegsToPass[i].second, InFlag);
802 InFlag = Chain.getValue(1);
805 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
806 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
807 // node so that legalize doesn't hack it.
808 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
809 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
810 Callee = DAG.getTargetGlobalAddress(G->getGlobal(),
811 getPointerTy(), 0, OpFlag);
812 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
813 Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
814 getPointerTy(), OpFlag);
816 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
817 // = Chain, Callee, Reg#1, Reg#2, ...
819 // Returns a chain & a flag for retval copy to use.
820 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
821 SmallVector<SDValue, 8> Ops;
822 Ops.push_back(Chain);
823 Ops.push_back(Callee);
825 // Add argument registers to the end of the list so that they are
826 // known live into the call.
827 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
828 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
829 RegsToPass[i].second.getValueType()));
831 if (InFlag.getNode())
832 Ops.push_back(InFlag);
834 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
835 InFlag = Chain.getValue(1);
837 // Create the CALLSEQ_END node.
838 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
839 DAG.getIntPtrConstant(0, true), InFlag);
840 InFlag = Chain.getValue(1);
842 // Create a stack location to hold GP when PIC is used. This stack
843 // location is used on function prologue to save GP and also after all
844 // emited CALL's to restore GP.
846 // Function can have an arbitrary number of calls, so
847 // hold the LastArgStackLoc with the biggest offset.
849 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
850 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
851 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
852 // Create the frame index only once. SPOffset here can be anything
853 // (this will be fixed on processFunctionBeforeFrameFinalized)
854 if (MipsFI->getGPStackOffset() == -1) {
855 FI = MFI->CreateFixedObject(4, 0);
858 MipsFI->setGPStackOffset(LastArgStackLoc);
862 FI = MipsFI->getGPFI();
863 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
864 SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0);
865 Chain = GPLoad.getValue(1);
866 Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
867 GPLoad, SDValue(0,0));
868 InFlag = Chain.getValue(1);
871 // Handle result values, copying them out of physregs into vregs that we
873 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
874 Ins, dl, DAG, InVals);
877 /// LowerCallResult - Lower the result values of a call into the
878 /// appropriate copies out of appropriate physical registers.
880 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
881 CallingConv::ID CallConv, bool isVarArg,
882 const SmallVectorImpl<ISD::InputArg> &Ins,
883 DebugLoc dl, SelectionDAG &DAG,
884 SmallVectorImpl<SDValue> &InVals) {
886 // Assign locations to each value returned by this call.
887 SmallVector<CCValAssign, 16> RVLocs;
888 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
889 RVLocs, *DAG.getContext());
891 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
893 // Copy all of the result registers out of their specified physreg.
894 for (unsigned i = 0; i != RVLocs.size(); ++i) {
895 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
896 RVLocs[i].getValVT(), InFlag).getValue(1);
897 InFlag = Chain.getValue(2);
898 InVals.push_back(Chain.getValue(0));
904 //===----------------------------------------------------------------------===//
905 // Formal Arguments Calling Convention Implementation
906 //===----------------------------------------------------------------------===//
908 /// LowerFormalArguments - transform physical registers into
909 /// virtual registers and generate load operations for
910 /// arguments places on the stack.
913 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
914 CallingConv::ID CallConv, bool isVarArg,
915 const SmallVectorImpl<ISD::InputArg>
917 DebugLoc dl, SelectionDAG &DAG,
918 SmallVectorImpl<SDValue> &InVals) {
920 MachineFunction &MF = DAG.getMachineFunction();
921 MachineFrameInfo *MFI = MF.getFrameInfo();
922 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
924 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
926 // Assign locations to all of the incoming arguments.
927 SmallVector<CCValAssign, 16> ArgLocs;
928 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
929 ArgLocs, *DAG.getContext());
931 if (Subtarget->isABI_O32())
932 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
934 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
938 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
940 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
941 CCValAssign &VA = ArgLocs[i];
943 // Arguments stored on registers
945 EVT RegVT = VA.getLocVT();
946 TargetRegisterClass *RC = 0;
948 if (RegVT == MVT::i32)
949 RC = Mips::CPURegsRegisterClass;
950 else if (RegVT == MVT::f32)
951 RC = Mips::FGR32RegisterClass;
952 else if (RegVT == MVT::f64) {
953 if (!Subtarget->isSingleFloat())
954 RC = Mips::AFGR64RegisterClass;
956 llvm_unreachable("RegVT not supported by LowerFormalArguments Lowering");
958 // Transform the arguments stored on
959 // physical registers into virtual ones
960 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
961 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
963 // If this is an 8 or 16-bit value, it has been passed promoted
964 // to 32 bits. Insert an assert[sz]ext to capture this, then
965 // truncate to the right size.
966 if (VA.getLocInfo() != CCValAssign::Full) {
968 if (VA.getLocInfo() == CCValAssign::SExt)
969 Opcode = ISD::AssertSext;
970 else if (VA.getLocInfo() == CCValAssign::ZExt)
971 Opcode = ISD::AssertZext;
973 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
974 DAG.getValueType(VA.getValVT()));
975 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
978 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
979 if (Subtarget->isABI_O32()) {
980 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
981 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
982 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
983 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
984 VA.getLocReg()+1, RC);
985 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
986 SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
987 SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2);
988 ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi);
992 InVals.push_back(ArgValue);
994 // To meet ABI, when VARARGS are passed on registers, the registers
995 // must have their values written to the caller stack frame.
996 if ((isVarArg) && (Subtarget->isABI_O32())) {
997 if (StackPtr.getNode() == 0)
998 StackPtr = DAG.getRegister(StackReg, getPointerTy());
1000 // The stack pointer offset is relative to the caller stack frame.
1001 // Since the real stack size is unknown here, a negative SPOffset
1002 // is used so there's a way to adjust these offsets when the stack
1003 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1004 // used instead of a direct negative address (which is recorded to
1005 // be used on emitPrologue) to avoid mis-calc of the first stack
1006 // offset on PEI::calculateFrameObjectOffsets.
1007 // Arguments are always 32-bit.
1008 int FI = MFI->CreateFixedObject(4, 0);
1009 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
1010 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
1012 // emit ISD::STORE whichs stores the
1013 // parameter value to a stack Location
1014 InVals.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, NULL, 0));
1017 } else { // VA.isRegLoc()
1020 assert(VA.isMemLoc());
1022 // The stack pointer offset is relative to the caller stack frame.
1023 // Since the real stack size is unknown here, a negative SPOffset
1024 // is used so there's a way to adjust these offsets when the stack
1025 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1026 // used instead of a direct negative address (which is recorded to
1027 // be used on emitPrologue) to avoid mis-calc of the first stack
1028 // offset on PEI::calculateFrameObjectOffsets.
1029 // Arguments are always 32-bit.
1030 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1031 int FI = MFI->CreateFixedObject(ArgSize, 0);
1032 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
1033 (FirstStackArgLoc + VA.getLocMemOffset())));
1035 // Create load nodes to retrieve arguments from the stack
1036 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1037 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
1041 // The mips ABIs for returning structs by value requires that we copy
1042 // the sret argument into $v0 for the return. Save the argument into
1043 // a virtual register so that we can access it from the return points.
1044 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1045 unsigned Reg = MipsFI->getSRetReturnReg();
1047 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1048 MipsFI->setSRetReturnReg(Reg);
1050 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1051 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1057 //===----------------------------------------------------------------------===//
1058 // Return Value Calling Convention Implementation
1059 //===----------------------------------------------------------------------===//
1062 MipsTargetLowering::LowerReturn(SDValue Chain,
1063 CallingConv::ID CallConv, bool isVarArg,
1064 const SmallVectorImpl<ISD::OutputArg> &Outs,
1065 DebugLoc dl, SelectionDAG &DAG) {
1067 // CCValAssign - represent the assignment of
1068 // the return value to a location
1069 SmallVector<CCValAssign, 16> RVLocs;
1071 // CCState - Info about the registers and stack slot.
1072 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1073 RVLocs, *DAG.getContext());
1075 // Analize return values.
1076 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
1078 // If this is the first return lowered for this function, add
1079 // the regs to the liveout set for the function.
1080 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1081 for (unsigned i = 0; i != RVLocs.size(); ++i)
1082 if (RVLocs[i].isRegLoc())
1083 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1088 // Copy the result values into the output registers.
1089 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1090 CCValAssign &VA = RVLocs[i];
1091 assert(VA.isRegLoc() && "Can only return in registers!");
1093 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1096 // guarantee that all emitted copies are
1097 // stuck together, avoiding something bad
1098 Flag = Chain.getValue(1);
1101 // The mips ABIs for returning structs by value requires that we copy
1102 // the sret argument into $v0 for the return. We saved the argument into
1103 // a virtual register in the entry block, so now we copy the value out
1105 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1106 MachineFunction &MF = DAG.getMachineFunction();
1107 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1108 unsigned Reg = MipsFI->getSRetReturnReg();
1111 llvm_unreachable("sret virtual register not created in the entry block");
1112 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1114 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1115 Flag = Chain.getValue(1);
1118 // Return on Mips is always a "jr $ra"
1120 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1121 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1123 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1124 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1127 //===----------------------------------------------------------------------===//
1128 // Mips Inline Assembly Support
1129 //===----------------------------------------------------------------------===//
1131 /// getConstraintType - Given a constraint letter, return the type of
1132 /// constraint it is for this target.
1133 MipsTargetLowering::ConstraintType MipsTargetLowering::
1134 getConstraintType(const std::string &Constraint) const
1136 // Mips specific constrainy
1137 // GCC config/mips/constraints.md
1139 // 'd' : An address register. Equivalent to r
1140 // unless generating MIPS16 code.
1141 // 'y' : Equivalent to r; retained for
1142 // backwards compatibility.
1143 // 'f' : Floating Point registers.
1144 if (Constraint.size() == 1) {
1145 switch (Constraint[0]) {
1150 return C_RegisterClass;
1154 return TargetLowering::getConstraintType(Constraint);
1157 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1158 /// return a list of registers that can be used to satisfy the constraint.
1159 /// This should only be used for C_RegisterClass constraints.
1160 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1161 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
1163 if (Constraint.size() == 1) {
1164 switch (Constraint[0]) {
1166 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1169 return std::make_pair(0U, Mips::FGR32RegisterClass);
1171 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1172 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1175 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1178 /// Given a register class constraint, like 'r', if this corresponds directly
1179 /// to an LLVM register class, return a register of 0 and the register class
1181 std::vector<unsigned> MipsTargetLowering::
1182 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1185 if (Constraint.size() != 1)
1186 return std::vector<unsigned>();
1188 switch (Constraint[0]) {
1191 // GCC Mips Constraint Letters
1194 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1195 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1196 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1200 if (VT == MVT::f32) {
1201 if (Subtarget->isSingleFloat())
1202 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1203 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1204 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1205 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1206 Mips::F30, Mips::F31, 0);
1208 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1209 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1210 Mips::F28, Mips::F30, 0);
1214 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1215 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1216 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1217 Mips::D14, Mips::D15, 0);
1219 return std::vector<unsigned>();
1223 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1224 // The Mips target isn't yet aware of offsets.