1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
39 const char *MipsTargetLowering::
40 getTargetNodeName(unsigned Opcode) const
44 case MipsISD::JmpLink : return "MipsISD::JmpLink";
45 case MipsISD::Hi : return "MipsISD::Hi";
46 case MipsISD::Lo : return "MipsISD::Lo";
47 case MipsISD::GPRel : return "MipsISD::GPRel";
48 case MipsISD::Ret : return "MipsISD::Ret";
49 case MipsISD::SelectCC : return "MipsISD::SelectCC";
50 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
51 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
52 case MipsISD::FPCmp : return "MipsISD::FPCmp";
53 default : return NULL;
58 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
60 Subtarget = &TM.getSubtarget<MipsSubtarget>();
62 // Mips does not have i1 type, so use i32 for
63 // setcc operations results (slt, sgt, ...).
64 setSetCCResultContents(ZeroOrOneSetCCResult);
66 // JumpTable targets must use GOT when using PIC_
67 setUsesGlobalOffsetTable(true);
69 // Set up the register classes
70 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
72 // When dealing with single precision only, use libcalls
73 if (!Subtarget->isSingleFloat()) {
74 addRegisterClass(MVT::f32, Mips::AFGR32RegisterClass);
75 if (!Subtarget->isFP64bit())
76 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
78 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
81 addLegalFPImmediate(APFloat(+0.0f));
83 // Load extented operations for i1 types must be promoted
84 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
85 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
86 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
88 // Used by legalize types to correctly generate the setcc result.
89 // Without this, every float setcc comes with a AND/OR with the result,
90 // we don't want this, since the fpcmp result goes to a flag register,
91 // which is used implicitly by brcond and select operations.
92 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
94 // Mips Custom Operations
95 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
96 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
97 setOperationAction(ISD::RET, MVT::Other, Custom);
98 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
99 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
100 setOperationAction(ISD::SELECT, MVT::f32, Custom);
101 setOperationAction(ISD::SELECT, MVT::i32, Custom);
102 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
103 setOperationAction(ISD::SETCC, MVT::f32, Custom);
104 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
106 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
107 // with operands comming from setcc fp comparions. This is necessary since
108 // the result from these setcc are in a flag registers (FCR31).
109 setOperationAction(ISD::AND, MVT::i32, Custom);
110 setOperationAction(ISD::OR, MVT::i32, Custom);
112 // Operations not directly supported by Mips.
113 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
114 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
115 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
116 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
117 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
119 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
120 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
121 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
122 setOperationAction(ISD::ROTL, MVT::i32, Expand);
123 setOperationAction(ISD::ROTR, MVT::i32, Expand);
124 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
125 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
126 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
127 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
128 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
130 // We don't have line number support yet.
131 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
132 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
133 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
134 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
136 // Use the default for now
137 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
138 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
139 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
141 if (Subtarget->isSingleFloat())
142 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
144 if (!Subtarget->hasSEInReg()) {
145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
149 setStackPointerRegisterToSaveRestore(Mips::SP);
150 computeRegisterProperties();
154 MVT MipsTargetLowering::getSetCCResultType(const SDValue &) const {
159 SDValue MipsTargetLowering::
160 LowerOperation(SDValue Op, SelectionDAG &DAG)
162 switch (Op.getOpcode())
164 case ISD::AND: return LowerANDOR(Op, DAG);
165 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
166 case ISD::CALL: return LowerCALL(Op, DAG);
167 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
168 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
169 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
170 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
171 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
172 case ISD::OR: return LowerANDOR(Op, DAG);
173 case ISD::RET: return LowerRET(Op, DAG);
174 case ISD::SELECT: return LowerSELECT(Op, DAG);
175 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
176 case ISD::SETCC: return LowerSETCC(Op, DAG);
181 //===----------------------------------------------------------------------===//
182 // Lower helper functions
183 //===----------------------------------------------------------------------===//
185 // AddLiveIn - This helper function adds the specified physical register to the
186 // MachineFunction as a live in value. It also creates a corresponding
187 // virtual register for it.
189 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
191 assert(RC->contains(PReg) && "Not the correct regclass!");
192 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
193 MF.getRegInfo().addLiveIn(PReg, VReg);
197 // A address must be loaded from a small section if its size is less than the
198 // small section size threshold. Data in this section must be addressed using
200 bool MipsTargetLowering::IsInSmallSection(unsigned Size) {
201 return (Size > 0 && (Size <= Subtarget->getSSectionThreshold()));
204 // Discover if this global address can be placed into small data/bss section.
205 bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV)
207 const TargetData *TD = getTargetData();
208 const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV);
213 const Type *Ty = GV->getType()->getElementType();
214 unsigned Size = TD->getABITypeSize(Ty);
216 // if this is a internal constant string, there is a special
217 // section for it, but not in small data/bss.
218 if (GVA->hasInitializer() && GV->hasInternalLinkage()) {
219 Constant *C = GVA->getInitializer();
220 const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
221 if (CVA && CVA->isCString())
225 return IsInSmallSection(Size);
228 // Get fp branch code (not opcode) from condition code.
229 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
230 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
231 return Mips::BRANCH_T;
233 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
234 return Mips::BRANCH_F;
236 return Mips::BRANCH_INVALID;
239 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
242 assert(0 && "Unknown branch code");
243 case Mips::BRANCH_T : return Mips::BC1T;
244 case Mips::BRANCH_F : return Mips::BC1F;
245 case Mips::BRANCH_TL : return Mips::BC1TL;
246 case Mips::BRANCH_FL : return Mips::BC1FL;
250 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
252 default: assert(0 && "Unknown fp condition code!");
254 case ISD::SETOEQ: return Mips::FCOND_EQ;
255 case ISD::SETUNE: return Mips::FCOND_OGL;
257 case ISD::SETOLT: return Mips::FCOND_OLT;
259 case ISD::SETOGT: return Mips::FCOND_OGT;
261 case ISD::SETOLE: return Mips::FCOND_OLE;
263 case ISD::SETOGE: return Mips::FCOND_OGE;
264 case ISD::SETULT: return Mips::FCOND_ULT;
265 case ISD::SETULE: return Mips::FCOND_ULE;
266 case ISD::SETUGT: return Mips::FCOND_UGT;
267 case ISD::SETUGE: return Mips::FCOND_UGE;
268 case ISD::SETUO: return Mips::FCOND_UN;
269 case ISD::SETO: return Mips::FCOND_OR;
271 case ISD::SETONE: return Mips::FCOND_NEQ;
272 case ISD::SETUEQ: return Mips::FCOND_UEQ;
277 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
278 MachineBasicBlock *BB)
280 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
281 bool isFPCmp = false;
283 switch (MI->getOpcode()) {
284 default: assert(false && "Unexpected instr type to insert");
285 case Mips::Select_FCC:
286 case Mips::Select_FCC_SO32:
287 case Mips::Select_FCC_AS32:
288 case Mips::Select_FCC_D32:
289 isFPCmp = true; // FALL THROUGH
290 case Mips::Select_CC:
291 case Mips::Select_CC_SO32:
292 case Mips::Select_CC_AS32:
293 case Mips::Select_CC_D32: {
294 // To "insert" a SELECT_CC instruction, we actually have to insert the
295 // diamond control-flow pattern. The incoming instruction knows the
296 // destination vreg to set, the condition code register to branch on, the
297 // true/false values to select between, and a branch opcode to use.
298 const BasicBlock *LLVM_BB = BB->getBasicBlock();
299 MachineFunction::iterator It = BB;
306 // bNE r1, r0, copy1MBB
307 // fallthrough --> copy0MBB
308 MachineBasicBlock *thisMBB = BB;
309 MachineFunction *F = BB->getParent();
310 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
311 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
313 // Emit the right instruction according to the type of the operands compared
315 // Find the condiction code present in the setcc operation.
316 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
317 // Get the branch opcode from the branch code.
318 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
319 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
321 BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
322 .addReg(Mips::ZERO).addMBB(sinkMBB);
324 F->insert(It, copy0MBB);
325 F->insert(It, sinkMBB);
326 // Update machine-CFG edges by first adding all successors of the current
327 // block to the new block which will contain the Phi node for the select.
328 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
329 e = BB->succ_end(); i != e; ++i)
330 sinkMBB->addSuccessor(*i);
331 // Next, remove all successors of the current block, and add the true
332 // and fallthrough blocks as its successors.
333 while(!BB->succ_empty())
334 BB->removeSuccessor(BB->succ_begin());
335 BB->addSuccessor(copy0MBB);
336 BB->addSuccessor(sinkMBB);
340 // # fallthrough to sinkMBB
343 // Update machine-CFG edges
344 BB->addSuccessor(sinkMBB);
347 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
350 BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg())
351 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
352 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
354 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
360 //===----------------------------------------------------------------------===//
361 // Misc Lower Operation implementation
362 //===----------------------------------------------------------------------===//
364 SDValue MipsTargetLowering::
365 LowerANDOR(SDValue Op, SelectionDAG &DAG)
367 SDValue LHS = Op.getOperand(0);
368 SDValue RHS = Op.getOperand(1);
370 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
373 SDValue True = DAG.getConstant(1, MVT::i32);
374 SDValue False = DAG.getConstant(0, MVT::i32);
376 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
377 LHS, True, False, LHS.getOperand(2));
378 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
379 RHS, True, False, RHS.getOperand(2));
381 return DAG.getNode(Op.getOpcode(), MVT::i32, LSEL, RSEL);
384 SDValue MipsTargetLowering::
385 LowerBRCOND(SDValue Op, SelectionDAG &DAG)
387 // The first operand is the chain, the second is the condition, the third is
388 // the block to branch to if the condition is true.
389 SDValue Chain = Op.getOperand(0);
390 SDValue Dest = Op.getOperand(2);
392 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
395 SDValue CondRes = Op.getOperand(1);
396 SDValue CCNode = CondRes.getOperand(2);
397 Mips::CondCode CC = (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getValue();
398 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
400 return DAG.getNode(MipsISD::FPBrcond, Op.getValueType(), Chain, BrCode,
404 SDValue MipsTargetLowering::
405 LowerSETCC(SDValue Op, SelectionDAG &DAG)
407 // The operands to this are the left and right operands to compare (ops #0,
408 // and #1) and the condition code to compare them with (op #2) as a
410 SDValue LHS = Op.getOperand(0);
411 SDValue RHS = Op.getOperand(1);
413 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
415 return DAG.getNode(MipsISD::FPCmp, Op.getValueType(), LHS, RHS,
416 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
419 SDValue MipsTargetLowering::
420 LowerSELECT(SDValue Op, SelectionDAG &DAG)
422 SDValue Cond = Op.getOperand(0);
423 SDValue True = Op.getOperand(1);
424 SDValue False = Op.getOperand(2);
426 // if the incomming condition comes from fpcmp, the select
427 // operation must use FPSelectCC, otherwise SelectCC.
428 if (Cond.getOpcode() != MipsISD::FPCmp)
429 return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
432 SDValue CCNode = Cond.getOperand(2);
433 return DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
434 Cond, True, False, CCNode);
437 SDValue MipsTargetLowering::
438 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG)
440 SDValue LHS = Op.getOperand(0);
441 SDValue RHS = Op.getOperand(1);
442 SDValue True = Op.getOperand(2);
443 SDValue False = Op.getOperand(3);
444 SDValue CC = Op.getOperand(4);
446 SDValue SetCCRes = DAG.getNode(ISD::SETCC, LHS.getValueType(), LHS, RHS, CC);
447 return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
448 SetCCRes, True, False);
451 SDValue MipsTargetLowering::
452 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
454 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
455 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
457 if (!Subtarget->hasABICall()) {
458 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
459 SDValue Ops[] = { GA };
460 // %gp_rel relocation
461 if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) {
462 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1);
463 SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
464 return DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
466 // %hi/%lo relocation
467 SDValue HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
468 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
469 return DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
471 } else { // Abicall relocations, TODO: make this cleaner.
472 SDValue ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
473 // On functions and global targets not internal linked only
474 // a load from got/GP is necessary for PIC to work.
475 if (!GV->hasInternalLinkage() || isa<Function>(GV))
477 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
478 return DAG.getNode(ISD::ADD, MVT::i32, ResNode, Lo);
481 assert(0 && "Dont know how to handle GlobalAddress");
485 SDValue MipsTargetLowering::
486 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
488 assert(0 && "TLS not implemented for MIPS.");
489 return SDValue(); // Not reached
492 SDValue MipsTargetLowering::
493 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
498 MVT PtrVT = Op.getValueType();
499 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
500 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
502 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
503 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
504 SDValue Ops[] = { JTI };
505 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
506 } else // Emit Load from Global Pointer
507 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
509 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
510 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
515 SDValue MipsTargetLowering::
516 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
519 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
520 Constant *C = N->getConstVal();
521 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
524 // FIXME: we should reference the constant pool using small data sections,
525 // but the asm printer currently doens't support this feature without
526 // hacking it. This feature should come soon so we can uncomment the
528 //if (!Subtarget->hasABICall() &&
529 // IsInSmallSection(getTargetData()->getABITypeSize(C->getType()))) {
530 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
531 // SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
532 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
533 //} else { // %hi/%lo relocation
534 SDValue HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP);
535 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP);
536 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
542 //===----------------------------------------------------------------------===//
543 // Calling Convention Implementation
545 // The lower operations present on calling convention works on this order:
546 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
547 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
548 // LowerRET (virt regs --> phys regs)
549 // LowerCALL (phys regs --> virt regs)
551 //===----------------------------------------------------------------------===//
553 #include "MipsGenCallingConv.inc"
555 //===----------------------------------------------------------------------===//
556 // CALL Calling Convention Implementation
557 //===----------------------------------------------------------------------===//
559 /// Mips custom CALL implementation
560 SDValue MipsTargetLowering::
561 LowerCALL(SDValue Op, SelectionDAG &DAG)
563 unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
565 // By now, only CallingConv::C implemented
566 switch (CallingConv) {
568 assert(0 && "Unsupported calling convention");
569 case CallingConv::Fast:
571 return LowerCCCCallTo(Op, DAG, CallingConv);
575 /// LowerCCCCallTo - functions arguments are copied from virtual
576 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
577 /// CALLSEQ_END are emitted.
578 /// TODO: isVarArg, isTailCall.
579 SDValue MipsTargetLowering::
580 LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC)
582 MachineFunction &MF = DAG.getMachineFunction();
584 SDValue Chain = Op.getOperand(0);
585 SDValue Callee = Op.getOperand(4);
586 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
588 MachineFrameInfo *MFI = MF.getFrameInfo();
590 // Analyze operands of the call, assigning locations to each operand.
591 SmallVector<CCValAssign, 16> ArgLocs;
592 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
594 // To meet O32 ABI, Mips must always allocate 16 bytes on
595 // the stack (even if less than 4 are used as arguments)
596 if (Subtarget->isABI_O32()) {
597 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
598 MFI->CreateFixedObject(VTsize, (VTsize*3));
601 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
603 // Get a count of how many bytes are to be pushed on the stack.
604 unsigned NumBytes = CCInfo.getNextStackOffset();
605 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
608 // With EABI is it possible to have 16 args on registers.
609 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
610 SmallVector<SDValue, 8> MemOpChains;
612 // First/LastArgStackLoc contains the first/last
613 // "at stack" argument location.
614 int LastArgStackLoc = 0;
615 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
617 // Walk the register/memloc assignments, inserting copies/loads.
618 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
619 CCValAssign &VA = ArgLocs[i];
621 // Arguments start after the 5 first operands of ISD::CALL
622 SDValue Arg = Op.getOperand(5+2*VA.getValNo());
624 // Promote the value if needed.
625 switch (VA.getLocInfo()) {
626 default: assert(0 && "Unknown loc info!");
627 case CCValAssign::Full: break;
628 case CCValAssign::SExt:
629 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
631 case CCValAssign::ZExt:
632 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
634 case CCValAssign::AExt:
635 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
639 // Arguments that can be passed on register must be kept at
642 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
646 // Register cant get to this point...
647 assert(VA.isMemLoc());
649 // Create the frame index object for this incoming parameter
650 // This guarantees that when allocating Local Area the firsts
651 // 16 bytes which are alwayes reserved won't be overwritten
652 // if O32 ABI is used. For EABI the first address is zero.
653 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
654 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
657 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
659 // emit ISD::STORE whichs stores the
660 // parameter value to a stack Location
661 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
664 // Transform all store nodes into one single node because all store
665 // nodes are independent of each other.
666 if (!MemOpChains.empty())
667 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
668 &MemOpChains[0], MemOpChains.size());
670 // Build a sequence of copy-to-reg nodes chained together with token
671 // chain and flag operands which copy the outgoing args into registers.
672 // The InFlag in necessary since all emited instructions must be
675 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
676 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
677 RegsToPass[i].second, InFlag);
678 InFlag = Chain.getValue(1);
681 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
682 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
683 // node so that legalize doesn't hack it.
684 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
685 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
686 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
687 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
690 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
691 // = Chain, Callee, Reg#1, Reg#2, ...
693 // Returns a chain & a flag for retval copy to use.
694 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
695 SmallVector<SDValue, 8> Ops;
696 Ops.push_back(Chain);
697 Ops.push_back(Callee);
699 // Add argument registers to the end of the list so that they are
700 // known live into the call.
701 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
702 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
703 RegsToPass[i].second.getValueType()));
706 Ops.push_back(InFlag);
708 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
709 InFlag = Chain.getValue(1);
711 // Create the CALLSEQ_END node.
712 Chain = DAG.getCALLSEQ_END(Chain,
713 DAG.getConstant(NumBytes, getPointerTy()),
714 DAG.getConstant(0, getPointerTy()),
716 InFlag = Chain.getValue(1);
718 // Create a stack location to hold GP when PIC is used. This stack
719 // location is used on function prologue to save GP and also after all
720 // emited CALL's to restore GP.
721 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
722 // Function can have an arbitrary number of calls, so
723 // hold the LastArgStackLoc with the biggest offset.
725 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
726 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
727 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
728 // Create the frame index only once. SPOffset here can be anything
729 // (this will be fixed on processFunctionBeforeFrameFinalized)
730 if (MipsFI->getGPStackOffset() == -1) {
731 FI = MFI->CreateFixedObject(4, 0);
734 MipsFI->setGPStackOffset(LastArgStackLoc);
738 FI = MipsFI->getGPFI();
739 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
740 SDValue GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
741 Chain = GPLoad.getValue(1);
742 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
743 GPLoad, SDValue(0,0));
744 InFlag = Chain.getValue(1);
747 // Handle result values, copying them out of physregs into vregs that we
749 return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
752 /// LowerCallResult - Lower the result values of an ISD::CALL into the
753 /// appropriate copies out of appropriate physical registers. This assumes that
754 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
755 /// being lowered. Returns a SDNode with the same number of values as the
757 SDNode *MipsTargetLowering::
758 LowerCallResult(SDValue Chain, SDValue InFlag, SDNode *TheCall,
759 unsigned CallingConv, SelectionDAG &DAG) {
761 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
763 // Assign locations to each value returned by this call.
764 SmallVector<CCValAssign, 16> RVLocs;
765 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
767 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
768 SmallVector<SDValue, 8> ResultVals;
770 // Copy all of the result registers out of their specified physreg.
771 for (unsigned i = 0; i != RVLocs.size(); ++i) {
772 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
773 RVLocs[i].getValVT(), InFlag).getValue(1);
774 InFlag = Chain.getValue(2);
775 ResultVals.push_back(Chain.getValue(0));
778 ResultVals.push_back(Chain);
780 // Merge everything together with a MERGE_VALUES node.
781 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
782 ResultVals.size()).Val;
785 //===----------------------------------------------------------------------===//
786 // FORMAL_ARGUMENTS Calling Convention Implementation
787 //===----------------------------------------------------------------------===//
789 /// Mips custom FORMAL_ARGUMENTS implementation
790 SDValue MipsTargetLowering::
791 LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
793 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
797 assert(0 && "Unsupported calling convention");
799 return LowerCCCArguments(Op, DAG);
803 /// LowerCCCArguments - transform physical registers into
804 /// virtual registers and generate load operations for
805 /// arguments places on the stack.
807 SDValue MipsTargetLowering::
808 LowerCCCArguments(SDValue Op, SelectionDAG &DAG)
810 SDValue Root = Op.getOperand(0);
811 MachineFunction &MF = DAG.getMachineFunction();
812 MachineFrameInfo *MFI = MF.getFrameInfo();
813 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
815 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
816 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
818 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
820 // GP must be live into PIC and non-PIC call target.
821 AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
823 // Assign locations to all of the incoming arguments.
824 SmallVector<CCValAssign, 16> ArgLocs;
825 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
827 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
828 SmallVector<SDValue, 16> ArgValues;
831 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
833 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
835 CCValAssign &VA = ArgLocs[i];
837 // Arguments stored on registers
839 MVT RegVT = VA.getLocVT();
840 TargetRegisterClass *RC = 0;
842 if (RegVT == MVT::i32)
843 RC = Mips::CPURegsRegisterClass;
844 else if (RegVT == MVT::f32) {
845 if (Subtarget->isSingleFloat())
846 RC = Mips::FGR32RegisterClass;
848 RC = Mips::AFGR32RegisterClass;
849 } else if (RegVT == MVT::f64) {
850 if (!Subtarget->isSingleFloat())
851 RC = Mips::AFGR64RegisterClass;
853 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
855 // Transform the arguments stored on
856 // physical registers into virtual ones
857 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
858 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
860 // If this is an 8 or 16-bit value, it is really passed promoted
861 // to 32 bits. Insert an assert[sz]ext to capture this, then
862 // truncate to the right size.
863 if (VA.getLocInfo() == CCValAssign::SExt)
864 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
865 DAG.getValueType(VA.getValVT()));
866 else if (VA.getLocInfo() == CCValAssign::ZExt)
867 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
868 DAG.getValueType(VA.getValVT()));
870 if (VA.getLocInfo() != CCValAssign::Full)
871 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
873 ArgValues.push_back(ArgValue);
875 // To meet ABI, when VARARGS are passed on registers, the registers
876 // must have their values written to the caller stack frame.
877 if ((isVarArg) && (Subtarget->isABI_O32())) {
878 if (StackPtr.Val == 0)
879 StackPtr = DAG.getRegister(StackReg, getPointerTy());
881 // The stack pointer offset is relative to the caller stack frame.
882 // Since the real stack size is unknown here, a negative SPOffset
883 // is used so there's a way to adjust these offsets when the stack
884 // size get known (on EliminateFrameIndex). A dummy SPOffset is
885 // used instead of a direct negative address (which is recorded to
886 // be used on emitPrologue) to avoid mis-calc of the first stack
887 // offset on PEI::calculateFrameObjectOffsets.
888 // Arguments are always 32-bit.
889 int FI = MFI->CreateFixedObject(4, 0);
890 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
891 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
893 // emit ISD::STORE whichs stores the
894 // parameter value to a stack Location
895 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
898 } else { // VA.isRegLoc()
901 assert(VA.isMemLoc());
903 // The stack pointer offset is relative to the caller stack frame.
904 // Since the real stack size is unknown here, a negative SPOffset
905 // is used so there's a way to adjust these offsets when the stack
906 // size get known (on EliminateFrameIndex). A dummy SPOffset is
907 // used instead of a direct negative address (which is recorded to
908 // be used on emitPrologue) to avoid mis-calc of the first stack
909 // offset on PEI::calculateFrameObjectOffsets.
910 // Arguments are always 32-bit.
911 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
912 int FI = MFI->CreateFixedObject(ArgSize, 0);
913 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
914 (FirstStackArgLoc + VA.getLocMemOffset())));
916 // Create load nodes to retrieve arguments from the stack
917 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
918 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
922 // The mips ABIs for returning structs by value requires that we copy
923 // the sret argument into $v0 for the return. Save the argument into
924 // a virtual register so that we can access it from the return points.
925 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
926 unsigned Reg = MipsFI->getSRetReturnReg();
928 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
929 MipsFI->setSRetReturnReg(Reg);
931 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
932 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
935 ArgValues.push_back(Root);
937 // Return the new list of results.
938 return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
939 ArgValues.size()).getValue(Op.ResNo);
942 //===----------------------------------------------------------------------===//
943 // Return Value Calling Convention Implementation
944 //===----------------------------------------------------------------------===//
946 SDValue MipsTargetLowering::
947 LowerRET(SDValue Op, SelectionDAG &DAG)
949 // CCValAssign - represent the assignment of
950 // the return value to a location
951 SmallVector<CCValAssign, 16> RVLocs;
952 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
953 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
955 // CCState - Info about the registers and stack slot.
956 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
958 // Analize return values of ISD::RET
959 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
961 // If this is the first return lowered for this function, add
962 // the regs to the liveout set for the function.
963 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
964 for (unsigned i = 0; i != RVLocs.size(); ++i)
965 if (RVLocs[i].isRegLoc())
966 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
969 // The chain is always operand #0
970 SDValue Chain = Op.getOperand(0);
973 // Copy the result values into the output registers.
974 for (unsigned i = 0; i != RVLocs.size(); ++i) {
975 CCValAssign &VA = RVLocs[i];
976 assert(VA.isRegLoc() && "Can only return in registers!");
978 // ISD::RET => ret chain, (regnum1,val1), ...
979 // So i*2+1 index only the regnums
980 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
982 // guarantee that all emitted copies are
983 // stuck together, avoiding something bad
984 Flag = Chain.getValue(1);
987 // The mips ABIs for returning structs by value requires that we copy
988 // the sret argument into $v0 for the return. We saved the argument into
989 // a virtual register in the entry block, so now we copy the value out
991 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
992 MachineFunction &MF = DAG.getMachineFunction();
993 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
994 unsigned Reg = MipsFI->getSRetReturnReg();
997 assert(0 && "sret virtual register not created in the entry block");
998 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
1000 Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag);
1001 Flag = Chain.getValue(1);
1004 // Return on Mips is always a "jr $ra"
1006 return DAG.getNode(MipsISD::Ret, MVT::Other,
1007 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1009 return DAG.getNode(MipsISD::Ret, MVT::Other,
1010 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1013 //===----------------------------------------------------------------------===//
1014 // Mips Inline Assembly Support
1015 //===----------------------------------------------------------------------===//
1017 /// getConstraintType - Given a constraint letter, return the type of
1018 /// constraint it is for this target.
1019 MipsTargetLowering::ConstraintType MipsTargetLowering::
1020 getConstraintType(const std::string &Constraint) const
1022 // Mips specific constrainy
1023 // GCC config/mips/constraints.md
1025 // 'd' : An address register. Equivalent to r
1026 // unless generating MIPS16 code.
1027 // 'y' : Equivalent to r; retained for
1028 // backwards compatibility.
1029 // 'f' : Floating Point registers.
1030 if (Constraint.size() == 1) {
1031 switch (Constraint[0]) {
1036 return C_RegisterClass;
1040 return TargetLowering::getConstraintType(Constraint);
1043 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1044 /// return a list of registers that can be used to satisfy the constraint.
1045 /// This should only be used for C_RegisterClass constraints.
1046 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1047 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
1049 if (Constraint.size() == 1) {
1050 switch (Constraint[0]) {
1052 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1054 if (VT == MVT::f32) {
1055 if (Subtarget->isSingleFloat())
1056 return std::make_pair(0U, Mips::FGR32RegisterClass);
1058 return std::make_pair(0U, Mips::AFGR32RegisterClass);
1061 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1062 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1065 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1068 /// Given a register class constraint, like 'r', if this corresponds directly
1069 /// to an LLVM register class, return a register of 0 and the register class
1071 std::vector<unsigned> MipsTargetLowering::
1072 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1075 if (Constraint.size() != 1)
1076 return std::vector<unsigned>();
1078 switch (Constraint[0]) {
1081 // GCC Mips Constraint Letters
1084 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1085 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1086 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1090 if (VT == MVT::f32) {
1091 if (Subtarget->isSingleFloat())
1092 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1093 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1094 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1095 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1096 Mips::F30, Mips::F31, 0);
1098 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1099 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1100 Mips::F28, Mips::F30, 0);
1104 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1105 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1106 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1107 Mips::D14, Mips::D15, 0);
1109 return std::vector<unsigned>();