1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "MipsTargetObjectFile.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
37 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
39 case MipsISD::JmpLink : return "MipsISD::JmpLink";
40 case MipsISD::Hi : return "MipsISD::Hi";
41 case MipsISD::Lo : return "MipsISD::Lo";
42 case MipsISD::GPRel : return "MipsISD::GPRel";
43 case MipsISD::Ret : return "MipsISD::Ret";
44 case MipsISD::CMov : return "MipsISD::CMov";
45 case MipsISD::SelectCC : return "MipsISD::SelectCC";
46 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
47 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
48 case MipsISD::FPCmp : return "MipsISD::FPCmp";
49 case MipsISD::FPRound : return "MipsISD::FPRound";
50 default : return NULL;
55 MipsTargetLowering(MipsTargetMachine &TM)
56 : TargetLowering(TM, new MipsTargetObjectFile()) {
57 Subtarget = &TM.getSubtarget<MipsSubtarget>();
59 // Mips does not have i1 type, so use i32 for
60 // setcc operations results (slt, sgt, ...).
61 setBooleanContents(ZeroOrOneBooleanContent);
63 // Set up the register classes
64 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
65 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
67 // When dealing with single precision only, use libcalls
68 if (!Subtarget->isSingleFloat())
69 if (!Subtarget->isFP64bit())
70 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
72 // Load extented operations for i1 types must be promoted
73 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
74 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
75 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
77 // MIPS doesn't have extending float->double load/store
78 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
79 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
81 // Used by legalize types to correctly generate the setcc result.
82 // Without this, every float setcc comes with a AND/OR with the result,
83 // we don't want this, since the fpcmp result goes to a flag register,
84 // which is used implicitly by brcond and select operations.
85 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
87 // Mips Custom Operations
88 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
89 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
90 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
91 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
92 setOperationAction(ISD::SELECT, MVT::f32, Custom);
93 setOperationAction(ISD::SELECT, MVT::f64, Custom);
94 setOperationAction(ISD::SELECT, MVT::i32, Custom);
95 setOperationAction(ISD::SETCC, MVT::f32, Custom);
96 setOperationAction(ISD::SETCC, MVT::f64, Custom);
97 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
98 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
99 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
100 setOperationAction(ISD::VASTART, MVT::Other, Custom);
103 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
104 // with operands comming from setcc fp comparions. This is necessary since
105 // the result from these setcc are in a flag registers (FCR31).
106 setOperationAction(ISD::AND, MVT::i32, Custom);
107 setOperationAction(ISD::OR, MVT::i32, Custom);
109 // Operations not directly supported by Mips.
110 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
111 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
112 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
113 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
114 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
115 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
116 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
117 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
118 setOperationAction(ISD::ROTL, MVT::i32, Expand);
119 setOperationAction(ISD::ROTR, MVT::i32, Expand);
120 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
121 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
122 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
123 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
124 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
125 setOperationAction(ISD::FSIN, MVT::f32, Expand);
126 setOperationAction(ISD::FCOS, MVT::f32, Expand);
127 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
128 setOperationAction(ISD::FPOW, MVT::f32, Expand);
129 setOperationAction(ISD::FLOG, MVT::f32, Expand);
130 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
131 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
132 setOperationAction(ISD::FEXP, MVT::f32, Expand);
134 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
136 // Use the default for now
137 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
138 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
139 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
141 if (Subtarget->isSingleFloat())
142 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
144 if (!Subtarget->hasSEInReg()) {
145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
149 if (!Subtarget->hasBitCount())
150 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
152 if (!Subtarget->hasSwap())
153 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
155 setStackPointerRegisterToSaveRestore(Mips::SP);
156 computeRegisterProperties();
159 MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
163 /// getFunctionAlignment - Return the Log2 alignment of this function.
164 unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const {
168 SDValue MipsTargetLowering::
169 LowerOperation(SDValue Op, SelectionDAG &DAG) const
171 switch (Op.getOpcode())
173 case ISD::AND: return LowerANDOR(Op, DAG);
174 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
175 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
176 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
177 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
178 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
179 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
180 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
181 case ISD::OR: return LowerANDOR(Op, DAG);
182 case ISD::SELECT: return LowerSELECT(Op, DAG);
183 case ISD::SETCC: return LowerSETCC(Op, DAG);
184 case ISD::VASTART: return LowerVASTART(Op, DAG);
189 //===----------------------------------------------------------------------===//
190 // Lower helper functions
191 //===----------------------------------------------------------------------===//
193 // AddLiveIn - This helper function adds the specified physical register to the
194 // MachineFunction as a live in value. It also creates a corresponding
195 // virtual register for it.
197 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
199 assert(RC->contains(PReg) && "Not the correct regclass!");
200 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
201 MF.getRegInfo().addLiveIn(PReg, VReg);
205 // Get fp branch code (not opcode) from condition code.
206 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
207 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
208 return Mips::BRANCH_T;
210 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
211 return Mips::BRANCH_F;
213 return Mips::BRANCH_INVALID;
216 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
219 llvm_unreachable("Unknown branch code");
220 case Mips::BRANCH_T : return Mips::BC1T;
221 case Mips::BRANCH_F : return Mips::BC1F;
222 case Mips::BRANCH_TL : return Mips::BC1TL;
223 case Mips::BRANCH_FL : return Mips::BC1FL;
227 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
229 default: llvm_unreachable("Unknown fp condition code!");
231 case ISD::SETOEQ: return Mips::FCOND_EQ;
232 case ISD::SETUNE: return Mips::FCOND_OGL;
234 case ISD::SETOLT: return Mips::FCOND_OLT;
236 case ISD::SETOGT: return Mips::FCOND_OGT;
238 case ISD::SETOLE: return Mips::FCOND_OLE;
240 case ISD::SETOGE: return Mips::FCOND_OGE;
241 case ISD::SETULT: return Mips::FCOND_ULT;
242 case ISD::SETULE: return Mips::FCOND_ULE;
243 case ISD::SETUGT: return Mips::FCOND_UGT;
244 case ISD::SETUGE: return Mips::FCOND_UGE;
245 case ISD::SETUO: return Mips::FCOND_UN;
246 case ISD::SETO: return Mips::FCOND_OR;
248 case ISD::SETONE: return Mips::FCOND_NEQ;
249 case ISD::SETUEQ: return Mips::FCOND_UEQ;
254 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
255 MachineBasicBlock *BB,
256 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
257 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
258 bool isFPCmp = false;
259 DebugLoc dl = MI->getDebugLoc();
261 switch (MI->getOpcode()) {
262 default: assert(false && "Unexpected instr type to insert");
263 case Mips::Select_FCC:
264 case Mips::Select_FCC_S32:
265 case Mips::Select_FCC_D32:
266 isFPCmp = true; // FALL THROUGH
267 case Mips::Select_CC:
268 case Mips::Select_CC_S32:
269 case Mips::Select_CC_D32: {
270 // To "insert" a SELECT_CC instruction, we actually have to insert the
271 // diamond control-flow pattern. The incoming instruction knows the
272 // destination vreg to set, the condition code register to branch on, the
273 // true/false values to select between, and a branch opcode to use.
274 const BasicBlock *LLVM_BB = BB->getBasicBlock();
275 MachineFunction::iterator It = BB;
282 // bNE r1, r0, copy1MBB
283 // fallthrough --> copy0MBB
284 MachineBasicBlock *thisMBB = BB;
285 MachineFunction *F = BB->getParent();
286 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
287 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
289 // Emit the right instruction according to the type of the operands compared
291 // Find the condiction code present in the setcc operation.
292 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
293 // Get the branch opcode from the branch code.
294 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
295 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
297 BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
298 .addReg(Mips::ZERO).addMBB(sinkMBB);
300 F->insert(It, copy0MBB);
301 F->insert(It, sinkMBB);
302 // Update machine-CFG edges by first adding all successors of the current
303 // block to the new block which will contain the Phi node for the select.
304 // Also inform sdisel of the edge changes.
305 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
306 e = BB->succ_end(); i != e; ++i) {
307 EM->insert(std::make_pair(*i, sinkMBB));
308 sinkMBB->addSuccessor(*i);
310 // Next, remove all successors of the current block, and add the true
311 // and fallthrough blocks as its successors.
312 while(!BB->succ_empty())
313 BB->removeSuccessor(BB->succ_begin());
314 BB->addSuccessor(copy0MBB);
315 BB->addSuccessor(sinkMBB);
319 // # fallthrough to sinkMBB
322 // Update machine-CFG edges
323 BB->addSuccessor(sinkMBB);
326 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
329 BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg())
330 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
331 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
333 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
339 //===----------------------------------------------------------------------===//
340 // Misc Lower Operation implementation
341 //===----------------------------------------------------------------------===//
343 SDValue MipsTargetLowering::
344 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
346 if (!Subtarget->isMips1())
349 MachineFunction &MF = DAG.getMachineFunction();
350 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
352 SDValue Chain = DAG.getEntryNode();
353 DebugLoc dl = Op.getDebugLoc();
354 SDValue Src = Op.getOperand(0);
356 // Set the condition register
357 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
358 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
359 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
361 SDValue Cst = DAG.getConstant(3, MVT::i32);
362 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
363 Cst = DAG.getConstant(2, MVT::i32);
364 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
366 SDValue InFlag(0, 0);
367 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
369 // Emit the round instruction and bit convert to integer
370 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
371 Src, CondReg.getValue(1));
372 SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Trunc);
376 SDValue MipsTargetLowering::
377 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
379 SDValue Chain = Op.getOperand(0);
380 SDValue Size = Op.getOperand(1);
381 DebugLoc dl = Op.getDebugLoc();
383 // Get a reference from Mips stack pointer
384 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
386 // Subtract the dynamic size from the actual stack size to
387 // obtain the new stack size.
388 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
390 // The Sub result contains the new stack start address, so it
391 // must be placed in the stack pointer register.
392 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
394 // This node always has two return values: a new stack pointer
396 SDValue Ops[2] = { Sub, Chain };
397 return DAG.getMergeValues(Ops, 2, dl);
400 SDValue MipsTargetLowering::
401 LowerANDOR(SDValue Op, SelectionDAG &DAG) const
403 SDValue LHS = Op.getOperand(0);
404 SDValue RHS = Op.getOperand(1);
405 DebugLoc dl = Op.getDebugLoc();
407 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
410 SDValue True = DAG.getConstant(1, MVT::i32);
411 SDValue False = DAG.getConstant(0, MVT::i32);
413 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
414 LHS, True, False, LHS.getOperand(2));
415 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
416 RHS, True, False, RHS.getOperand(2));
418 return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
421 SDValue MipsTargetLowering::
422 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
424 // The first operand is the chain, the second is the condition, the third is
425 // the block to branch to if the condition is true.
426 SDValue Chain = Op.getOperand(0);
427 SDValue Dest = Op.getOperand(2);
428 DebugLoc dl = Op.getDebugLoc();
430 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
433 SDValue CondRes = Op.getOperand(1);
434 SDValue CCNode = CondRes.getOperand(2);
436 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
437 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
439 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
443 SDValue MipsTargetLowering::
444 LowerSETCC(SDValue Op, SelectionDAG &DAG) const
446 // The operands to this are the left and right operands to compare (ops #0,
447 // and #1) and the condition code to compare them with (op #2) as a
449 SDValue LHS = Op.getOperand(0);
450 SDValue RHS = Op.getOperand(1);
451 DebugLoc dl = Op.getDebugLoc();
453 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
455 return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
456 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
459 SDValue MipsTargetLowering::
460 LowerSELECT(SDValue Op, SelectionDAG &DAG) const
462 SDValue Cond = Op.getOperand(0);
463 SDValue True = Op.getOperand(1);
464 SDValue False = Op.getOperand(2);
465 DebugLoc dl = Op.getDebugLoc();
467 // if the incomming condition comes from a integer compare, the select
468 // operation must be SelectCC or a conditional move if the subtarget
470 if (Cond.getOpcode() != MipsISD::FPCmp) {
471 if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
473 return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(),
477 // if the incomming condition comes from fpcmp, the select
478 // operation must use FPSelectCC.
479 SDValue CCNode = Cond.getOperand(2);
480 return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
481 Cond, True, False, CCNode);
484 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
485 SelectionDAG &DAG) const {
486 // FIXME there isn't actually debug info here
487 DebugLoc dl = Op.getDebugLoc();
488 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
490 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
491 SDVTList VTs = DAG.getVTList(MVT::i32);
493 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
495 // %gp_rel relocation
496 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
497 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32, 0,
499 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
500 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
501 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
503 // %hi/%lo relocation
504 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32, 0,
505 MipsII::MO_ABS_HILO);
506 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GA, 1);
507 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
508 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
511 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32, 0,
513 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
514 DAG.getEntryNode(), GA, NULL, 0,
516 // On functions and global targets not internal linked only
517 // a load from got/GP is necessary for PIC to work.
518 if (!GV->hasLocalLinkage() || isa<Function>(GV))
520 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
521 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
524 llvm_unreachable("Dont know how to handle GlobalAddress");
528 SDValue MipsTargetLowering::
529 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
531 llvm_unreachable("TLS not implemented for MIPS.");
532 return SDValue(); // Not reached
535 SDValue MipsTargetLowering::
536 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
540 // FIXME there isn't actually debug info here
541 DebugLoc dl = Op.getDebugLoc();
542 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
543 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HILO;
545 EVT PtrVT = Op.getValueType();
546 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
548 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
551 SDValue Ops[] = { JTI };
552 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
553 } else // Emit Load from Global Pointer
554 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0,
557 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
558 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
563 SDValue MipsTargetLowering::
564 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
567 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
568 const Constant *C = N->getConstVal();
569 // FIXME there isn't actually debug info here
570 DebugLoc dl = Op.getDebugLoc();
573 // FIXME: we should reference the constant pool using small data sections,
574 // but the asm printer currently doens't support this feature without
575 // hacking it. This feature should come soon so we can uncomment the
577 //if (IsInSmallSection(C->getType())) {
578 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
579 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
580 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
582 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
583 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
584 N->getOffset(), MipsII::MO_ABS_HILO);
585 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
586 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
587 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
589 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
590 N->getOffset(), MipsII::MO_GOT);
591 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(),
592 CP, NULL, 0, false, false, 0);
593 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
594 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
600 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
601 MachineFunction &MF = DAG.getMachineFunction();
602 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
604 DebugLoc dl = Op.getDebugLoc();
605 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
608 // vastart just stores the address of the VarArgsFrameIndex slot into the
609 // memory location argument.
610 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
611 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), SV, 0,
615 //===----------------------------------------------------------------------===//
616 // Calling Convention Implementation
617 //===----------------------------------------------------------------------===//
619 #include "MipsGenCallingConv.inc"
621 //===----------------------------------------------------------------------===//
622 // TODO: Implement a generic logic using tblgen that can support this.
623 // Mips O32 ABI rules:
625 // i32 - Passed in A0, A1, A2, A3 and stack
626 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
627 // an argument. Otherwise, passed in A1, A2, A3 and stack.
628 // f64 - Only passed in two aliased f32 registers if no int reg has been used
629 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
630 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
632 //===----------------------------------------------------------------------===//
634 static bool CC_MipsO32(unsigned ValNo, EVT ValVT,
635 EVT LocVT, CCValAssign::LocInfo LocInfo,
636 ISD::ArgFlagsTy ArgFlags, CCState &State) {
638 static const unsigned IntRegsSize=4, FloatRegsSize=2;
640 static const unsigned IntRegs[] = {
641 Mips::A0, Mips::A1, Mips::A2, Mips::A3
643 static const unsigned F32Regs[] = {
646 static const unsigned F64Regs[] = {
651 unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
652 bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0)));
654 // Promote i8 and i16
655 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
657 if (ArgFlags.isSExt())
658 LocInfo = CCValAssign::SExt;
659 else if (ArgFlags.isZExt())
660 LocInfo = CCValAssign::ZExt;
662 LocInfo = CCValAssign::AExt;
665 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) {
666 Reg = State.AllocateReg(IntRegs, IntRegsSize);
671 if (ValVT.isFloatingPoint() && !IntRegUsed) {
672 if (ValVT == MVT::f32)
673 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
675 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
678 if (ValVT == MVT::f64 && IntRegUsed) {
679 if (UnallocIntReg != IntRegsSize) {
680 // If we hit register A3 as the first not allocated, we must
681 // mark it as allocated (shadow) and use the stack instead.
682 if (IntRegs[UnallocIntReg] != (unsigned (Mips::A3)))
684 for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg)
685 State.AllocateReg(UnallocIntReg);
691 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
692 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
693 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
695 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
697 return false; // CC must always match
700 static bool CC_MipsO32_VarArgs(unsigned ValNo, EVT ValVT,
701 EVT LocVT, CCValAssign::LocInfo LocInfo,
702 ISD::ArgFlagsTy ArgFlags, CCState &State) {
704 static const unsigned IntRegsSize=4;
706 static const unsigned IntRegs[] = {
707 Mips::A0, Mips::A1, Mips::A2, Mips::A3
710 // Promote i8 and i16
711 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
713 if (ArgFlags.isSExt())
714 LocInfo = CCValAssign::SExt;
715 else if (ArgFlags.isZExt())
716 LocInfo = CCValAssign::ZExt;
718 LocInfo = CCValAssign::AExt;
721 if (ValVT == MVT::i32 || ValVT == MVT::f32) {
722 if (unsigned Reg = State.AllocateReg(IntRegs, IntRegsSize)) {
723 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
726 unsigned Off = State.AllocateStack(4, 4);
727 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Off, LocVT, LocInfo));
731 unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
732 if (ValVT == MVT::f64) {
733 if (IntRegs[UnallocIntReg] == (unsigned (Mips::A1))) {
734 // A1 can't be used anymore, because 64 bit arguments
735 // must be aligned when copied back to the caller stack
736 State.AllocateReg(IntRegs, IntRegsSize);
740 if (IntRegs[UnallocIntReg] == (unsigned (Mips::A0)) ||
741 IntRegs[UnallocIntReg] == (unsigned (Mips::A2))) {
742 unsigned Reg = State.AllocateReg(IntRegs, IntRegsSize);
743 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
744 // Shadow the next register so it can be used
745 // later to get the other 32bit part.
746 State.AllocateReg(IntRegs, IntRegsSize);
750 // Register is shadowed to preserve alignment, and the
751 // argument goes to a stack location.
752 if (UnallocIntReg != IntRegsSize)
753 State.AllocateReg(IntRegs, IntRegsSize);
755 unsigned Off = State.AllocateStack(8, 8);
756 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Off, LocVT, LocInfo));
760 return true; // CC didn't match
763 //===----------------------------------------------------------------------===//
764 // Call Calling Convention Implementation
765 //===----------------------------------------------------------------------===//
767 /// LowerCall - functions arguments are copied from virtual regs to
768 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
769 /// TODO: isTailCall.
771 MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
772 CallingConv::ID CallConv, bool isVarArg,
774 const SmallVectorImpl<ISD::OutputArg> &Outs,
775 const SmallVectorImpl<ISD::InputArg> &Ins,
776 DebugLoc dl, SelectionDAG &DAG,
777 SmallVectorImpl<SDValue> &InVals) const {
778 // MIPs target does not yet support tail call optimization.
781 MachineFunction &MF = DAG.getMachineFunction();
782 MachineFrameInfo *MFI = MF.getFrameInfo();
783 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
785 // Analyze operands of the call, assigning locations to each operand.
786 SmallVector<CCValAssign, 16> ArgLocs;
787 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
790 // To meet O32 ABI, Mips must always allocate 16 bytes on
791 // the stack (even if less than 4 are used as arguments)
792 if (Subtarget->isABI_O32()) {
793 int VTsize = EVT(MVT::i32).getSizeInBits()/8;
794 MFI->CreateFixedObject(VTsize, (VTsize*3), true, false);
795 CCInfo.AnalyzeCallOperands(Outs,
796 isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32);
798 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
800 // Get a count of how many bytes are to be pushed on the stack.
801 unsigned NumBytes = CCInfo.getNextStackOffset();
802 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
804 // With EABI is it possible to have 16 args on registers.
805 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
806 SmallVector<SDValue, 8> MemOpChains;
808 // First/LastArgStackLoc contains the first/last
809 // "at stack" argument location.
810 int LastArgStackLoc = 0;
811 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
813 // Walk the register/memloc assignments, inserting copies/loads.
814 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
815 SDValue Arg = Outs[i].Val;
816 CCValAssign &VA = ArgLocs[i];
818 // Promote the value if needed.
819 switch (VA.getLocInfo()) {
820 default: llvm_unreachable("Unknown loc info!");
821 case CCValAssign::Full:
822 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
823 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
824 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg);
825 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
826 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
827 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
828 DAG.getConstant(0, getPointerTy()));
829 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
830 DAG.getConstant(1, getPointerTy()));
831 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
832 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
837 case CCValAssign::SExt:
838 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
840 case CCValAssign::ZExt:
841 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
843 case CCValAssign::AExt:
844 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
848 // Arguments that can be passed on register must be kept at
851 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
855 // Register can't get to this point...
856 assert(VA.isMemLoc());
858 // Create the frame index object for this incoming parameter
859 // This guarantees that when allocating Local Area the firsts
860 // 16 bytes which are alwayes reserved won't be overwritten
861 // if O32 ABI is used. For EABI the first address is zero.
862 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
863 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
864 LastArgStackLoc, true, false);
866 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
868 // emit ISD::STORE whichs stores the
869 // parameter value to a stack Location
870 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
874 // Transform all store nodes into one single node because all store
875 // nodes are independent of each other.
876 if (!MemOpChains.empty())
877 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
878 &MemOpChains[0], MemOpChains.size());
880 // Build a sequence of copy-to-reg nodes chained together with token
881 // chain and flag operands which copy the outgoing args into registers.
882 // The InFlag in necessary since all emited instructions must be
885 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
886 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
887 RegsToPass[i].second, InFlag);
888 InFlag = Chain.getValue(1);
891 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
892 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
893 // node so that legalize doesn't hack it.
894 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
895 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
896 Callee = DAG.getTargetGlobalAddress(G->getGlobal(),
897 getPointerTy(), 0, OpFlag);
898 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
899 Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
900 getPointerTy(), OpFlag);
902 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
903 // = Chain, Callee, Reg#1, Reg#2, ...
905 // Returns a chain & a flag for retval copy to use.
906 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
907 SmallVector<SDValue, 8> Ops;
908 Ops.push_back(Chain);
909 Ops.push_back(Callee);
911 // Add argument registers to the end of the list so that they are
912 // known live into the call.
913 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
914 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
915 RegsToPass[i].second.getValueType()));
917 if (InFlag.getNode())
918 Ops.push_back(InFlag);
920 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
921 InFlag = Chain.getValue(1);
923 // Create a stack location to hold GP when PIC is used. This stack
924 // location is used on function prologue to save GP and also after all
925 // emited CALL's to restore GP.
927 // Function can have an arbitrary number of calls, so
928 // hold the LastArgStackLoc with the biggest offset.
930 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
931 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
932 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
933 // Create the frame index only once. SPOffset here can be anything
934 // (this will be fixed on processFunctionBeforeFrameFinalized)
935 if (MipsFI->getGPStackOffset() == -1) {
936 FI = MFI->CreateFixedObject(4, 0, true, false);
939 MipsFI->setGPStackOffset(LastArgStackLoc);
943 FI = MipsFI->getGPFI();
944 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
945 SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0,
947 Chain = GPLoad.getValue(1);
948 Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
949 GPLoad, SDValue(0,0));
950 InFlag = Chain.getValue(1);
953 // Create the CALLSEQ_END node.
954 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
955 DAG.getIntPtrConstant(0, true), InFlag);
956 InFlag = Chain.getValue(1);
958 // Handle result values, copying them out of physregs into vregs that we
960 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
961 Ins, dl, DAG, InVals);
964 /// LowerCallResult - Lower the result values of a call into the
965 /// appropriate copies out of appropriate physical registers.
967 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
968 CallingConv::ID CallConv, bool isVarArg,
969 const SmallVectorImpl<ISD::InputArg> &Ins,
970 DebugLoc dl, SelectionDAG &DAG,
971 SmallVectorImpl<SDValue> &InVals) const {
973 // Assign locations to each value returned by this call.
974 SmallVector<CCValAssign, 16> RVLocs;
975 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
976 RVLocs, *DAG.getContext());
978 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
980 // Copy all of the result registers out of their specified physreg.
981 for (unsigned i = 0; i != RVLocs.size(); ++i) {
982 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
983 RVLocs[i].getValVT(), InFlag).getValue(1);
984 InFlag = Chain.getValue(2);
985 InVals.push_back(Chain.getValue(0));
991 //===----------------------------------------------------------------------===//
992 // Formal Arguments Calling Convention Implementation
993 //===----------------------------------------------------------------------===//
995 /// LowerFormalArguments - transform physical registers into virtual registers
996 /// and generate load operations for arguments places on the stack.
998 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
999 CallingConv::ID CallConv, bool isVarArg,
1000 const SmallVectorImpl<ISD::InputArg>
1002 DebugLoc dl, SelectionDAG &DAG,
1003 SmallVectorImpl<SDValue> &InVals)
1006 MachineFunction &MF = DAG.getMachineFunction();
1007 MachineFrameInfo *MFI = MF.getFrameInfo();
1008 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1010 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
1011 MipsFI->setVarArgsFrameIndex(0);
1013 // Used with vargs to acumulate store chains.
1014 std::vector<SDValue> OutChains;
1016 // Keep track of the last register used for arguments
1017 unsigned ArgRegEnd = 0;
1019 // Assign locations to all of the incoming arguments.
1020 SmallVector<CCValAssign, 16> ArgLocs;
1021 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1022 ArgLocs, *DAG.getContext());
1024 if (Subtarget->isABI_O32())
1025 CCInfo.AnalyzeFormalArguments(Ins,
1026 isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32);
1028 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
1032 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
1034 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1035 CCValAssign &VA = ArgLocs[i];
1037 // Arguments stored on registers
1038 if (VA.isRegLoc()) {
1039 EVT RegVT = VA.getLocVT();
1040 ArgRegEnd = VA.getLocReg();
1041 TargetRegisterClass *RC = 0;
1043 if (RegVT == MVT::i32)
1044 RC = Mips::CPURegsRegisterClass;
1045 else if (RegVT == MVT::f32)
1046 RC = Mips::FGR32RegisterClass;
1047 else if (RegVT == MVT::f64) {
1048 if (!Subtarget->isSingleFloat())
1049 RC = Mips::AFGR64RegisterClass;
1051 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
1053 // Transform the arguments stored on
1054 // physical registers into virtual ones
1055 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
1056 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1058 // If this is an 8 or 16-bit value, it has been passed promoted
1059 // to 32 bits. Insert an assert[sz]ext to capture this, then
1060 // truncate to the right size.
1061 if (VA.getLocInfo() != CCValAssign::Full) {
1062 unsigned Opcode = 0;
1063 if (VA.getLocInfo() == CCValAssign::SExt)
1064 Opcode = ISD::AssertSext;
1065 else if (VA.getLocInfo() == CCValAssign::ZExt)
1066 Opcode = ISD::AssertZext;
1068 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
1069 DAG.getValueType(VA.getValVT()));
1070 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1073 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
1074 if (Subtarget->isABI_O32()) {
1075 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
1076 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
1077 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
1078 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
1079 VA.getLocReg()+1, RC);
1080 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
1081 SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
1082 SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2);
1083 ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi);
1087 InVals.push_back(ArgValue);
1088 } else { // VA.isRegLoc()
1091 assert(VA.isMemLoc());
1093 // The last argument is not a register anymore
1096 // The stack pointer offset is relative to the caller stack frame.
1097 // Since the real stack size is unknown here, a negative SPOffset
1098 // is used so there's a way to adjust these offsets when the stack
1099 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1100 // used instead of a direct negative address (which is recorded to
1101 // be used on emitPrologue) to avoid mis-calc of the first stack
1102 // offset on PEI::calculateFrameObjectOffsets.
1103 // Arguments are always 32-bit.
1104 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1105 int FI = MFI->CreateFixedObject(ArgSize, 0, true, false);
1106 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
1107 (FirstStackArgLoc + VA.getLocMemOffset())));
1109 // Create load nodes to retrieve arguments from the stack
1110 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1111 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0,
1116 // The mips ABIs for returning structs by value requires that we copy
1117 // the sret argument into $v0 for the return. Save the argument into
1118 // a virtual register so that we can access it from the return points.
1119 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1120 unsigned Reg = MipsFI->getSRetReturnReg();
1122 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1123 MipsFI->setSRetReturnReg(Reg);
1125 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1126 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1129 // To meet ABI, when VARARGS are passed on registers, the registers
1130 // must have their values written to the caller stack frame. If the last
1131 // argument was placed in the stack, there's no need to save any register.
1132 if ((isVarArg) && (Subtarget->isABI_O32() && ArgRegEnd)) {
1133 if (StackPtr.getNode() == 0)
1134 StackPtr = DAG.getRegister(StackReg, getPointerTy());
1136 // The last register argument that must be saved is Mips::A3
1137 TargetRegisterClass *RC = Mips::CPURegsRegisterClass;
1138 unsigned StackLoc = ArgLocs.size()-1;
1140 for (++ArgRegEnd; ArgRegEnd <= Mips::A3; ++ArgRegEnd, ++StackLoc) {
1141 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
1142 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
1144 int FI = MFI->CreateFixedObject(4, 0, true, false);
1145 MipsFI->recordStoreVarArgsFI(FI, -(4+(StackLoc*4)));
1146 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
1147 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, NULL, 0,
1150 // Record the frame index of the first variable argument
1151 // which is a value necessary to VASTART.
1152 if (!MipsFI->getVarArgsFrameIndex())
1153 MipsFI->setVarArgsFrameIndex(FI);
1157 // All stores are grouped in one node to allow the matching between
1158 // the size of Ins and InVals. This only happens when on varg functions
1159 if (!OutChains.empty()) {
1160 OutChains.push_back(Chain);
1161 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1162 &OutChains[0], OutChains.size());
1168 //===----------------------------------------------------------------------===//
1169 // Return Value Calling Convention Implementation
1170 //===----------------------------------------------------------------------===//
1173 MipsTargetLowering::LowerReturn(SDValue Chain,
1174 CallingConv::ID CallConv, bool isVarArg,
1175 const SmallVectorImpl<ISD::OutputArg> &Outs,
1176 DebugLoc dl, SelectionDAG &DAG) const {
1178 // CCValAssign - represent the assignment of
1179 // the return value to a location
1180 SmallVector<CCValAssign, 16> RVLocs;
1182 // CCState - Info about the registers and stack slot.
1183 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1184 RVLocs, *DAG.getContext());
1186 // Analize return values.
1187 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
1189 // If this is the first return lowered for this function, add
1190 // the regs to the liveout set for the function.
1191 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1192 for (unsigned i = 0; i != RVLocs.size(); ++i)
1193 if (RVLocs[i].isRegLoc())
1194 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1199 // Copy the result values into the output registers.
1200 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1201 CCValAssign &VA = RVLocs[i];
1202 assert(VA.isRegLoc() && "Can only return in registers!");
1204 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1207 // guarantee that all emitted copies are
1208 // stuck together, avoiding something bad
1209 Flag = Chain.getValue(1);
1212 // The mips ABIs for returning structs by value requires that we copy
1213 // the sret argument into $v0 for the return. We saved the argument into
1214 // a virtual register in the entry block, so now we copy the value out
1216 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1217 MachineFunction &MF = DAG.getMachineFunction();
1218 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1219 unsigned Reg = MipsFI->getSRetReturnReg();
1222 llvm_unreachable("sret virtual register not created in the entry block");
1223 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1225 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1226 Flag = Chain.getValue(1);
1229 // Return on Mips is always a "jr $ra"
1231 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1232 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1234 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1235 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1238 //===----------------------------------------------------------------------===//
1239 // Mips Inline Assembly Support
1240 //===----------------------------------------------------------------------===//
1242 /// getConstraintType - Given a constraint letter, return the type of
1243 /// constraint it is for this target.
1244 MipsTargetLowering::ConstraintType MipsTargetLowering::
1245 getConstraintType(const std::string &Constraint) const
1247 // Mips specific constrainy
1248 // GCC config/mips/constraints.md
1250 // 'd' : An address register. Equivalent to r
1251 // unless generating MIPS16 code.
1252 // 'y' : Equivalent to r; retained for
1253 // backwards compatibility.
1254 // 'f' : Floating Point registers.
1255 if (Constraint.size() == 1) {
1256 switch (Constraint[0]) {
1261 return C_RegisterClass;
1265 return TargetLowering::getConstraintType(Constraint);
1268 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1269 /// return a list of registers that can be used to satisfy the constraint.
1270 /// This should only be used for C_RegisterClass constraints.
1271 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1272 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
1274 if (Constraint.size() == 1) {
1275 switch (Constraint[0]) {
1277 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1280 return std::make_pair(0U, Mips::FGR32RegisterClass);
1282 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1283 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1286 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1289 /// Given a register class constraint, like 'r', if this corresponds directly
1290 /// to an LLVM register class, return a register of 0 and the register class
1292 std::vector<unsigned> MipsTargetLowering::
1293 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1296 if (Constraint.size() != 1)
1297 return std::vector<unsigned>();
1299 switch (Constraint[0]) {
1302 // GCC Mips Constraint Letters
1305 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1306 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1307 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1311 if (VT == MVT::f32) {
1312 if (Subtarget->isSingleFloat())
1313 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1314 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1315 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1316 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1317 Mips::F30, Mips::F31, 0);
1319 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1320 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1321 Mips::F28, Mips::F30, 0);
1325 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1326 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1327 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1328 Mips::D14, Mips::D15, 0);
1330 return std::vector<unsigned>();
1334 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1335 // The Mips target isn't yet aware of offsets.
1339 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
1340 if (VT != MVT::f32 && VT != MVT::f64)
1342 return Imm.isZero();