1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Bruno Cardoso Lopes and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Function.h"
21 #include "llvm/Intrinsics.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/CodeGen/SSARegMap.h"
29 #include "llvm/CodeGen/ValueTypes.h"
30 #include "llvm/Support/Debug.h"
36 const char *MipsTargetLowering::
37 getTargetNodeName(unsigned Opcode) const
41 case MipsISD::JmpLink : return "MipsISD::JmpLink";
42 case MipsISD::Hi : return "MipsISD::Hi";
43 case MipsISD::Lo : return "MipsISD::Lo";
44 case MipsISD::Ret : return "MipsISD::Ret";
45 default : return NULL;
50 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
52 // Mips does not have i1 type, so use i32 for
53 // setcc operations results (slt, sgt, ...).
54 setSetCCResultType(MVT::i32);
55 setSetCCResultContents(ZeroOrOneSetCCResult);
57 // Set up the register classes
58 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
61 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
62 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
63 setOperationAction(ISD::RET, MVT::Other, Custom);
65 // Load extented operations for i1 types must be promoted
66 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
67 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
68 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
70 // Store operations for i1 types must be promoted
71 setStoreXAction(MVT::i1, Promote);
73 // Mips does not have these NodeTypes below.
74 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
75 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
76 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
77 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
78 setOperationAction(ISD::SELECT, MVT::i32, Expand);
80 // Mips not supported intrinsics.
81 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
82 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
83 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
85 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
86 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
87 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
88 setOperationAction(ISD::ROTL , MVT::i32, Expand);
89 setOperationAction(ISD::ROTR , MVT::i32, Expand);
90 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
92 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
93 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
94 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
96 // We don't have line number support yet.
97 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
98 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
99 setOperationAction(ISD::LABEL, MVT::Other, Expand);
101 // Use the default for now
102 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
103 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
105 setStackPointerRegisterToSaveRestore(Mips::SP);
106 computeRegisterProperties();
110 SDOperand MipsTargetLowering::
111 LowerOperation(SDOperand Op, SelectionDAG &DAG)
113 switch (Op.getOpcode())
115 case ISD::CALL: return LowerCALL(Op, DAG);
116 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
117 case ISD::RET: return LowerRET(Op, DAG);
118 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
119 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
120 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
125 //===----------------------------------------------------------------------===//
126 // Lower helper functions
127 //===----------------------------------------------------------------------===//
129 // AddLiveIn - This helper function adds the specified physical register to the
130 // MachineFunction as a live in value. It also creates a corresponding
131 // virtual register for it.
133 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
135 assert(RC->contains(PReg) && "Not the correct regclass!");
136 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
137 MF.addLiveIn(PReg, VReg);
141 // Set up a frame object for the return address.
142 SDOperand MipsTargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
143 if (ReturnAddrIndex == 0) {
144 MachineFunction &MF = DAG.getMachineFunction();
145 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, 0);
148 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
152 //===----------------------------------------------------------------------===//
153 // Misc Lower Operation implementation
154 //===----------------------------------------------------------------------===//
155 SDOperand MipsTargetLowering::
156 LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
158 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
160 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
161 SDOperand Hi = DAG.getNode(MipsISD::Hi, MVT::i32, GA);
162 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
164 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
167 SDOperand MipsTargetLowering::
168 LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG)
170 assert(0 && "TLS not implemented for MIPS.");
173 SDOperand MipsTargetLowering::
174 LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
175 // Depths > 0 not supported yet!
176 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
179 // Just load the return address
180 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
181 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
184 //===----------------------------------------------------------------------===//
185 // Calling Convention Implementation
187 // The lower operations present on calling convention works on this order:
188 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
189 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
190 // LowerRET (virt regs --> phys regs)
191 // LowerCALL (phys regs --> virt regs)
193 //===----------------------------------------------------------------------===//
195 #include "MipsGenCallingConv.inc"
197 //===----------------------------------------------------------------------===//
198 // CALL Calling Convention Implementation
199 //===----------------------------------------------------------------------===//
201 /// Mips custom CALL implementation
202 SDOperand MipsTargetLowering::
203 LowerCALL(SDOperand Op, SelectionDAG &DAG)
205 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
207 // By now, only CallingConv::C implemented
211 assert(0 && "Unsupported calling convention");
212 case CallingConv::Fast:
214 return LowerCCCCallTo(Op, DAG, CallingConv);
218 /// LowerCCCCallTo - functions arguments are copied from virtual
219 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
220 /// CALLSEQ_END are emitted.
221 /// TODO: isVarArg, isTailCall, sret, GOT, linkage types.
222 SDOperand MipsTargetLowering::
223 LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
225 SDOperand Chain = Op.getOperand(0);
226 SDOperand Callee = Op.getOperand(4);
228 // Analyze operands of the call, assigning locations to each operand.
229 SmallVector<CCValAssign, 16> ArgLocs;
230 CCState CCInfo(CC, getTargetMachine(), ArgLocs);
231 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
233 // Get a count of how many bytes are to be pushed on the stack.
234 unsigned NumBytes = CCInfo.getNextStackOffset();
236 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
239 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
240 SmallVector<SDOperand, 8> MemOpChains;
244 // Walk the register/memloc assignments, inserting copies/loads.
245 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
246 CCValAssign &VA = ArgLocs[i];
248 // Arguments start after the 5 first operands of ISD::CALL
249 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
251 // Promote the value if needed.
252 switch (VA.getLocInfo()) {
253 default: assert(0 && "Unknown loc info!");
254 case CCValAssign::Full: break;
255 case CCValAssign::SExt:
256 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
258 case CCValAssign::ZExt:
259 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
261 case CCValAssign::AExt:
262 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
266 // Arguments that can be passed on register,
267 // must be kept at RegsToPass vector
269 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
271 assert(VA.isMemLoc());
272 // Mips::SP holds our stack pointer
273 if (StackPtr.Val == 0)
274 StackPtr = DAG.getRegister(Mips::SP, getPointerTy());
276 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(),
279 // emit a ISD::ADD which emits the final
280 // stack location to place the parameter
281 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
283 // emit ISD::STORE whichs stores the
284 // parameter value to a stack Location
285 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
289 // Transform all store nodes into one single node because
290 // all store nodes ar independent of each other.
291 if (!MemOpChains.empty())
292 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
293 &MemOpChains[0], MemOpChains.size());
295 // Build a sequence of copy-to-reg nodes chained together with token
296 // chain and flag operands which copy the outgoing args into registers.
297 // The InFlag in necessary since all emited instructions must be
300 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
301 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
302 RegsToPass[i].second, InFlag);
303 InFlag = Chain.getValue(1);
306 // If the callee is a GlobalAddress node (quite common, every direct
307 // call is) turn it into a TargetGlobalAddress node so that legalize
309 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
310 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
312 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
313 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
315 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
316 // = Chain, Callee, Reg#1, Reg#2, ...
318 // Returns a chain & a flag for retval copy to use.
319 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
320 SmallVector<SDOperand, 8> Ops;
321 Ops.push_back(Chain);
322 Ops.push_back(Callee);
324 // Add argument registers to the end of the list so that they are
325 // known live into the call.
326 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
327 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
328 RegsToPass[i].second.getValueType()));
331 Ops.push_back(InFlag);
333 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
334 InFlag = Chain.getValue(1);
336 // Create the CALLSEQ_END node.
337 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
339 Ops.push_back(Chain);
340 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
341 Ops.push_back(InFlag);
342 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
343 InFlag = Chain.getValue(1);
345 // Handle result values, copying them out of physregs into vregs that we
347 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
350 /// LowerCallResult - Lower the result values of an ISD::CALL into the
351 /// appropriate copies out of appropriate physical registers. This assumes that
352 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
353 /// being lowered. Returns a SDNode with the same number of values as the
355 SDNode *MipsTargetLowering::
356 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
357 unsigned CallingConv, SelectionDAG &DAG) {
359 // Assign locations to each value returned by this call.
360 SmallVector<CCValAssign, 16> RVLocs;
361 CCState CCInfo(CallingConv, getTargetMachine(), RVLocs);
362 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
363 SmallVector<SDOperand, 8> ResultVals;
369 // Copy all of the result registers out of their specified physreg.
370 for (unsigned i = 0; i != RVLocs.size(); ++i) {
371 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
372 RVLocs[i].getValVT(), InFlag).getValue(1);
373 InFlag = Chain.getValue(2);
374 ResultVals.push_back(Chain.getValue(0));
377 // Merge everything together with a MERGE_VALUES node.
378 ResultVals.push_back(Chain);
379 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
380 &ResultVals[0], ResultVals.size()).Val;
383 //===----------------------------------------------------------------------===//
384 // FORMAL_ARGUMENTS Calling Convention Implementation
385 //===----------------------------------------------------------------------===//
387 /// Mips custom FORMAL_ARGUMENTS implementation
388 SDOperand MipsTargetLowering::
389 LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
391 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
395 assert(0 && "Unsupported calling convention");
397 return LowerCCCArguments(Op, DAG);
401 /// LowerCCCArguments - transform physical registers into
402 /// virtual registers and generate load operations for
403 /// arguments places on the stack.
404 /// TODO: isVarArg, sret
405 SDOperand MipsTargetLowering::
406 LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
408 MachineFunction &MF = DAG.getMachineFunction();
409 MachineFrameInfo *MFI = MF.getFrameInfo();
410 SDOperand Root = Op.getOperand(0);
412 // Assign locations to all of the incoming arguments.
413 SmallVector<CCValAssign, 16> ArgLocs;
414 CCState CCInfo(MF.getFunction()->getCallingConv(),
415 getTargetMachine(), ArgLocs);
416 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
417 SmallVector<SDOperand, 8> ArgValues;
419 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
421 CCValAssign &VA = ArgLocs[i];
423 // Arguments stored on registers
425 MVT::ValueType RegVT = VA.getLocVT();
426 TargetRegisterClass *RC;
428 if (RegVT == MVT::i32)
429 RC = Mips::CPURegsRegisterClass;
431 assert(0 && "support only Mips::CPURegsRegisterClass");
433 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
435 // Transform the arguments stored on
436 // physical registers into virtual ones
437 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
439 // If this is an 8 or 16-bit value, it is really passed promoted
440 // to 32 bits. Insert an assert[sz]ext to capture this, then
441 // truncate to the right size.
442 if (VA.getLocInfo() == CCValAssign::SExt)
443 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
444 DAG.getValueType(VA.getValVT()));
445 else if (VA.getLocInfo() == CCValAssign::ZExt)
446 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
447 DAG.getValueType(VA.getValVT()));
449 if (VA.getLocInfo() != CCValAssign::Full)
450 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
452 ArgValues.push_back(ArgValue);
456 assert(VA.isMemLoc());
458 // Create the frame index object for this incoming parameter...
459 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
460 VA.getLocMemOffset());
462 // Create load nodes to retrieve arguments from the stack
463 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
464 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
467 ArgValues.push_back(Root);
471 // Return the new list of results.
472 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
473 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
476 //===----------------------------------------------------------------------===//
477 // Return Value Calling Convention Implementation
478 //===----------------------------------------------------------------------===//
480 SDOperand MipsTargetLowering::
481 LowerRET(SDOperand Op, SelectionDAG &DAG)
483 // CCValAssign - represent the assignment of
484 // the return value to a location
485 SmallVector<CCValAssign, 16> RVLocs;
486 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
488 // CCState - Info about the registers and stack slot.
489 CCState CCInfo(CC, getTargetMachine(), RVLocs);
491 // Analize return values of ISD::RET
492 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
494 // If this is the first return lowered for this function, add
495 // the regs to the liveout set for the function.
496 if (DAG.getMachineFunction().liveout_empty()) {
497 for (unsigned i = 0; i != RVLocs.size(); ++i)
498 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
501 // The chain is always operand #0
502 SDOperand Chain = Op.getOperand(0);
505 // Copy the result values into the output registers.
506 for (unsigned i = 0; i != RVLocs.size(); ++i) {
507 CCValAssign &VA = RVLocs[i];
508 assert(VA.isRegLoc() && "Can only return in registers!");
510 // ISD::RET => ret chain, (regnum1,val1), ...
511 // So i*2+1 index only the regnums
512 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(),
513 Op.getOperand(i*2+1), Flag);
515 // guarantee that all emitted copies are
516 // stuck together, avoiding something bad
517 Flag = Chain.getValue(1);
520 // Return on Mips is always a "jr $ra"
522 return DAG.getNode(MipsISD::Ret, MVT::Other,
523 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
525 return DAG.getNode(MipsISD::Ret, MVT::Other,
526 Chain, DAG.getRegister(Mips::RA, MVT::i32));