1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
37 const char *MipsTargetLowering::
38 getTargetNodeName(unsigned Opcode) const
42 case MipsISD::JmpLink : return "MipsISD::JmpLink";
43 case MipsISD::Hi : return "MipsISD::Hi";
44 case MipsISD::Lo : return "MipsISD::Lo";
45 case MipsISD::GPRel : return "MipsISD::GPRel";
46 case MipsISD::Ret : return "MipsISD::Ret";
47 case MipsISD::CMov : return "MipsISD::CMov";
48 case MipsISD::SelectCC : return "MipsISD::SelectCC";
49 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
50 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
51 case MipsISD::FPCmp : return "MipsISD::FPCmp";
52 case MipsISD::FPRound : return "MipsISD::FPRound";
53 default : return NULL;
58 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
60 Subtarget = &TM.getSubtarget<MipsSubtarget>();
62 // Mips does not have i1 type, so use i32 for
63 // setcc operations results (slt, sgt, ...).
64 setBooleanContents(ZeroOrOneBooleanContent);
66 // JumpTable targets must use GOT when using PIC_
67 setUsesGlobalOffsetTable(true);
69 // Set up the register classes
70 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
71 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
73 // When dealing with single precision only, use libcalls
74 if (!Subtarget->isSingleFloat())
75 if (!Subtarget->isFP64bit())
76 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
79 addLegalFPImmediate(APFloat(+0.0f));
81 // Load extented operations for i1 types must be promoted
82 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
83 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
86 // MIPS doesn't have extending float->double load (?)
87 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
89 // Used by legalize types to correctly generate the setcc result.
90 // Without this, every float setcc comes with a AND/OR with the result,
91 // we don't want this, since the fpcmp result goes to a flag register,
92 // which is used implicitly by brcond and select operations.
93 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
95 // Mips Custom Operations
96 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
97 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
98 setOperationAction(ISD::RET, MVT::Other, Custom);
99 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
100 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
101 setOperationAction(ISD::SELECT, MVT::f32, Custom);
102 setOperationAction(ISD::SELECT, MVT::f64, Custom);
103 setOperationAction(ISD::SELECT, MVT::i32, Custom);
104 setOperationAction(ISD::SETCC, MVT::f32, Custom);
105 setOperationAction(ISD::SETCC, MVT::f64, Custom);
106 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
107 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
108 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
110 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
111 // with operands comming from setcc fp comparions. This is necessary since
112 // the result from these setcc are in a flag registers (FCR31).
113 setOperationAction(ISD::AND, MVT::i32, Custom);
114 setOperationAction(ISD::OR, MVT::i32, Custom);
116 // Operations not directly supported by Mips.
117 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
118 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
119 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
120 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
121 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
123 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
124 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
125 setOperationAction(ISD::ROTL, MVT::i32, Expand);
126 setOperationAction(ISD::ROTR, MVT::i32, Expand);
127 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
128 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
129 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
130 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
131 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
132 setOperationAction(ISD::FSIN, MVT::f32, Expand);
133 setOperationAction(ISD::FCOS, MVT::f32, Expand);
134 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
135 setOperationAction(ISD::FPOW, MVT::f32, Expand);
136 setOperationAction(ISD::FLOG, MVT::f32, Expand);
137 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
138 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
139 setOperationAction(ISD::FEXP, MVT::f32, Expand);
141 // We don't have line number support yet.
142 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
143 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
144 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
145 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
147 // Use the default for now
148 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
149 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
150 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
152 if (Subtarget->isSingleFloat())
153 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
155 if (!Subtarget->hasSEInReg()) {
156 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
157 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
160 if (!Subtarget->hasBitCount())
161 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
163 if (!Subtarget->hasSwap())
164 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
166 setStackPointerRegisterToSaveRestore(Mips::SP);
167 computeRegisterProperties();
170 MVT MipsTargetLowering::getSetCCResultType(MVT VT) const {
174 /// getFunctionAlignment - Return the Log2 alignment of this function.
175 unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const {
179 SDValue MipsTargetLowering::
180 LowerOperation(SDValue Op, SelectionDAG &DAG)
182 switch (Op.getOpcode())
184 case ISD::AND: return LowerANDOR(Op, DAG);
185 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
186 case ISD::CALL: return LowerCALL(Op, DAG);
187 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
188 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
189 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
190 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
191 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
192 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
193 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
194 case ISD::OR: return LowerANDOR(Op, DAG);
195 case ISD::RET: return LowerRET(Op, DAG);
196 case ISD::SELECT: return LowerSELECT(Op, DAG);
197 case ISD::SETCC: return LowerSETCC(Op, DAG);
202 //===----------------------------------------------------------------------===//
203 // Lower helper functions
204 //===----------------------------------------------------------------------===//
206 // AddLiveIn - This helper function adds the specified physical register to the
207 // MachineFunction as a live in value. It also creates a corresponding
208 // virtual register for it.
210 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
212 assert(RC->contains(PReg) && "Not the correct regclass!");
213 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
214 MF.getRegInfo().addLiveIn(PReg, VReg);
218 // A address must be loaded from a small section if its size is less than the
219 // small section size threshold. Data in this section must be addressed using
221 bool MipsTargetLowering::IsInSmallSection(unsigned Size) {
222 return (Size > 0 && (Size <= Subtarget->getSSectionThreshold()));
225 // Discover if this global address can be placed into small data/bss section.
226 bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV)
228 const TargetData *TD = getTargetData();
229 const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV);
234 const Type *Ty = GV->getType()->getElementType();
235 unsigned Size = TD->getTypeAllocSize(Ty);
237 // if this is a internal constant string, there is a special
238 // section for it, but not in small data/bss.
239 if (GVA->hasInitializer() && GV->hasLocalLinkage()) {
240 Constant *C = GVA->getInitializer();
241 const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
242 if (CVA && CVA->isCString())
246 return IsInSmallSection(Size);
249 // Get fp branch code (not opcode) from condition code.
250 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
251 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
252 return Mips::BRANCH_T;
254 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
255 return Mips::BRANCH_F;
257 return Mips::BRANCH_INVALID;
260 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
263 llvm_unreachable("Unknown branch code");
264 case Mips::BRANCH_T : return Mips::BC1T;
265 case Mips::BRANCH_F : return Mips::BC1F;
266 case Mips::BRANCH_TL : return Mips::BC1TL;
267 case Mips::BRANCH_FL : return Mips::BC1FL;
271 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
273 default: llvm_unreachable("Unknown fp condition code!");
275 case ISD::SETOEQ: return Mips::FCOND_EQ;
276 case ISD::SETUNE: return Mips::FCOND_OGL;
278 case ISD::SETOLT: return Mips::FCOND_OLT;
280 case ISD::SETOGT: return Mips::FCOND_OGT;
282 case ISD::SETOLE: return Mips::FCOND_OLE;
284 case ISD::SETOGE: return Mips::FCOND_OGE;
285 case ISD::SETULT: return Mips::FCOND_ULT;
286 case ISD::SETULE: return Mips::FCOND_ULE;
287 case ISD::SETUGT: return Mips::FCOND_UGT;
288 case ISD::SETUGE: return Mips::FCOND_UGE;
289 case ISD::SETUO: return Mips::FCOND_UN;
290 case ISD::SETO: return Mips::FCOND_OR;
292 case ISD::SETONE: return Mips::FCOND_NEQ;
293 case ISD::SETUEQ: return Mips::FCOND_UEQ;
298 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
299 MachineBasicBlock *BB) const {
300 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
301 bool isFPCmp = false;
302 DebugLoc dl = MI->getDebugLoc();
304 switch (MI->getOpcode()) {
305 default: assert(false && "Unexpected instr type to insert");
306 case Mips::Select_FCC:
307 case Mips::Select_FCC_S32:
308 case Mips::Select_FCC_D32:
309 isFPCmp = true; // FALL THROUGH
310 case Mips::Select_CC:
311 case Mips::Select_CC_S32:
312 case Mips::Select_CC_D32: {
313 // To "insert" a SELECT_CC instruction, we actually have to insert the
314 // diamond control-flow pattern. The incoming instruction knows the
315 // destination vreg to set, the condition code register to branch on, the
316 // true/false values to select between, and a branch opcode to use.
317 const BasicBlock *LLVM_BB = BB->getBasicBlock();
318 MachineFunction::iterator It = BB;
325 // bNE r1, r0, copy1MBB
326 // fallthrough --> copy0MBB
327 MachineBasicBlock *thisMBB = BB;
328 MachineFunction *F = BB->getParent();
329 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
330 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
332 // Emit the right instruction according to the type of the operands compared
334 // Find the condiction code present in the setcc operation.
335 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
336 // Get the branch opcode from the branch code.
337 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
338 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
340 BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
341 .addReg(Mips::ZERO).addMBB(sinkMBB);
343 F->insert(It, copy0MBB);
344 F->insert(It, sinkMBB);
345 // Update machine-CFG edges by first adding all successors of the current
346 // block to the new block which will contain the Phi node for the select.
347 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
348 e = BB->succ_end(); i != e; ++i)
349 sinkMBB->addSuccessor(*i);
350 // Next, remove all successors of the current block, and add the true
351 // and fallthrough blocks as its successors.
352 while(!BB->succ_empty())
353 BB->removeSuccessor(BB->succ_begin());
354 BB->addSuccessor(copy0MBB);
355 BB->addSuccessor(sinkMBB);
359 // # fallthrough to sinkMBB
362 // Update machine-CFG edges
363 BB->addSuccessor(sinkMBB);
366 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
369 BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg())
370 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
371 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
373 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
379 //===----------------------------------------------------------------------===//
380 // Misc Lower Operation implementation
381 //===----------------------------------------------------------------------===//
383 SDValue MipsTargetLowering::
384 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG)
386 if (!Subtarget->isMips1())
389 MachineFunction &MF = DAG.getMachineFunction();
390 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
392 SDValue Chain = DAG.getEntryNode();
393 DebugLoc dl = Op.getDebugLoc();
394 SDValue Src = Op.getOperand(0);
396 // Set the condition register
397 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
398 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
399 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
401 SDValue Cst = DAG.getConstant(3, MVT::i32);
402 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
403 Cst = DAG.getConstant(2, MVT::i32);
404 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
406 SDValue InFlag(0, 0);
407 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
409 // Emit the round instruction and bit convert to integer
410 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
411 Src, CondReg.getValue(1));
412 SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Trunc);
416 SDValue MipsTargetLowering::
417 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
419 SDValue Chain = Op.getOperand(0);
420 SDValue Size = Op.getOperand(1);
421 DebugLoc dl = Op.getDebugLoc();
423 // Get a reference from Mips stack pointer
424 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
426 // Subtract the dynamic size from the actual stack size to
427 // obtain the new stack size.
428 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
430 // The Sub result contains the new stack start address, so it
431 // must be placed in the stack pointer register.
432 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
434 // This node always has two return values: a new stack pointer
436 SDValue Ops[2] = { Sub, Chain };
437 return DAG.getMergeValues(Ops, 2, dl);
440 SDValue MipsTargetLowering::
441 LowerANDOR(SDValue Op, SelectionDAG &DAG)
443 SDValue LHS = Op.getOperand(0);
444 SDValue RHS = Op.getOperand(1);
445 DebugLoc dl = Op.getDebugLoc();
447 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
450 SDValue True = DAG.getConstant(1, MVT::i32);
451 SDValue False = DAG.getConstant(0, MVT::i32);
453 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
454 LHS, True, False, LHS.getOperand(2));
455 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
456 RHS, True, False, RHS.getOperand(2));
458 return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
461 SDValue MipsTargetLowering::
462 LowerBRCOND(SDValue Op, SelectionDAG &DAG)
464 // The first operand is the chain, the second is the condition, the third is
465 // the block to branch to if the condition is true.
466 SDValue Chain = Op.getOperand(0);
467 SDValue Dest = Op.getOperand(2);
468 DebugLoc dl = Op.getDebugLoc();
470 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
473 SDValue CondRes = Op.getOperand(1);
474 SDValue CCNode = CondRes.getOperand(2);
476 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
477 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
479 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
483 SDValue MipsTargetLowering::
484 LowerSETCC(SDValue Op, SelectionDAG &DAG)
486 // The operands to this are the left and right operands to compare (ops #0,
487 // and #1) and the condition code to compare them with (op #2) as a
489 SDValue LHS = Op.getOperand(0);
490 SDValue RHS = Op.getOperand(1);
491 DebugLoc dl = Op.getDebugLoc();
493 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
495 return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
496 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
499 SDValue MipsTargetLowering::
500 LowerSELECT(SDValue Op, SelectionDAG &DAG)
502 SDValue Cond = Op.getOperand(0);
503 SDValue True = Op.getOperand(1);
504 SDValue False = Op.getOperand(2);
505 DebugLoc dl = Op.getDebugLoc();
507 // if the incomming condition comes from a integer compare, the select
508 // operation must be SelectCC or a conditional move if the subtarget
510 if (Cond.getOpcode() != MipsISD::FPCmp) {
511 if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
513 return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(),
517 // if the incomming condition comes from fpcmp, the select
518 // operation must use FPSelectCC.
519 SDValue CCNode = Cond.getOperand(2);
520 return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
521 Cond, True, False, CCNode);
524 SDValue MipsTargetLowering::
525 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
527 // FIXME there isn't actually debug info here
528 DebugLoc dl = Op.getDebugLoc();
529 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
530 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
532 if (!Subtarget->hasABICall()) {
533 SDVTList VTs = DAG.getVTList(MVT::i32);
534 SDValue Ops[] = { GA };
535 // %gp_rel relocation
536 if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) {
537 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, Ops, 1);
538 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
539 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
541 // %hi/%lo relocation
542 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1);
543 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
544 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
546 } else { // Abicall relocations, TODO: make this cleaner.
547 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
548 DAG.getEntryNode(), GA, NULL, 0);
549 // On functions and global targets not internal linked only
550 // a load from got/GP is necessary for PIC to work.
551 if (!GV->hasLocalLinkage() || isa<Function>(GV))
553 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
554 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
557 llvm_unreachable("Dont know how to handle GlobalAddress");
561 SDValue MipsTargetLowering::
562 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
564 llvm_unreachable("TLS not implemented for MIPS.");
565 return SDValue(); // Not reached
568 SDValue MipsTargetLowering::
569 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
573 // FIXME there isn't actually debug info here
574 DebugLoc dl = Op.getDebugLoc();
576 MVT PtrVT = Op.getValueType();
577 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
578 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
580 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
581 SDVTList VTs = DAG.getVTList(MVT::i32);
582 SDValue Ops[] = { JTI };
583 HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1);
584 } else // Emit Load from Global Pointer
585 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
587 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
588 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
593 SDValue MipsTargetLowering::
594 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
597 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
598 Constant *C = N->getConstVal();
599 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
600 // FIXME there isn't actually debug info here
601 DebugLoc dl = Op.getDebugLoc();
604 // FIXME: we should reference the constant pool using small data sections,
605 // but the asm printer currently doens't support this feature without
606 // hacking it. This feature should come soon so we can uncomment the
608 //if (!Subtarget->hasABICall() &&
609 // IsInSmallSection(getTargetData()->getTypeAllocSize(C->getType()))) {
610 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
611 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
612 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
613 //} else { // %hi/%lo relocation
614 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
615 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
616 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
622 //===----------------------------------------------------------------------===//
623 // Calling Convention Implementation
625 // The lower operations present on calling convention works on this order:
626 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
627 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
628 // LowerRET (virt regs --> phys regs)
629 // LowerCALL (phys regs --> virt regs)
631 //===----------------------------------------------------------------------===//
633 #include "MipsGenCallingConv.inc"
635 //===----------------------------------------------------------------------===//
636 // TODO: Implement a generic logic using tblgen that can support this.
637 // Mips O32 ABI rules:
639 // i32 - Passed in A0, A1, A2, A3 and stack
640 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
641 // an argument. Otherwise, passed in A1, A2, A3 and stack.
642 // f64 - Only passed in two aliased f32 registers if no int reg has been used
643 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
644 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
646 //===----------------------------------------------------------------------===//
648 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
649 MVT LocVT, CCValAssign::LocInfo LocInfo,
650 ISD::ArgFlagsTy ArgFlags, CCState &State) {
652 static const unsigned IntRegsSize=4, FloatRegsSize=2;
654 static const unsigned IntRegs[] = {
655 Mips::A0, Mips::A1, Mips::A2, Mips::A3
657 static const unsigned F32Regs[] = {
660 static const unsigned F64Regs[] = {
665 unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
666 bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0)));
668 // Promote i8 and i16
669 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
671 if (ArgFlags.isSExt())
672 LocInfo = CCValAssign::SExt;
673 else if (ArgFlags.isZExt())
674 LocInfo = CCValAssign::ZExt;
676 LocInfo = CCValAssign::AExt;
679 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) {
680 Reg = State.AllocateReg(IntRegs, IntRegsSize);
685 if (ValVT.isFloatingPoint() && !IntRegUsed) {
686 if (ValVT == MVT::f32)
687 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
689 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
692 if (ValVT == MVT::f64 && IntRegUsed) {
693 if (UnallocIntReg != IntRegsSize) {
694 // If we hit register A3 as the first not allocated, we must
695 // mark it as allocated (shadow) and use the stack instead.
696 if (IntRegs[UnallocIntReg] != (unsigned (Mips::A3)))
698 for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg)
699 State.AllocateReg(UnallocIntReg);
705 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
706 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
707 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
709 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
711 return false; // CC must always match
714 //===----------------------------------------------------------------------===//
715 // CALL Calling Convention Implementation
716 //===----------------------------------------------------------------------===//
718 /// LowerCALL - functions arguments are copied from virtual regs to
719 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
720 /// TODO: isVarArg, isTailCall.
721 SDValue MipsTargetLowering::
722 LowerCALL(SDValue Op, SelectionDAG &DAG)
724 MachineFunction &MF = DAG.getMachineFunction();
726 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
727 SDValue Chain = TheCall->getChain();
728 SDValue Callee = TheCall->getCallee();
729 bool isVarArg = TheCall->isVarArg();
730 unsigned CC = TheCall->getCallingConv();
731 DebugLoc dl = TheCall->getDebugLoc();
733 MachineFrameInfo *MFI = MF.getFrameInfo();
735 // Analyze operands of the call, assigning locations to each operand.
736 SmallVector<CCValAssign, 16> ArgLocs;
737 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
739 // To meet O32 ABI, Mips must always allocate 16 bytes on
740 // the stack (even if less than 4 are used as arguments)
741 if (Subtarget->isABI_O32()) {
742 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
743 MFI->CreateFixedObject(VTsize, (VTsize*3));
744 CCInfo.AnalyzeCallOperands(TheCall, CC_MipsO32);
746 CCInfo.AnalyzeCallOperands(TheCall, CC_Mips);
748 // Get a count of how many bytes are to be pushed on the stack.
749 unsigned NumBytes = CCInfo.getNextStackOffset();
750 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
752 // With EABI is it possible to have 16 args on registers.
753 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
754 SmallVector<SDValue, 8> MemOpChains;
756 // First/LastArgStackLoc contains the first/last
757 // "at stack" argument location.
758 int LastArgStackLoc = 0;
759 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
761 // Walk the register/memloc assignments, inserting copies/loads.
762 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
763 SDValue Arg = TheCall->getArg(i);
764 CCValAssign &VA = ArgLocs[i];
766 // Promote the value if needed.
767 switch (VA.getLocInfo()) {
768 default: llvm_unreachable("Unknown loc info!");
769 case CCValAssign::Full:
770 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
771 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
772 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg);
773 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
774 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
775 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
776 DAG.getConstant(0, getPointerTy()));
777 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
778 DAG.getConstant(1, getPointerTy()));
779 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
780 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
785 case CCValAssign::SExt:
786 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
788 case CCValAssign::ZExt:
789 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
791 case CCValAssign::AExt:
792 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
796 // Arguments that can be passed on register must be kept at
799 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
803 // Register can't get to this point...
804 assert(VA.isMemLoc());
806 // Create the frame index object for this incoming parameter
807 // This guarantees that when allocating Local Area the firsts
808 // 16 bytes which are alwayes reserved won't be overwritten
809 // if O32 ABI is used. For EABI the first address is zero.
810 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
811 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
814 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
816 // emit ISD::STORE whichs stores the
817 // parameter value to a stack Location
818 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
821 // Transform all store nodes into one single node because all store
822 // nodes are independent of each other.
823 if (!MemOpChains.empty())
824 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
825 &MemOpChains[0], MemOpChains.size());
827 // Build a sequence of copy-to-reg nodes chained together with token
828 // chain and flag operands which copy the outgoing args into registers.
829 // The InFlag in necessary since all emited instructions must be
832 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
833 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
834 RegsToPass[i].second, InFlag);
835 InFlag = Chain.getValue(1);
838 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
839 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
840 // node so that legalize doesn't hack it.
841 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
842 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
843 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
844 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
846 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
847 // = Chain, Callee, Reg#1, Reg#2, ...
849 // Returns a chain & a flag for retval copy to use.
850 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
851 SmallVector<SDValue, 8> Ops;
852 Ops.push_back(Chain);
853 Ops.push_back(Callee);
855 // Add argument registers to the end of the list so that they are
856 // known live into the call.
857 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
858 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
859 RegsToPass[i].second.getValueType()));
861 if (InFlag.getNode())
862 Ops.push_back(InFlag);
864 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
865 InFlag = Chain.getValue(1);
867 // Create the CALLSEQ_END node.
868 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
869 DAG.getIntPtrConstant(0, true), InFlag);
870 InFlag = Chain.getValue(1);
872 // Create a stack location to hold GP when PIC is used. This stack
873 // location is used on function prologue to save GP and also after all
874 // emited CALL's to restore GP.
875 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
876 // Function can have an arbitrary number of calls, so
877 // hold the LastArgStackLoc with the biggest offset.
879 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
880 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
881 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
882 // Create the frame index only once. SPOffset here can be anything
883 // (this will be fixed on processFunctionBeforeFrameFinalized)
884 if (MipsFI->getGPStackOffset() == -1) {
885 FI = MFI->CreateFixedObject(4, 0);
888 MipsFI->setGPStackOffset(LastArgStackLoc);
892 FI = MipsFI->getGPFI();
893 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
894 SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0);
895 Chain = GPLoad.getValue(1);
896 Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
897 GPLoad, SDValue(0,0));
898 InFlag = Chain.getValue(1);
901 // Handle result values, copying them out of physregs into vregs that we
903 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG), Op.getResNo());
906 /// LowerCallResult - Lower the result values of an ISD::CALL into the
907 /// appropriate copies out of appropriate physical registers. This assumes that
908 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
909 /// being lowered. Returns a SDNode with the same number of values as the
911 SDNode *MipsTargetLowering::
912 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
913 unsigned CallingConv, SelectionDAG &DAG) {
915 bool isVarArg = TheCall->isVarArg();
916 DebugLoc dl = TheCall->getDebugLoc();
918 // Assign locations to each value returned by this call.
919 SmallVector<CCValAssign, 16> RVLocs;
920 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(),
921 RVLocs, DAG.getContext());
923 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
924 SmallVector<SDValue, 8> ResultVals;
926 // Copy all of the result registers out of their specified physreg.
927 for (unsigned i = 0; i != RVLocs.size(); ++i) {
928 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
929 RVLocs[i].getValVT(), InFlag).getValue(1);
930 InFlag = Chain.getValue(2);
931 ResultVals.push_back(Chain.getValue(0));
934 ResultVals.push_back(Chain);
936 // Merge everything together with a MERGE_VALUES node.
937 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
938 &ResultVals[0], ResultVals.size()).getNode();
941 //===----------------------------------------------------------------------===//
942 // FORMAL_ARGUMENTS Calling Convention Implementation
943 //===----------------------------------------------------------------------===//
945 /// LowerFORMAL_ARGUMENTS - transform physical registers into
946 /// virtual registers and generate load operations for
947 /// arguments places on the stack.
949 SDValue MipsTargetLowering::
950 LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
952 SDValue Root = Op.getOperand(0);
953 MachineFunction &MF = DAG.getMachineFunction();
954 MachineFrameInfo *MFI = MF.getFrameInfo();
955 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
956 DebugLoc dl = Op.getDebugLoc();
958 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
959 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
961 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
963 // Assign locations to all of the incoming arguments.
964 SmallVector<CCValAssign, 16> ArgLocs;
965 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
967 if (Subtarget->isABI_O32())
968 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MipsO32);
970 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_Mips);
972 SmallVector<SDValue, 16> ArgValues;
975 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
977 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
978 CCValAssign &VA = ArgLocs[i];
980 // Arguments stored on registers
982 MVT RegVT = VA.getLocVT();
983 TargetRegisterClass *RC = 0;
985 if (RegVT == MVT::i32)
986 RC = Mips::CPURegsRegisterClass;
987 else if (RegVT == MVT::f32)
988 RC = Mips::FGR32RegisterClass;
989 else if (RegVT == MVT::f64) {
990 if (!Subtarget->isSingleFloat())
991 RC = Mips::AFGR64RegisterClass;
993 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
995 // Transform the arguments stored on
996 // physical registers into virtual ones
997 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
998 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
1000 // If this is an 8 or 16-bit value, it has been passed promoted
1001 // to 32 bits. Insert an assert[sz]ext to capture this, then
1002 // truncate to the right size.
1003 if (VA.getLocInfo() != CCValAssign::Full) {
1004 unsigned Opcode = 0;
1005 if (VA.getLocInfo() == CCValAssign::SExt)
1006 Opcode = ISD::AssertSext;
1007 else if (VA.getLocInfo() == CCValAssign::ZExt)
1008 Opcode = ISD::AssertZext;
1010 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
1011 DAG.getValueType(VA.getValVT()));
1012 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1015 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
1016 if (Subtarget->isABI_O32()) {
1017 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
1018 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
1019 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
1020 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
1021 VA.getLocReg()+1, RC);
1022 SDValue ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg2, RegVT);
1023 SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
1024 SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2);
1025 ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi);
1029 ArgValues.push_back(ArgValue);
1031 // To meet ABI, when VARARGS are passed on registers, the registers
1032 // must have their values written to the caller stack frame.
1033 if ((isVarArg) && (Subtarget->isABI_O32())) {
1034 if (StackPtr.getNode() == 0)
1035 StackPtr = DAG.getRegister(StackReg, getPointerTy());
1037 // The stack pointer offset is relative to the caller stack frame.
1038 // Since the real stack size is unknown here, a negative SPOffset
1039 // is used so there's a way to adjust these offsets when the stack
1040 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1041 // used instead of a direct negative address (which is recorded to
1042 // be used on emitPrologue) to avoid mis-calc of the first stack
1043 // offset on PEI::calculateFrameObjectOffsets.
1044 // Arguments are always 32-bit.
1045 int FI = MFI->CreateFixedObject(4, 0);
1046 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
1047 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
1049 // emit ISD::STORE whichs stores the
1050 // parameter value to a stack Location
1051 ArgValues.push_back(DAG.getStore(Root, dl, ArgValue, PtrOff, NULL, 0));
1054 } else { // VA.isRegLoc()
1057 assert(VA.isMemLoc());
1059 // The stack pointer offset is relative to the caller stack frame.
1060 // Since the real stack size is unknown here, a negative SPOffset
1061 // is used so there's a way to adjust these offsets when the stack
1062 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1063 // used instead of a direct negative address (which is recorded to
1064 // be used on emitPrologue) to avoid mis-calc of the first stack
1065 // offset on PEI::calculateFrameObjectOffsets.
1066 // Arguments are always 32-bit.
1067 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1068 int FI = MFI->CreateFixedObject(ArgSize, 0);
1069 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
1070 (FirstStackArgLoc + VA.getLocMemOffset())));
1072 // Create load nodes to retrieve arguments from the stack
1073 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1074 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0));
1078 // The mips ABIs for returning structs by value requires that we copy
1079 // the sret argument into $v0 for the return. Save the argument into
1080 // a virtual register so that we can access it from the return points.
1081 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1082 unsigned Reg = MipsFI->getSRetReturnReg();
1084 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1085 MipsFI->setSRetReturnReg(Reg);
1087 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]);
1088 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root);
1091 ArgValues.push_back(Root);
1093 // Return the new list of results.
1094 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1095 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1098 //===----------------------------------------------------------------------===//
1099 // Return Value Calling Convention Implementation
1100 //===----------------------------------------------------------------------===//
1102 SDValue MipsTargetLowering::
1103 LowerRET(SDValue Op, SelectionDAG &DAG)
1105 // CCValAssign - represent the assignment of
1106 // the return value to a location
1107 SmallVector<CCValAssign, 16> RVLocs;
1108 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1109 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1110 DebugLoc dl = Op.getDebugLoc();
1112 // CCState - Info about the registers and stack slot.
1113 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs, DAG.getContext());
1115 // Analize return values of ISD::RET
1116 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Mips);
1118 // If this is the first return lowered for this function, add
1119 // the regs to the liveout set for the function.
1120 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1121 for (unsigned i = 0; i != RVLocs.size(); ++i)
1122 if (RVLocs[i].isRegLoc())
1123 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1126 // The chain is always operand #0
1127 SDValue Chain = Op.getOperand(0);
1130 // Copy the result values into the output registers.
1131 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1132 CCValAssign &VA = RVLocs[i];
1133 assert(VA.isRegLoc() && "Can only return in registers!");
1135 // ISD::RET => ret chain, (regnum1,val1), ...
1136 // So i*2+1 index only the regnums
1137 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1138 Op.getOperand(i*2+1), Flag);
1140 // guarantee that all emitted copies are
1141 // stuck together, avoiding something bad
1142 Flag = Chain.getValue(1);
1145 // The mips ABIs for returning structs by value requires that we copy
1146 // the sret argument into $v0 for the return. We saved the argument into
1147 // a virtual register in the entry block, so now we copy the value out
1149 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1150 MachineFunction &MF = DAG.getMachineFunction();
1151 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1152 unsigned Reg = MipsFI->getSRetReturnReg();
1155 llvm_unreachable("sret virtual register not created in the entry block");
1156 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1158 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1159 Flag = Chain.getValue(1);
1162 // Return on Mips is always a "jr $ra"
1164 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1165 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1167 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1168 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1171 //===----------------------------------------------------------------------===//
1172 // Mips Inline Assembly Support
1173 //===----------------------------------------------------------------------===//
1175 /// getConstraintType - Given a constraint letter, return the type of
1176 /// constraint it is for this target.
1177 MipsTargetLowering::ConstraintType MipsTargetLowering::
1178 getConstraintType(const std::string &Constraint) const
1180 // Mips specific constrainy
1181 // GCC config/mips/constraints.md
1183 // 'd' : An address register. Equivalent to r
1184 // unless generating MIPS16 code.
1185 // 'y' : Equivalent to r; retained for
1186 // backwards compatibility.
1187 // 'f' : Floating Point registers.
1188 if (Constraint.size() == 1) {
1189 switch (Constraint[0]) {
1194 return C_RegisterClass;
1198 return TargetLowering::getConstraintType(Constraint);
1201 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1202 /// return a list of registers that can be used to satisfy the constraint.
1203 /// This should only be used for C_RegisterClass constraints.
1204 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1205 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
1207 if (Constraint.size() == 1) {
1208 switch (Constraint[0]) {
1210 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1213 return std::make_pair(0U, Mips::FGR32RegisterClass);
1215 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1216 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1219 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1222 /// Given a register class constraint, like 'r', if this corresponds directly
1223 /// to an LLVM register class, return a register of 0 and the register class
1225 std::vector<unsigned> MipsTargetLowering::
1226 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1229 if (Constraint.size() != 1)
1230 return std::vector<unsigned>();
1232 switch (Constraint[0]) {
1235 // GCC Mips Constraint Letters
1238 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1239 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1240 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1244 if (VT == MVT::f32) {
1245 if (Subtarget->isSingleFloat())
1246 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1247 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1248 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1249 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1250 Mips::F30, Mips::F31, 0);
1252 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1253 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1254 Mips::F28, Mips::F30, 0);
1258 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1259 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1260 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1261 Mips::D14, Mips::D15, 0);
1263 return std::vector<unsigned>();
1267 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1268 // The Mips target isn't yet aware of offsets.