1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-lower"
15 #include "MipsISelLowering.h"
16 #include "InstPrinter/MipsInstPrinter.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "MipsTargetObjectFile.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/CodeGen/ValueTypes.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/GlobalVariable.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
40 STATISTIC(NumTailCalls, "Number of tail calls");
43 LargeGOT("mxgot", cl::Hidden,
44 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
47 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
48 cl::desc("MIPS: Don't trap on integer division by zero."),
51 static const uint16_t O32IntRegs[4] = {
52 Mips::A0, Mips::A1, Mips::A2, Mips::A3
55 static const uint16_t Mips64IntRegs[8] = {
56 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
57 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
60 static const uint16_t Mips64DPRegs[8] = {
61 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
62 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
65 // If I is a shifted mask, set the size (Size) and the first bit of the
66 // mask (Pos), and return true.
67 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
68 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
69 if (!isShiftedMask_64(I))
72 Size = CountPopulation_64(I);
73 Pos = countTrailingZeros(I);
77 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
78 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
79 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
82 static SDValue getTargetNode(SDValue Op, SelectionDAG &DAG, unsigned Flag) {
83 EVT Ty = Op.getValueType();
85 if (GlobalAddressSDNode *N = dyn_cast<GlobalAddressSDNode>(Op))
86 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(Op), Ty, 0,
88 if (ExternalSymbolSDNode *N = dyn_cast<ExternalSymbolSDNode>(Op))
89 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
90 if (BlockAddressSDNode *N = dyn_cast<BlockAddressSDNode>(Op))
91 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
92 if (JumpTableSDNode *N = dyn_cast<JumpTableSDNode>(Op))
93 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
94 if (ConstantPoolSDNode *N = dyn_cast<ConstantPoolSDNode>(Op))
95 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
96 N->getOffset(), Flag);
98 llvm_unreachable("Unexpected node type.");
102 static SDValue getAddrNonPIC(SDValue Op, SelectionDAG &DAG) {
104 EVT Ty = Op.getValueType();
105 SDValue Hi = getTargetNode(Op, DAG, MipsII::MO_ABS_HI);
106 SDValue Lo = getTargetNode(Op, DAG, MipsII::MO_ABS_LO);
107 return DAG.getNode(ISD::ADD, DL, Ty,
108 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
109 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
112 SDValue MipsTargetLowering::getAddrLocal(SDValue Op, SelectionDAG &DAG,
113 bool HasMips64) const {
115 EVT Ty = Op.getValueType();
116 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
117 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
118 getTargetNode(Op, DAG, GOTFlag));
119 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
120 MachinePointerInfo::getGOT(), false, false, false,
122 unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
123 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, getTargetNode(Op, DAG, LoFlag));
124 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
127 SDValue MipsTargetLowering::getAddrGlobal(SDValue Op, SelectionDAG &DAG,
128 unsigned Flag) const {
130 EVT Ty = Op.getValueType();
131 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
132 getTargetNode(Op, DAG, Flag));
133 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Tgt,
134 MachinePointerInfo::getGOT(), false, false, false, 0);
137 SDValue MipsTargetLowering::getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
139 unsigned LoFlag) const {
141 EVT Ty = Op.getValueType();
142 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(Op, DAG, HiFlag));
143 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
144 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
145 getTargetNode(Op, DAG, LoFlag));
146 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Wrapper,
147 MachinePointerInfo::getGOT(), false, false, false, 0);
150 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
152 case MipsISD::JmpLink: return "MipsISD::JmpLink";
153 case MipsISD::TailCall: return "MipsISD::TailCall";
154 case MipsISD::Hi: return "MipsISD::Hi";
155 case MipsISD::Lo: return "MipsISD::Lo";
156 case MipsISD::GPRel: return "MipsISD::GPRel";
157 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
158 case MipsISD::Ret: return "MipsISD::Ret";
159 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
160 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
161 case MipsISD::FPCmp: return "MipsISD::FPCmp";
162 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
163 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
164 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
165 case MipsISD::ExtractLOHI: return "MipsISD::ExtractLOHI";
166 case MipsISD::InsertLOHI: return "MipsISD::InsertLOHI";
167 case MipsISD::Mult: return "MipsISD::Mult";
168 case MipsISD::Multu: return "MipsISD::Multu";
169 case MipsISD::MAdd: return "MipsISD::MAdd";
170 case MipsISD::MAddu: return "MipsISD::MAddu";
171 case MipsISD::MSub: return "MipsISD::MSub";
172 case MipsISD::MSubu: return "MipsISD::MSubu";
173 case MipsISD::DivRem: return "MipsISD::DivRem";
174 case MipsISD::DivRemU: return "MipsISD::DivRemU";
175 case MipsISD::DivRem16: return "MipsISD::DivRem16";
176 case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
177 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
178 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
179 case MipsISD::Wrapper: return "MipsISD::Wrapper";
180 case MipsISD::Sync: return "MipsISD::Sync";
181 case MipsISD::Ext: return "MipsISD::Ext";
182 case MipsISD::Ins: return "MipsISD::Ins";
183 case MipsISD::LWL: return "MipsISD::LWL";
184 case MipsISD::LWR: return "MipsISD::LWR";
185 case MipsISD::SWL: return "MipsISD::SWL";
186 case MipsISD::SWR: return "MipsISD::SWR";
187 case MipsISD::LDL: return "MipsISD::LDL";
188 case MipsISD::LDR: return "MipsISD::LDR";
189 case MipsISD::SDL: return "MipsISD::SDL";
190 case MipsISD::SDR: return "MipsISD::SDR";
191 case MipsISD::EXTP: return "MipsISD::EXTP";
192 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
193 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
194 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
195 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
196 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
197 case MipsISD::SHILO: return "MipsISD::SHILO";
198 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
199 case MipsISD::MULT: return "MipsISD::MULT";
200 case MipsISD::MULTU: return "MipsISD::MULTU";
201 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
202 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
203 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
204 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
205 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
206 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
207 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
208 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
209 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
210 default: return NULL;
215 MipsTargetLowering(MipsTargetMachine &TM)
216 : TargetLowering(TM, new MipsTargetObjectFile()),
217 Subtarget(&TM.getSubtarget<MipsSubtarget>()),
218 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
219 IsO32(Subtarget->isABI_O32()) {
220 // Mips does not have i1 type, so use i32 for
221 // setcc operations results (slt, sgt, ...).
222 setBooleanContents(ZeroOrOneBooleanContent);
223 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
225 // Load extented operations for i1 types must be promoted
226 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
227 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
228 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
230 // MIPS doesn't have extending float->double load/store
231 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
232 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
234 // Used by legalize types to correctly generate the setcc result.
235 // Without this, every float setcc comes with a AND/OR with the result,
236 // we don't want this, since the fpcmp result goes to a flag register,
237 // which is used implicitly by brcond and select operations.
238 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
240 // Mips Custom Operations
241 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
242 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
243 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
244 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
245 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
246 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
247 setOperationAction(ISD::SELECT, MVT::f32, Custom);
248 setOperationAction(ISD::SELECT, MVT::f64, Custom);
249 setOperationAction(ISD::SELECT, MVT::i32, Custom);
250 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
251 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
252 setOperationAction(ISD::SETCC, MVT::f32, Custom);
253 setOperationAction(ISD::SETCC, MVT::f64, Custom);
254 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
255 setOperationAction(ISD::VASTART, MVT::Other, Custom);
256 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
257 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
258 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
260 if (!TM.Options.NoNaNsFPMath) {
261 setOperationAction(ISD::FABS, MVT::f32, Custom);
262 setOperationAction(ISD::FABS, MVT::f64, Custom);
266 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
267 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
268 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
269 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
270 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
271 setOperationAction(ISD::SELECT, MVT::i64, Custom);
272 setOperationAction(ISD::LOAD, MVT::i64, Custom);
273 setOperationAction(ISD::STORE, MVT::i64, Custom);
274 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
278 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
279 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
280 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
283 setOperationAction(ISD::ADD, MVT::i32, Custom);
285 setOperationAction(ISD::ADD, MVT::i64, Custom);
287 setOperationAction(ISD::SDIV, MVT::i32, Expand);
288 setOperationAction(ISD::SREM, MVT::i32, Expand);
289 setOperationAction(ISD::UDIV, MVT::i32, Expand);
290 setOperationAction(ISD::UREM, MVT::i32, Expand);
291 setOperationAction(ISD::SDIV, MVT::i64, Expand);
292 setOperationAction(ISD::SREM, MVT::i64, Expand);
293 setOperationAction(ISD::UDIV, MVT::i64, Expand);
294 setOperationAction(ISD::UREM, MVT::i64, Expand);
296 // Operations not directly supported by Mips.
297 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
298 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
299 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
300 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
301 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
302 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
303 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
304 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
305 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
307 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
308 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
309 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
310 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
311 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
312 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
313 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
314 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
315 setOperationAction(ISD::ROTL, MVT::i32, Expand);
316 setOperationAction(ISD::ROTL, MVT::i64, Expand);
317 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
318 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
320 if (!Subtarget->hasMips32r2())
321 setOperationAction(ISD::ROTR, MVT::i32, Expand);
323 if (!Subtarget->hasMips64r2())
324 setOperationAction(ISD::ROTR, MVT::i64, Expand);
326 setOperationAction(ISD::FSIN, MVT::f32, Expand);
327 setOperationAction(ISD::FSIN, MVT::f64, Expand);
328 setOperationAction(ISD::FCOS, MVT::f32, Expand);
329 setOperationAction(ISD::FCOS, MVT::f64, Expand);
330 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
331 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
332 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
333 setOperationAction(ISD::FPOW, MVT::f32, Expand);
334 setOperationAction(ISD::FPOW, MVT::f64, Expand);
335 setOperationAction(ISD::FLOG, MVT::f32, Expand);
336 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
337 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
338 setOperationAction(ISD::FEXP, MVT::f32, Expand);
339 setOperationAction(ISD::FMA, MVT::f32, Expand);
340 setOperationAction(ISD::FMA, MVT::f64, Expand);
341 setOperationAction(ISD::FREM, MVT::f32, Expand);
342 setOperationAction(ISD::FREM, MVT::f64, Expand);
344 if (!TM.Options.NoNaNsFPMath) {
345 setOperationAction(ISD::FNEG, MVT::f32, Expand);
346 setOperationAction(ISD::FNEG, MVT::f64, Expand);
349 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
350 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
351 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
352 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
354 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
356 setOperationAction(ISD::VAARG, MVT::Other, Expand);
357 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
358 setOperationAction(ISD::VAEND, MVT::Other, Expand);
360 // Use the default for now
361 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
362 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
364 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
365 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
366 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
367 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
369 setInsertFencesForAtomic(true);
371 if (!Subtarget->hasSEInReg()) {
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
376 if (!Subtarget->hasBitCount()) {
377 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
378 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
381 if (!Subtarget->hasSwap()) {
382 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
383 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
387 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
388 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
389 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
390 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
393 setTargetDAGCombine(ISD::SDIVREM);
394 setTargetDAGCombine(ISD::UDIVREM);
395 setTargetDAGCombine(ISD::SELECT);
396 setTargetDAGCombine(ISD::AND);
397 setTargetDAGCombine(ISD::OR);
398 setTargetDAGCombine(ISD::ADD);
400 setMinFunctionAlignment(HasMips64 ? 3 : 2);
402 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
404 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
405 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
407 MaxStoresPerMemcpy = 16;
410 const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) {
411 if (TM.getSubtargetImpl()->inMips16Mode())
412 return llvm::createMips16TargetLowering(TM);
414 return llvm::createMipsSETargetLowering(TM);
417 EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
420 return VT.changeVectorElementTypeToInteger();
423 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
424 TargetLowering::DAGCombinerInfo &DCI,
425 const MipsSubtarget *Subtarget) {
426 if (DCI.isBeforeLegalizeOps())
429 EVT Ty = N->getValueType(0);
430 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
431 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
432 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
436 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
437 N->getOperand(0), N->getOperand(1));
438 SDValue InChain = DAG.getEntryNode();
439 SDValue InGlue = DivRem;
442 if (N->hasAnyUseOfValue(0)) {
443 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
445 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
446 InChain = CopyFromLo.getValue(1);
447 InGlue = CopyFromLo.getValue(2);
451 if (N->hasAnyUseOfValue(1)) {
452 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
454 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
460 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
462 default: llvm_unreachable("Unknown fp condition code!");
464 case ISD::SETOEQ: return Mips::FCOND_OEQ;
465 case ISD::SETUNE: return Mips::FCOND_UNE;
467 case ISD::SETOLT: return Mips::FCOND_OLT;
469 case ISD::SETOGT: return Mips::FCOND_OGT;
471 case ISD::SETOLE: return Mips::FCOND_OLE;
473 case ISD::SETOGE: return Mips::FCOND_OGE;
474 case ISD::SETULT: return Mips::FCOND_ULT;
475 case ISD::SETULE: return Mips::FCOND_ULE;
476 case ISD::SETUGT: return Mips::FCOND_UGT;
477 case ISD::SETUGE: return Mips::FCOND_UGE;
478 case ISD::SETUO: return Mips::FCOND_UN;
479 case ISD::SETO: return Mips::FCOND_OR;
481 case ISD::SETONE: return Mips::FCOND_ONE;
482 case ISD::SETUEQ: return Mips::FCOND_UEQ;
487 /// This function returns true if the floating point conditional branches and
488 /// conditional moves which use condition code CC should be inverted.
489 static bool invertFPCondCodeUser(Mips::CondCode CC) {
490 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
493 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
494 "Illegal Condition Code");
499 // Creates and returns an FPCmp node from a setcc node.
500 // Returns Op if setcc is not a floating point comparison.
501 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
502 // must be a SETCC node
503 if (Op.getOpcode() != ISD::SETCC)
506 SDValue LHS = Op.getOperand(0);
508 if (!LHS.getValueType().isFloatingPoint())
511 SDValue RHS = Op.getOperand(1);
514 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
515 // node if necessary.
516 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
518 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
519 DAG.getConstant(condCodeToFCC(CC), MVT::i32));
522 // Creates and returns a CMovFPT/F node.
523 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
524 SDValue False, SDLoc DL) {
525 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
526 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
528 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
529 True.getValueType(), True, False, Cond);
532 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
533 TargetLowering::DAGCombinerInfo &DCI,
534 const MipsSubtarget *Subtarget) {
535 if (DCI.isBeforeLegalizeOps())
538 SDValue SetCC = N->getOperand(0);
540 if ((SetCC.getOpcode() != ISD::SETCC) ||
541 !SetCC.getOperand(0).getValueType().isInteger())
544 SDValue False = N->getOperand(2);
545 EVT FalseTy = False.getValueType();
547 if (!FalseTy.isInteger())
550 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
552 if (!CN || CN->getZExtValue())
556 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
557 SDValue True = N->getOperand(1);
559 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
560 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
562 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
565 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
566 TargetLowering::DAGCombinerInfo &DCI,
567 const MipsSubtarget *Subtarget) {
568 // Pattern match EXT.
569 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
570 // => ext $dst, $src, size, pos
571 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
574 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
575 unsigned ShiftRightOpc = ShiftRight.getOpcode();
577 // Op's first operand must be a shift right.
578 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
581 // The second operand of the shift must be an immediate.
583 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
586 uint64_t Pos = CN->getZExtValue();
587 uint64_t SMPos, SMSize;
589 // Op's second operand must be a shifted mask.
590 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
591 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
594 // Return if the shifted mask does not start at bit 0 or the sum of its size
595 // and Pos exceeds the word's size.
596 EVT ValTy = N->getValueType(0);
597 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
600 return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy,
601 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
602 DAG.getConstant(SMSize, MVT::i32));
605 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
606 TargetLowering::DAGCombinerInfo &DCI,
607 const MipsSubtarget *Subtarget) {
608 // Pattern match INS.
609 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
610 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
611 // => ins $dst, $src, size, pos, $src1
612 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
615 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
616 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
619 // See if Op's first operand matches (and $src1 , mask0).
620 if (And0.getOpcode() != ISD::AND)
623 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
624 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
627 // See if Op's second operand matches (and (shl $src, pos), mask1).
628 if (And1.getOpcode() != ISD::AND)
631 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
632 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
635 // The shift masks must have the same position and size.
636 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
639 SDValue Shl = And1.getOperand(0);
640 if (Shl.getOpcode() != ISD::SHL)
643 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
646 unsigned Shamt = CN->getZExtValue();
648 // Return if the shift amount and the first bit position of mask are not the
650 EVT ValTy = N->getValueType(0);
651 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
654 return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0),
655 DAG.getConstant(SMPos0, MVT::i32),
656 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
659 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
660 TargetLowering::DAGCombinerInfo &DCI,
661 const MipsSubtarget *Subtarget) {
662 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
664 if (DCI.isBeforeLegalizeOps())
667 SDValue Add = N->getOperand(1);
669 if (Add.getOpcode() != ISD::ADD)
672 SDValue Lo = Add.getOperand(1);
674 if ((Lo.getOpcode() != MipsISD::Lo) ||
675 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
678 EVT ValTy = N->getValueType(0);
681 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
683 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
686 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
688 SelectionDAG &DAG = DCI.DAG;
689 unsigned Opc = N->getOpcode();
695 return performDivRemCombine(N, DAG, DCI, Subtarget);
697 return performSELECTCombine(N, DAG, DCI, Subtarget);
699 return performANDCombine(N, DAG, DCI, Subtarget);
701 return performORCombine(N, DAG, DCI, Subtarget);
703 return performADDCombine(N, DAG, DCI, Subtarget);
710 MipsTargetLowering::LowerOperationWrapper(SDNode *N,
711 SmallVectorImpl<SDValue> &Results,
712 SelectionDAG &DAG) const {
713 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
715 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
716 Results.push_back(Res.getValue(I));
720 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
721 SmallVectorImpl<SDValue> &Results,
722 SelectionDAG &DAG) const {
723 return LowerOperationWrapper(N, Results, DAG);
726 SDValue MipsTargetLowering::
727 LowerOperation(SDValue Op, SelectionDAG &DAG) const
729 switch (Op.getOpcode())
731 case ISD::BR_JT: return lowerBR_JT(Op, DAG);
732 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
733 case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
734 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
735 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
736 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
737 case ISD::JumpTable: return lowerJumpTable(Op, DAG);
738 case ISD::SELECT: return lowerSELECT(Op, DAG);
739 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG);
740 case ISD::SETCC: return lowerSETCC(Op, DAG);
741 case ISD::VASTART: return lowerVASTART(Op, DAG);
742 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
743 case ISD::FABS: return lowerFABS(Op, DAG);
744 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
745 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
746 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
747 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
748 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
749 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
750 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
751 case ISD::LOAD: return lowerLOAD(Op, DAG);
752 case ISD::STORE: return lowerSTORE(Op, DAG);
753 case ISD::ADD: return lowerADD(Op, DAG);
754 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
759 //===----------------------------------------------------------------------===//
760 // Lower helper functions
761 //===----------------------------------------------------------------------===//
763 // addLiveIn - This helper function adds the specified physical register to the
764 // MachineFunction as a live in value. It also creates a corresponding
765 // virtual register for it.
767 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
769 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
770 MF.getRegInfo().addLiveIn(PReg, VReg);
774 static MachineBasicBlock *expandPseudoDIV(MachineInstr *MI,
775 MachineBasicBlock &MBB,
776 const TargetInstrInfo &TII,
781 // Insert instruction "teq $divisor_reg, $zero, 7".
782 MachineBasicBlock::iterator I(MI);
783 MachineInstrBuilder MIB;
784 MIB = BuildMI(MBB, llvm::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
785 .addOperand(MI->getOperand(2)).addReg(Mips::ZERO).addImm(7);
787 // Use the 32-bit sub-register if this is a 64-bit division.
789 MIB->getOperand(0).setSubReg(Mips::sub_32);
795 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
796 MachineBasicBlock *BB) const {
797 switch (MI->getOpcode()) {
799 llvm_unreachable("Unexpected instr type to insert");
800 case Mips::ATOMIC_LOAD_ADD_I8:
801 case Mips::ATOMIC_LOAD_ADD_I8_P8:
802 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
803 case Mips::ATOMIC_LOAD_ADD_I16:
804 case Mips::ATOMIC_LOAD_ADD_I16_P8:
805 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
806 case Mips::ATOMIC_LOAD_ADD_I32:
807 case Mips::ATOMIC_LOAD_ADD_I32_P8:
808 return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
809 case Mips::ATOMIC_LOAD_ADD_I64:
810 case Mips::ATOMIC_LOAD_ADD_I64_P8:
811 return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
813 case Mips::ATOMIC_LOAD_AND_I8:
814 case Mips::ATOMIC_LOAD_AND_I8_P8:
815 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
816 case Mips::ATOMIC_LOAD_AND_I16:
817 case Mips::ATOMIC_LOAD_AND_I16_P8:
818 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
819 case Mips::ATOMIC_LOAD_AND_I32:
820 case Mips::ATOMIC_LOAD_AND_I32_P8:
821 return emitAtomicBinary(MI, BB, 4, Mips::AND);
822 case Mips::ATOMIC_LOAD_AND_I64:
823 case Mips::ATOMIC_LOAD_AND_I64_P8:
824 return emitAtomicBinary(MI, BB, 8, Mips::AND64);
826 case Mips::ATOMIC_LOAD_OR_I8:
827 case Mips::ATOMIC_LOAD_OR_I8_P8:
828 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
829 case Mips::ATOMIC_LOAD_OR_I16:
830 case Mips::ATOMIC_LOAD_OR_I16_P8:
831 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
832 case Mips::ATOMIC_LOAD_OR_I32:
833 case Mips::ATOMIC_LOAD_OR_I32_P8:
834 return emitAtomicBinary(MI, BB, 4, Mips::OR);
835 case Mips::ATOMIC_LOAD_OR_I64:
836 case Mips::ATOMIC_LOAD_OR_I64_P8:
837 return emitAtomicBinary(MI, BB, 8, Mips::OR64);
839 case Mips::ATOMIC_LOAD_XOR_I8:
840 case Mips::ATOMIC_LOAD_XOR_I8_P8:
841 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
842 case Mips::ATOMIC_LOAD_XOR_I16:
843 case Mips::ATOMIC_LOAD_XOR_I16_P8:
844 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
845 case Mips::ATOMIC_LOAD_XOR_I32:
846 case Mips::ATOMIC_LOAD_XOR_I32_P8:
847 return emitAtomicBinary(MI, BB, 4, Mips::XOR);
848 case Mips::ATOMIC_LOAD_XOR_I64:
849 case Mips::ATOMIC_LOAD_XOR_I64_P8:
850 return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
852 case Mips::ATOMIC_LOAD_NAND_I8:
853 case Mips::ATOMIC_LOAD_NAND_I8_P8:
854 return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
855 case Mips::ATOMIC_LOAD_NAND_I16:
856 case Mips::ATOMIC_LOAD_NAND_I16_P8:
857 return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
858 case Mips::ATOMIC_LOAD_NAND_I32:
859 case Mips::ATOMIC_LOAD_NAND_I32_P8:
860 return emitAtomicBinary(MI, BB, 4, 0, true);
861 case Mips::ATOMIC_LOAD_NAND_I64:
862 case Mips::ATOMIC_LOAD_NAND_I64_P8:
863 return emitAtomicBinary(MI, BB, 8, 0, true);
865 case Mips::ATOMIC_LOAD_SUB_I8:
866 case Mips::ATOMIC_LOAD_SUB_I8_P8:
867 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
868 case Mips::ATOMIC_LOAD_SUB_I16:
869 case Mips::ATOMIC_LOAD_SUB_I16_P8:
870 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
871 case Mips::ATOMIC_LOAD_SUB_I32:
872 case Mips::ATOMIC_LOAD_SUB_I32_P8:
873 return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
874 case Mips::ATOMIC_LOAD_SUB_I64:
875 case Mips::ATOMIC_LOAD_SUB_I64_P8:
876 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
878 case Mips::ATOMIC_SWAP_I8:
879 case Mips::ATOMIC_SWAP_I8_P8:
880 return emitAtomicBinaryPartword(MI, BB, 1, 0);
881 case Mips::ATOMIC_SWAP_I16:
882 case Mips::ATOMIC_SWAP_I16_P8:
883 return emitAtomicBinaryPartword(MI, BB, 2, 0);
884 case Mips::ATOMIC_SWAP_I32:
885 case Mips::ATOMIC_SWAP_I32_P8:
886 return emitAtomicBinary(MI, BB, 4, 0);
887 case Mips::ATOMIC_SWAP_I64:
888 case Mips::ATOMIC_SWAP_I64_P8:
889 return emitAtomicBinary(MI, BB, 8, 0);
891 case Mips::ATOMIC_CMP_SWAP_I8:
892 case Mips::ATOMIC_CMP_SWAP_I8_P8:
893 return emitAtomicCmpSwapPartword(MI, BB, 1);
894 case Mips::ATOMIC_CMP_SWAP_I16:
895 case Mips::ATOMIC_CMP_SWAP_I16_P8:
896 return emitAtomicCmpSwapPartword(MI, BB, 2);
897 case Mips::ATOMIC_CMP_SWAP_I32:
898 case Mips::ATOMIC_CMP_SWAP_I32_P8:
899 return emitAtomicCmpSwap(MI, BB, 4);
900 case Mips::ATOMIC_CMP_SWAP_I64:
901 case Mips::ATOMIC_CMP_SWAP_I64_P8:
902 return emitAtomicCmpSwap(MI, BB, 8);
903 case Mips::PseudoSDIV:
904 case Mips::PseudoUDIV:
905 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), false);
906 case Mips::PseudoDSDIV:
907 case Mips::PseudoDUDIV:
908 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), true);
912 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
913 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
915 MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
916 unsigned Size, unsigned BinOpcode,
918 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
920 MachineFunction *MF = BB->getParent();
921 MachineRegisterInfo &RegInfo = MF->getRegInfo();
922 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
923 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
924 DebugLoc DL = MI->getDebugLoc();
925 unsigned LL, SC, AND, NOR, ZERO, BEQ;
928 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
929 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
936 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
937 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
940 ZERO = Mips::ZERO_64;
944 unsigned OldVal = MI->getOperand(0).getReg();
945 unsigned Ptr = MI->getOperand(1).getReg();
946 unsigned Incr = MI->getOperand(2).getReg();
948 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
949 unsigned AndRes = RegInfo.createVirtualRegister(RC);
950 unsigned Success = RegInfo.createVirtualRegister(RC);
952 // insert new blocks after the current block
953 const BasicBlock *LLVM_BB = BB->getBasicBlock();
954 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
955 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
956 MachineFunction::iterator It = BB;
958 MF->insert(It, loopMBB);
959 MF->insert(It, exitMBB);
961 // Transfer the remainder of BB and its successor edges to exitMBB.
962 exitMBB->splice(exitMBB->begin(), BB,
963 llvm::next(MachineBasicBlock::iterator(MI)),
965 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
969 // fallthrough --> loopMBB
970 BB->addSuccessor(loopMBB);
971 loopMBB->addSuccessor(loopMBB);
972 loopMBB->addSuccessor(exitMBB);
976 // <binop> storeval, oldval, incr
977 // sc success, storeval, 0(ptr)
978 // beq success, $0, loopMBB
980 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
982 // and andres, oldval, incr
983 // nor storeval, $0, andres
984 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
985 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
986 } else if (BinOpcode) {
987 // <binop> storeval, oldval, incr
988 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
992 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
993 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
995 MI->eraseFromParent(); // The instruction is gone now.
1001 MipsTargetLowering::emitAtomicBinaryPartword(MachineInstr *MI,
1002 MachineBasicBlock *BB,
1003 unsigned Size, unsigned BinOpcode,
1005 assert((Size == 1 || Size == 2) &&
1006 "Unsupported size for EmitAtomicBinaryPartial.");
1008 MachineFunction *MF = BB->getParent();
1009 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1010 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1011 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1012 DebugLoc DL = MI->getDebugLoc();
1013 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1014 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1016 unsigned Dest = MI->getOperand(0).getReg();
1017 unsigned Ptr = MI->getOperand(1).getReg();
1018 unsigned Incr = MI->getOperand(2).getReg();
1020 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1021 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1022 unsigned Mask = RegInfo.createVirtualRegister(RC);
1023 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1024 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1025 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1026 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1027 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1028 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1029 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1030 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1031 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1032 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1033 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1034 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1035 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1036 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1037 unsigned Success = RegInfo.createVirtualRegister(RC);
1039 // insert new blocks after the current block
1040 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1041 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1042 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1043 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1044 MachineFunction::iterator It = BB;
1046 MF->insert(It, loopMBB);
1047 MF->insert(It, sinkMBB);
1048 MF->insert(It, exitMBB);
1050 // Transfer the remainder of BB and its successor edges to exitMBB.
1051 exitMBB->splice(exitMBB->begin(), BB,
1052 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1053 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1055 BB->addSuccessor(loopMBB);
1056 loopMBB->addSuccessor(loopMBB);
1057 loopMBB->addSuccessor(sinkMBB);
1058 sinkMBB->addSuccessor(exitMBB);
1061 // addiu masklsb2,$0,-4 # 0xfffffffc
1062 // and alignedaddr,ptr,masklsb2
1063 // andi ptrlsb2,ptr,3
1064 // sll shiftamt,ptrlsb2,3
1065 // ori maskupper,$0,255 # 0xff
1066 // sll mask,maskupper,shiftamt
1067 // nor mask2,$0,mask
1068 // sll incr2,incr,shiftamt
1070 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1071 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1072 .addReg(Mips::ZERO).addImm(-4);
1073 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1074 .addReg(Ptr).addReg(MaskLSB2);
1075 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1076 if (Subtarget->isLittle()) {
1077 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1079 unsigned Off = RegInfo.createVirtualRegister(RC);
1080 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1081 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1082 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1084 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1085 .addReg(Mips::ZERO).addImm(MaskImm);
1086 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1087 .addReg(MaskUpper).addReg(ShiftAmt);
1088 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1089 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1091 // atomic.load.binop
1093 // ll oldval,0(alignedaddr)
1094 // binop binopres,oldval,incr2
1095 // and newval,binopres,mask
1096 // and maskedoldval0,oldval,mask2
1097 // or storeval,maskedoldval0,newval
1098 // sc success,storeval,0(alignedaddr)
1099 // beq success,$0,loopMBB
1103 // ll oldval,0(alignedaddr)
1104 // and newval,incr2,mask
1105 // and maskedoldval0,oldval,mask2
1106 // or storeval,maskedoldval0,newval
1107 // sc success,storeval,0(alignedaddr)
1108 // beq success,$0,loopMBB
1111 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1113 // and andres, oldval, incr2
1114 // nor binopres, $0, andres
1115 // and newval, binopres, mask
1116 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1117 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1118 .addReg(Mips::ZERO).addReg(AndRes);
1119 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1120 } else if (BinOpcode) {
1121 // <binop> binopres, oldval, incr2
1122 // and newval, binopres, mask
1123 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1124 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1125 } else {// atomic.swap
1126 // and newval, incr2, mask
1127 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1130 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1131 .addReg(OldVal).addReg(Mask2);
1132 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1133 .addReg(MaskedOldVal0).addReg(NewVal);
1134 BuildMI(BB, DL, TII->get(SC), Success)
1135 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1136 BuildMI(BB, DL, TII->get(Mips::BEQ))
1137 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1140 // and maskedoldval1,oldval,mask
1141 // srl srlres,maskedoldval1,shiftamt
1142 // sll sllres,srlres,24
1143 // sra dest,sllres,24
1145 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1147 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1148 .addReg(OldVal).addReg(Mask);
1149 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1150 .addReg(MaskedOldVal1).addReg(ShiftAmt);
1151 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes)
1152 .addReg(SrlRes).addImm(ShiftImm);
1153 BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
1154 .addReg(SllRes).addImm(ShiftImm);
1156 MI->eraseFromParent(); // The instruction is gone now.
1162 MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
1163 MachineBasicBlock *BB,
1164 unsigned Size) const {
1165 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1167 MachineFunction *MF = BB->getParent();
1168 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1169 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1170 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1171 DebugLoc DL = MI->getDebugLoc();
1172 unsigned LL, SC, ZERO, BNE, BEQ;
1175 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1176 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1182 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1183 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1184 ZERO = Mips::ZERO_64;
1189 unsigned Dest = MI->getOperand(0).getReg();
1190 unsigned Ptr = MI->getOperand(1).getReg();
1191 unsigned OldVal = MI->getOperand(2).getReg();
1192 unsigned NewVal = MI->getOperand(3).getReg();
1194 unsigned Success = RegInfo.createVirtualRegister(RC);
1196 // insert new blocks after the current block
1197 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1198 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1199 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1200 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1201 MachineFunction::iterator It = BB;
1203 MF->insert(It, loop1MBB);
1204 MF->insert(It, loop2MBB);
1205 MF->insert(It, exitMBB);
1207 // Transfer the remainder of BB and its successor edges to exitMBB.
1208 exitMBB->splice(exitMBB->begin(), BB,
1209 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1210 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1214 // fallthrough --> loop1MBB
1215 BB->addSuccessor(loop1MBB);
1216 loop1MBB->addSuccessor(exitMBB);
1217 loop1MBB->addSuccessor(loop2MBB);
1218 loop2MBB->addSuccessor(loop1MBB);
1219 loop2MBB->addSuccessor(exitMBB);
1223 // bne dest, oldval, exitMBB
1225 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1226 BuildMI(BB, DL, TII->get(BNE))
1227 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1230 // sc success, newval, 0(ptr)
1231 // beq success, $0, loop1MBB
1233 BuildMI(BB, DL, TII->get(SC), Success)
1234 .addReg(NewVal).addReg(Ptr).addImm(0);
1235 BuildMI(BB, DL, TII->get(BEQ))
1236 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1238 MI->eraseFromParent(); // The instruction is gone now.
1244 MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
1245 MachineBasicBlock *BB,
1246 unsigned Size) const {
1247 assert((Size == 1 || Size == 2) &&
1248 "Unsupported size for EmitAtomicCmpSwapPartial.");
1250 MachineFunction *MF = BB->getParent();
1251 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1252 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1253 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1254 DebugLoc DL = MI->getDebugLoc();
1255 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1256 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1258 unsigned Dest = MI->getOperand(0).getReg();
1259 unsigned Ptr = MI->getOperand(1).getReg();
1260 unsigned CmpVal = MI->getOperand(2).getReg();
1261 unsigned NewVal = MI->getOperand(3).getReg();
1263 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1264 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1265 unsigned Mask = RegInfo.createVirtualRegister(RC);
1266 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1267 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1268 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1269 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1270 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1271 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1272 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1273 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1274 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1275 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1276 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1277 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1278 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1279 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1280 unsigned Success = RegInfo.createVirtualRegister(RC);
1282 // insert new blocks after the current block
1283 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1284 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1285 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1286 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1287 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1288 MachineFunction::iterator It = BB;
1290 MF->insert(It, loop1MBB);
1291 MF->insert(It, loop2MBB);
1292 MF->insert(It, sinkMBB);
1293 MF->insert(It, exitMBB);
1295 // Transfer the remainder of BB and its successor edges to exitMBB.
1296 exitMBB->splice(exitMBB->begin(), BB,
1297 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1298 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1300 BB->addSuccessor(loop1MBB);
1301 loop1MBB->addSuccessor(sinkMBB);
1302 loop1MBB->addSuccessor(loop2MBB);
1303 loop2MBB->addSuccessor(loop1MBB);
1304 loop2MBB->addSuccessor(sinkMBB);
1305 sinkMBB->addSuccessor(exitMBB);
1307 // FIXME: computation of newval2 can be moved to loop2MBB.
1309 // addiu masklsb2,$0,-4 # 0xfffffffc
1310 // and alignedaddr,ptr,masklsb2
1311 // andi ptrlsb2,ptr,3
1312 // sll shiftamt,ptrlsb2,3
1313 // ori maskupper,$0,255 # 0xff
1314 // sll mask,maskupper,shiftamt
1315 // nor mask2,$0,mask
1316 // andi maskedcmpval,cmpval,255
1317 // sll shiftedcmpval,maskedcmpval,shiftamt
1318 // andi maskednewval,newval,255
1319 // sll shiftednewval,maskednewval,shiftamt
1320 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1321 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1322 .addReg(Mips::ZERO).addImm(-4);
1323 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1324 .addReg(Ptr).addReg(MaskLSB2);
1325 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1326 if (Subtarget->isLittle()) {
1327 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1329 unsigned Off = RegInfo.createVirtualRegister(RC);
1330 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1331 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1332 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1334 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1335 .addReg(Mips::ZERO).addImm(MaskImm);
1336 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1337 .addReg(MaskUpper).addReg(ShiftAmt);
1338 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1339 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1340 .addReg(CmpVal).addImm(MaskImm);
1341 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1342 .addReg(MaskedCmpVal).addReg(ShiftAmt);
1343 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1344 .addReg(NewVal).addImm(MaskImm);
1345 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1346 .addReg(MaskedNewVal).addReg(ShiftAmt);
1349 // ll oldval,0(alginedaddr)
1350 // and maskedoldval0,oldval,mask
1351 // bne maskedoldval0,shiftedcmpval,sinkMBB
1353 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1354 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1355 .addReg(OldVal).addReg(Mask);
1356 BuildMI(BB, DL, TII->get(Mips::BNE))
1357 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1360 // and maskedoldval1,oldval,mask2
1361 // or storeval,maskedoldval1,shiftednewval
1362 // sc success,storeval,0(alignedaddr)
1363 // beq success,$0,loop1MBB
1365 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1366 .addReg(OldVal).addReg(Mask2);
1367 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1368 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1369 BuildMI(BB, DL, TII->get(SC), Success)
1370 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1371 BuildMI(BB, DL, TII->get(Mips::BEQ))
1372 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1375 // srl srlres,maskedoldval0,shiftamt
1376 // sll sllres,srlres,24
1377 // sra dest,sllres,24
1379 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1381 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1382 .addReg(MaskedOldVal0).addReg(ShiftAmt);
1383 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes)
1384 .addReg(SrlRes).addImm(ShiftImm);
1385 BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
1386 .addReg(SllRes).addImm(ShiftImm);
1388 MI->eraseFromParent(); // The instruction is gone now.
1393 //===----------------------------------------------------------------------===//
1394 // Misc Lower Operation implementation
1395 //===----------------------------------------------------------------------===//
1396 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
1397 SDValue Chain = Op.getOperand(0);
1398 SDValue Table = Op.getOperand(1);
1399 SDValue Index = Op.getOperand(2);
1401 EVT PTy = getPointerTy();
1402 unsigned EntrySize =
1403 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout());
1405 Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
1406 DAG.getConstant(EntrySize, PTy));
1407 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
1409 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
1410 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
1411 MachinePointerInfo::getJumpTable(), MemVT, false, false,
1413 Chain = Addr.getValue(1);
1415 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || IsN64) {
1416 // For PIC, the sequence is:
1417 // BRIND(load(Jumptable + index) + RelocBase)
1418 // RelocBase can be JumpTable, GOT or some sort of global base.
1419 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
1420 getPICJumpTableRelocBase(Table, DAG));
1423 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
1426 SDValue MipsTargetLowering::
1427 lowerBRCOND(SDValue Op, SelectionDAG &DAG) const
1429 // The first operand is the chain, the second is the condition, the third is
1430 // the block to branch to if the condition is true.
1431 SDValue Chain = Op.getOperand(0);
1432 SDValue Dest = Op.getOperand(2);
1435 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1437 // Return if flag is not set by a floating point comparison.
1438 if (CondRes.getOpcode() != MipsISD::FPCmp)
1441 SDValue CCNode = CondRes.getOperand(2);
1443 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1444 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1445 SDValue BrCode = DAG.getConstant(Opc, MVT::i32);
1446 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1450 SDValue MipsTargetLowering::
1451 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1453 SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1455 // Return if flag is not set by a floating point comparison.
1456 if (Cond.getOpcode() != MipsISD::FPCmp)
1459 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1463 SDValue MipsTargetLowering::
1464 lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
1467 EVT Ty = Op.getOperand(0).getValueType();
1468 SDValue Cond = DAG.getNode(ISD::SETCC, DL,
1469 getSetCCResultType(*DAG.getContext(), Ty),
1470 Op.getOperand(0), Op.getOperand(1),
1473 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1477 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1478 SDValue Cond = createFPCmp(DAG, Op);
1480 assert(Cond.getOpcode() == MipsISD::FPCmp &&
1481 "Floating point operand expected.");
1483 SDValue True = DAG.getConstant(1, MVT::i32);
1484 SDValue False = DAG.getConstant(0, MVT::i32);
1486 return createCMovFP(DAG, Cond, True, False, SDLoc(Op));
1489 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
1490 SelectionDAG &DAG) const {
1491 // FIXME there isn't actually debug info here
1493 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1495 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
1496 const MipsTargetObjectFile &TLOF =
1497 (const MipsTargetObjectFile&)getObjFileLowering();
1499 // %gp_rel relocation
1500 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1501 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0,
1503 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, DL,
1504 DAG.getVTList(MVT::i32), &GA, 1);
1505 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
1506 return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode);
1509 // %hi/%lo relocation
1510 return getAddrNonPIC(Op, DAG);
1513 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
1514 return getAddrLocal(Op, DAG, HasMips64);
1517 return getAddrGlobalLargeGOT(Op, DAG, MipsII::MO_GOT_HI16,
1518 MipsII::MO_GOT_LO16);
1520 return getAddrGlobal(Op, DAG,
1521 HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16);
1524 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
1525 SelectionDAG &DAG) const {
1526 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
1527 return getAddrNonPIC(Op, DAG);
1529 return getAddrLocal(Op, DAG, HasMips64);
1532 SDValue MipsTargetLowering::
1533 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1535 // If the relocation model is PIC, use the General Dynamic TLS Model or
1536 // Local Dynamic TLS model, otherwise use the Initial Exec or
1537 // Local Exec TLS Model.
1539 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1541 const GlobalValue *GV = GA->getGlobal();
1542 EVT PtrVT = getPointerTy();
1544 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1546 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1547 // General Dynamic and Local Dynamic TLS Model.
1548 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1551 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
1552 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
1553 getGlobalReg(DAG, PtrVT), TGA);
1554 unsigned PtrSize = PtrVT.getSizeInBits();
1555 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1557 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
1561 Entry.Node = Argument;
1563 Args.push_back(Entry);
1565 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy,
1566 false, false, false, false, 0, CallingConv::C,
1567 /*IsTailCall=*/false, /*doesNotRet=*/false,
1568 /*isReturnValueUsed=*/true,
1569 TlsGetAddr, Args, DAG, DL);
1570 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1572 SDValue Ret = CallResult.first;
1574 if (model != TLSModel::LocalDynamic)
1577 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1578 MipsII::MO_DTPREL_HI);
1579 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1580 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1581 MipsII::MO_DTPREL_LO);
1582 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1583 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
1584 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
1588 if (model == TLSModel::InitialExec) {
1589 // Initial Exec TLS Model
1590 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1591 MipsII::MO_GOTTPREL);
1592 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
1594 Offset = DAG.getLoad(PtrVT, DL,
1595 DAG.getEntryNode(), TGA, MachinePointerInfo(),
1596 false, false, false, 0);
1598 // Local Exec TLS Model
1599 assert(model == TLSModel::LocalExec);
1600 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1601 MipsII::MO_TPREL_HI);
1602 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1603 MipsII::MO_TPREL_LO);
1604 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1605 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1606 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1609 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
1610 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
1613 SDValue MipsTargetLowering::
1614 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1616 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
1617 return getAddrNonPIC(Op, DAG);
1619 return getAddrLocal(Op, DAG, HasMips64);
1622 SDValue MipsTargetLowering::
1623 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1625 // gp_rel relocation
1626 // FIXME: we should reference the constant pool using small data sections,
1627 // but the asm printer currently doesn't support this feature without
1628 // hacking it. This feature should come soon so we can uncomment the
1630 //if (IsInSmallSection(C->getType())) {
1631 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1632 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1633 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
1635 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
1636 return getAddrNonPIC(Op, DAG);
1638 return getAddrLocal(Op, DAG, HasMips64);
1641 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1642 MachineFunction &MF = DAG.getMachineFunction();
1643 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1646 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1649 // vastart just stores the address of the VarArgsFrameIndex slot into the
1650 // memory location argument.
1651 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1652 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1653 MachinePointerInfo(SV), false, false, 0);
1656 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1657 EVT TyX = Op.getOperand(0).getValueType();
1658 EVT TyY = Op.getOperand(1).getValueType();
1659 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1660 SDValue Const31 = DAG.getConstant(31, MVT::i32);
1664 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1666 SDValue X = (TyX == MVT::f32) ?
1667 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1668 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1670 SDValue Y = (TyY == MVT::f32) ?
1671 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1672 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
1676 // ext E, Y, 31, 1 ; extract bit31 of Y
1677 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
1678 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1679 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1682 // srl SrlX, SllX, 1
1684 // sll SllY, SrlX, 31
1685 // or Or, SrlX, SllY
1686 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1687 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1688 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1689 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1690 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1693 if (TyX == MVT::f32)
1694 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1696 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1697 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1698 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1701 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1702 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
1703 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
1704 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
1705 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1708 // Bitcast to integer nodes.
1709 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1710 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
1713 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
1714 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
1715 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
1716 DAG.getConstant(WidthY - 1, MVT::i32), Const1);
1718 if (WidthX > WidthY)
1719 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
1720 else if (WidthY > WidthX)
1721 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
1723 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
1724 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
1725 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
1728 // (d)sll SllX, X, 1
1729 // (d)srl SrlX, SllX, 1
1730 // (d)srl SrlY, Y, width(Y)-1
1731 // (d)sll SllY, SrlX, width(Y)-1
1732 // or Or, SrlX, SllY
1733 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1734 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1735 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1736 DAG.getConstant(WidthY - 1, MVT::i32));
1738 if (WidthX > WidthY)
1739 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
1740 else if (WidthY > WidthX)
1741 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
1743 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
1744 DAG.getConstant(WidthX - 1, MVT::i32));
1745 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
1746 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
1750 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
1751 if (Subtarget->hasMips64())
1752 return lowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2());
1754 return lowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
1757 static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1758 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1761 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1763 SDValue X = (Op.getValueType() == MVT::f32) ?
1764 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1765 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1770 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
1771 DAG.getRegister(Mips::ZERO, MVT::i32),
1772 DAG.getConstant(31, MVT::i32), Const1, X);
1774 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1775 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1778 if (Op.getValueType() == MVT::f32)
1779 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
1781 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1782 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1783 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1786 static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1787 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1790 // Bitcast to integer node.
1791 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
1795 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
1796 DAG.getRegister(Mips::ZERO_64, MVT::i64),
1797 DAG.getConstant(63, MVT::i32), Const1, X);
1799 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
1800 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
1803 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
1807 MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const {
1808 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
1809 return lowerFABS64(Op, DAG, Subtarget->hasMips32r2());
1811 return lowerFABS32(Op, DAG, Subtarget->hasMips32r2());
1814 SDValue MipsTargetLowering::
1815 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1817 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1818 "Frame address can only be determined for current frame.");
1820 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1821 MFI->setFrameAddressIsTaken(true);
1822 EVT VT = Op.getValueType();
1824 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL,
1825 IsN64 ? Mips::FP_64 : Mips::FP, VT);
1829 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
1830 SelectionDAG &DAG) const {
1832 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1833 "Return address can be determined only for current frame.");
1835 MachineFunction &MF = DAG.getMachineFunction();
1836 MachineFrameInfo *MFI = MF.getFrameInfo();
1837 MVT VT = Op.getSimpleValueType();
1838 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
1839 MFI->setReturnAddressIsTaken(true);
1841 // Return RA, which contains the return address. Mark it an implicit live-in.
1842 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
1843 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
1846 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
1847 // generated from __builtin_eh_return (offset, handler)
1848 // The effect of this is to adjust the stack pointer by "offset"
1849 // and then branch to "handler".
1850 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
1852 MachineFunction &MF = DAG.getMachineFunction();
1853 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1855 MipsFI->setCallsEhReturn();
1856 SDValue Chain = Op.getOperand(0);
1857 SDValue Offset = Op.getOperand(1);
1858 SDValue Handler = Op.getOperand(2);
1860 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
1862 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
1863 // EH_RETURN nodes, so that instructions are emitted back-to-back.
1864 unsigned OffsetReg = IsN64 ? Mips::V1_64 : Mips::V1;
1865 unsigned AddrReg = IsN64 ? Mips::V0_64 : Mips::V0;
1866 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
1867 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
1868 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
1869 DAG.getRegister(OffsetReg, Ty),
1870 DAG.getRegister(AddrReg, getPointerTy()),
1874 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
1875 SelectionDAG &DAG) const {
1876 // FIXME: Need pseudo-fence for 'singlethread' fences
1877 // FIXME: Set SType for weaker fences where supported/appropriate.
1880 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
1881 DAG.getConstant(SType, MVT::i32));
1884 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
1885 SelectionDAG &DAG) const {
1887 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
1888 SDValue Shamt = Op.getOperand(2);
1891 // lo = (shl lo, shamt)
1892 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
1895 // hi = (shl lo, shamt[4:0])
1896 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
1897 DAG.getConstant(-1, MVT::i32));
1898 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
1899 DAG.getConstant(1, MVT::i32));
1900 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
1902 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
1903 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
1904 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
1905 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
1906 DAG.getConstant(0x20, MVT::i32));
1907 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
1908 DAG.getConstant(0, MVT::i32), ShiftLeftLo);
1909 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
1911 SDValue Ops[2] = {Lo, Hi};
1912 return DAG.getMergeValues(Ops, 2, DL);
1915 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
1918 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
1919 SDValue Shamt = Op.getOperand(2);
1922 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
1924 // hi = (sra hi, shamt)
1926 // hi = (srl hi, shamt)
1929 // lo = (sra hi, shamt[4:0])
1930 // hi = (sra hi, 31)
1932 // lo = (srl hi, shamt[4:0])
1934 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
1935 DAG.getConstant(-1, MVT::i32));
1936 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
1937 DAG.getConstant(1, MVT::i32));
1938 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
1939 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
1940 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
1941 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
1943 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
1944 DAG.getConstant(0x20, MVT::i32));
1945 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
1946 DAG.getConstant(31, MVT::i32));
1947 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
1948 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
1949 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
1952 SDValue Ops[2] = {Lo, Hi};
1953 return DAG.getMergeValues(Ops, 2, DL);
1956 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
1957 SDValue Chain, SDValue Src, unsigned Offset) {
1958 SDValue Ptr = LD->getBasePtr();
1959 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
1960 EVT BasePtrVT = Ptr.getValueType();
1962 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1965 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
1966 DAG.getConstant(Offset, BasePtrVT));
1968 SDValue Ops[] = { Chain, Ptr, Src };
1969 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
1970 LD->getMemOperand());
1973 // Expand an unaligned 32 or 64-bit integer load node.
1974 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1975 LoadSDNode *LD = cast<LoadSDNode>(Op);
1976 EVT MemVT = LD->getMemoryVT();
1978 // Return if load is aligned or if MemVT is neither i32 nor i64.
1979 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
1980 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
1983 bool IsLittle = Subtarget->isLittle();
1984 EVT VT = Op.getValueType();
1985 ISD::LoadExtType ExtType = LD->getExtensionType();
1986 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
1988 assert((VT == MVT::i32) || (VT == MVT::i64));
1991 // (set dst, (i64 (load baseptr)))
1993 // (set tmp, (ldl (add baseptr, 7), undef))
1994 // (set dst, (ldr baseptr, tmp))
1995 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
1996 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
1998 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2002 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2004 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2008 // (set dst, (i32 (load baseptr))) or
2009 // (set dst, (i64 (sextload baseptr))) or
2010 // (set dst, (i64 (extload baseptr)))
2012 // (set tmp, (lwl (add baseptr, 3), undef))
2013 // (set dst, (lwr baseptr, tmp))
2014 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2015 (ExtType == ISD::EXTLOAD))
2018 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2021 // (set dst, (i64 (zextload baseptr)))
2023 // (set tmp0, (lwl (add baseptr, 3), undef))
2024 // (set tmp1, (lwr baseptr, tmp0))
2025 // (set tmp2, (shl tmp1, 32))
2026 // (set dst, (srl tmp2, 32))
2028 SDValue Const32 = DAG.getConstant(32, MVT::i32);
2029 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2030 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2031 SDValue Ops[] = { SRL, LWR.getValue(1) };
2032 return DAG.getMergeValues(Ops, 2, DL);
2035 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2036 SDValue Chain, unsigned Offset) {
2037 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2038 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2040 SDVTList VTList = DAG.getVTList(MVT::Other);
2043 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2044 DAG.getConstant(Offset, BasePtrVT));
2046 SDValue Ops[] = { Chain, Value, Ptr };
2047 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2048 SD->getMemOperand());
2051 // Expand an unaligned 32 or 64-bit integer store node.
2052 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2054 SDValue Value = SD->getValue(), Chain = SD->getChain();
2055 EVT VT = Value.getValueType();
2058 // (store val, baseptr) or
2059 // (truncstore val, baseptr)
2061 // (swl val, (add baseptr, 3))
2062 // (swr val, baseptr)
2063 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2064 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2066 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2069 assert(VT == MVT::i64);
2072 // (store val, baseptr)
2074 // (sdl val, (add baseptr, 7))
2075 // (sdr val, baseptr)
2076 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2077 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2080 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2081 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
2082 SDValue Val = SD->getValue();
2084 if (Val.getOpcode() != ISD::FP_TO_SINT)
2087 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2088 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2091 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2092 SD->getPointerInfo(), SD->isVolatile(),
2093 SD->isNonTemporal(), SD->getAlignment());
2096 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2097 StoreSDNode *SD = cast<StoreSDNode>(Op);
2098 EVT MemVT = SD->getMemoryVT();
2100 // Lower unaligned integer stores.
2101 if ((SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2102 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2103 return lowerUnalignedIntStore(SD, DAG, Subtarget->isLittle());
2105 return lowerFP_TO_SINT_STORE(SD, DAG);
2108 SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
2109 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
2110 || cast<ConstantSDNode>
2111 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0
2112 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
2116 // (add (frameaddr 0), (frame_to_args_offset))
2117 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
2118 // (add FrameObject, 0)
2119 // where FrameObject is a fixed StackObject with offset 0 which points to
2120 // the old stack pointer.
2121 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2122 EVT ValTy = Op->getValueType(0);
2123 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2124 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
2125 return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr,
2126 DAG.getConstant(0, ValTy));
2129 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2130 SelectionDAG &DAG) const {
2131 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2132 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2134 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2137 //===----------------------------------------------------------------------===//
2138 // Calling Convention Implementation
2139 //===----------------------------------------------------------------------===//
2141 //===----------------------------------------------------------------------===//
2142 // TODO: Implement a generic logic using tblgen that can support this.
2143 // Mips O32 ABI rules:
2145 // i32 - Passed in A0, A1, A2, A3 and stack
2146 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2147 // an argument. Otherwise, passed in A1, A2, A3 and stack.
2148 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2149 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2150 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
2153 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2154 //===----------------------------------------------------------------------===//
2156 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
2157 MVT LocVT, CCValAssign::LocInfo LocInfo,
2158 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2160 static const unsigned IntRegsSize=4, FloatRegsSize=2;
2162 static const uint16_t IntRegs[] = {
2163 Mips::A0, Mips::A1, Mips::A2, Mips::A3
2165 static const uint16_t F32Regs[] = {
2166 Mips::F12, Mips::F14
2168 static const uint16_t F64Regs[] = {
2172 // Do not process byval args here.
2173 if (ArgFlags.isByVal())
2176 // Promote i8 and i16
2177 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2179 if (ArgFlags.isSExt())
2180 LocInfo = CCValAssign::SExt;
2181 else if (ArgFlags.isZExt())
2182 LocInfo = CCValAssign::ZExt;
2184 LocInfo = CCValAssign::AExt;
2189 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2190 // is true: function is vararg, argument is 3rd or higher, there is previous
2191 // argument which is not f32 or f64.
2192 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
2193 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
2194 unsigned OrigAlign = ArgFlags.getOrigAlign();
2195 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2197 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2198 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2199 // If this is the first part of an i64 arg,
2200 // the allocated register must be either A0 or A2.
2201 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2202 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2204 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2205 // Allocate int register and shadow next int register. If first
2206 // available register is Mips::A1 or Mips::A3, shadow it too.
2207 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2208 if (Reg == Mips::A1 || Reg == Mips::A3)
2209 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2210 State.AllocateReg(IntRegs, IntRegsSize);
2212 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2213 // we are guaranteed to find an available float register
2214 if (ValVT == MVT::f32) {
2215 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
2216 // Shadow int register
2217 State.AllocateReg(IntRegs, IntRegsSize);
2219 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
2220 // Shadow int registers
2221 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
2222 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2223 State.AllocateReg(IntRegs, IntRegsSize);
2224 State.AllocateReg(IntRegs, IntRegsSize);
2227 llvm_unreachable("Cannot handle this ValVT.");
2230 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
2232 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2234 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2239 #include "MipsGenCallingConv.inc"
2241 //===----------------------------------------------------------------------===//
2242 // Call Calling Convention Implementation
2243 //===----------------------------------------------------------------------===//
2245 static const unsigned O32IntRegsSize = 4;
2247 // Return next O32 integer argument register.
2248 static unsigned getNextIntArgReg(unsigned Reg) {
2249 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2250 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2254 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2255 SDValue Chain, SDValue Arg, SDLoc DL,
2256 bool IsTailCall, SelectionDAG &DAG) const {
2258 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
2259 DAG.getIntPtrConstant(Offset));
2260 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
2264 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2265 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2266 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2267 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2268 /*isVolatile=*/ true, false, 0);
2271 void MipsTargetLowering::
2272 getOpndList(SmallVectorImpl<SDValue> &Ops,
2273 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
2274 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2275 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
2276 // Insert node "GP copy globalreg" before call to function.
2278 // R_MIPS_CALL* operators (emitted when non-internal functions are called
2279 // in PIC mode) allow symbols to be resolved via lazy binding.
2280 // The lazy binding stub requires GP to point to the GOT.
2281 if (IsPICCall && !InternalLinkage) {
2282 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP;
2283 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
2284 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2287 // Build a sequence of copy-to-reg nodes chained together with token
2288 // chain and flag operands which copy the outgoing args into registers.
2289 // The InFlag in necessary since all emitted instructions must be
2293 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2294 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2295 RegsToPass[i].second, InFlag);
2296 InFlag = Chain.getValue(1);
2299 // Add argument registers to the end of the list so that they are
2300 // known live into the call.
2301 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2302 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2303 RegsToPass[i].second.getValueType()));
2305 // Add a register mask operand representing the call-preserved registers.
2306 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2307 const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv);
2308 assert(Mask && "Missing call preserved mask for calling convention");
2309 if (Subtarget->inMips16HardFloat()) {
2310 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2311 llvm::StringRef Sym = G->getGlobal()->getName();
2312 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2313 if (F->hasFnAttribute("__Mips16RetHelper")) {
2314 Mask = MipsRegisterInfo::getMips16RetHelperMask();
2318 Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2320 if (InFlag.getNode())
2321 Ops.push_back(InFlag);
2324 /// LowerCall - functions arguments are copied from virtual regs to
2325 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2327 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2328 SmallVectorImpl<SDValue> &InVals) const {
2329 SelectionDAG &DAG = CLI.DAG;
2331 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2332 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2333 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2334 SDValue Chain = CLI.Chain;
2335 SDValue Callee = CLI.Callee;
2336 bool &IsTailCall = CLI.IsTailCall;
2337 CallingConv::ID CallConv = CLI.CallConv;
2338 bool IsVarArg = CLI.IsVarArg;
2340 MachineFunction &MF = DAG.getMachineFunction();
2341 MachineFrameInfo *MFI = MF.getFrameInfo();
2342 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
2343 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
2345 // Analyze operands of the call, assigning locations to each operand.
2346 SmallVector<CCValAssign, 16> ArgLocs;
2347 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2348 getTargetMachine(), ArgLocs, *DAG.getContext());
2349 MipsCC::SpecialCallingConvType SpecialCallingConv =
2350 getSpecialCallingConv(Callee);
2351 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo, SpecialCallingConv);
2353 MipsCCInfo.analyzeCallOperands(Outs, IsVarArg,
2354 getTargetMachine().Options.UseSoftFloat,
2355 Callee.getNode(), CLI.Args);
2357 // Get a count of how many bytes are to be pushed on the stack.
2358 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2360 // Check if it's really possible to do a tail call.
2363 isEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset,
2364 *MF.getInfo<MipsFunctionInfo>());
2369 // Chain is the output chain of the last Load/Store or CopyToReg node.
2370 // ByValChain is the output chain of the last Memcpy node created for copying
2371 // byval arguments to the stack.
2372 unsigned StackAlignment = TFL->getStackAlignment();
2373 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
2374 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
2377 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
2379 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL,
2380 IsN64 ? Mips::SP_64 : Mips::SP,
2383 // With EABI is it possible to have 16 args on registers.
2384 std::deque< std::pair<unsigned, SDValue> > RegsToPass;
2385 SmallVector<SDValue, 8> MemOpChains;
2386 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
2388 // Walk the register/memloc assignments, inserting copies/loads.
2389 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2390 SDValue Arg = OutVals[i];
2391 CCValAssign &VA = ArgLocs[i];
2392 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2393 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2396 if (Flags.isByVal()) {
2397 assert(Flags.getByValSize() &&
2398 "ByVal args of size 0 should have been ignored by front-end.");
2399 assert(ByValArg != MipsCCInfo.byval_end());
2400 assert(!IsTailCall &&
2401 "Do not tail-call optimize if there is a byval argument.");
2402 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2403 MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle());
2408 // Promote the value if needed.
2409 switch (VA.getLocInfo()) {
2410 default: llvm_unreachable("Unknown loc info!");
2411 case CCValAssign::Full:
2412 if (VA.isRegLoc()) {
2413 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2414 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
2415 (ValVT == MVT::i64 && LocVT == MVT::f64))
2416 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2417 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2418 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2419 Arg, DAG.getConstant(0, MVT::i32));
2420 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2421 Arg, DAG.getConstant(1, MVT::i32));
2422 if (!Subtarget->isLittle())
2424 unsigned LocRegLo = VA.getLocReg();
2425 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2426 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2427 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2432 case CCValAssign::SExt:
2433 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
2435 case CCValAssign::ZExt:
2436 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
2438 case CCValAssign::AExt:
2439 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
2443 // Arguments that can be passed on register must be kept at
2444 // RegsToPass vector
2445 if (VA.isRegLoc()) {
2446 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2450 // Register can't get to this point...
2451 assert(VA.isMemLoc());
2453 // emit ISD::STORE whichs stores the
2454 // parameter value to a stack Location
2455 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
2456 Chain, Arg, DL, IsTailCall, DAG));
2459 // Transform all store nodes into one single node because all store
2460 // nodes are independent of each other.
2461 if (!MemOpChains.empty())
2462 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
2463 &MemOpChains[0], MemOpChains.size());
2465 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2466 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2467 // node so that legalize doesn't hack it.
2468 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
2469 bool GlobalOrExternal = false, InternalLinkage = false;
2472 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2474 InternalLinkage = G->getGlobal()->hasInternalLinkage();
2476 if (InternalLinkage)
2477 Callee = getAddrLocal(Callee, DAG, HasMips64);
2479 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16,
2480 MipsII::MO_CALL_LO16);
2482 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL);
2484 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0,
2485 MipsII::MO_NO_FLAG);
2486 GlobalOrExternal = true;
2488 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2489 if (!IsN64 && !IsPIC) // !N64 && static
2490 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2491 MipsII::MO_NO_FLAG);
2493 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16,
2494 MipsII::MO_CALL_LO16);
2496 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL);
2498 GlobalOrExternal = true;
2501 SmallVector<SDValue, 8> Ops(1, Chain);
2502 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2504 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
2505 CLI, Callee, Chain);
2508 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, &Ops[0], Ops.size());
2510 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, &Ops[0], Ops.size());
2511 SDValue InFlag = Chain.getValue(1);
2513 // Create the CALLSEQ_END node.
2514 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
2515 DAG.getIntPtrConstant(0, true), InFlag, DL);
2516 InFlag = Chain.getValue(1);
2518 // Handle result values, copying them out of physregs into vregs that we
2520 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg,
2521 Ins, DL, DAG, InVals, CLI.Callee.getNode(), CLI.RetTy);
2524 /// LowerCallResult - Lower the result values of a call into the
2525 /// appropriate copies out of appropriate physical registers.
2527 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2528 CallingConv::ID CallConv, bool IsVarArg,
2529 const SmallVectorImpl<ISD::InputArg> &Ins,
2530 SDLoc DL, SelectionDAG &DAG,
2531 SmallVectorImpl<SDValue> &InVals,
2532 const SDNode *CallNode,
2533 const Type *RetTy) const {
2534 // Assign locations to each value returned by this call.
2535 SmallVector<CCValAssign, 16> RVLocs;
2536 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2537 getTargetMachine(), RVLocs, *DAG.getContext());
2538 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo);
2540 MipsCCInfo.analyzeCallResult(Ins, getTargetMachine().Options.UseSoftFloat,
2543 // Copy all of the result registers out of their specified physreg.
2544 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2545 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
2546 RVLocs[i].getLocVT(), InFlag);
2547 Chain = Val.getValue(1);
2548 InFlag = Val.getValue(2);
2550 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
2551 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val);
2553 InVals.push_back(Val);
2559 //===----------------------------------------------------------------------===//
2560 // Formal Arguments Calling Convention Implementation
2561 //===----------------------------------------------------------------------===//
2562 /// LowerFormalArguments - transform physical registers into virtual registers
2563 /// and generate load operations for arguments places on the stack.
2565 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
2566 CallingConv::ID CallConv,
2568 const SmallVectorImpl<ISD::InputArg> &Ins,
2569 SDLoc DL, SelectionDAG &DAG,
2570 SmallVectorImpl<SDValue> &InVals)
2572 MachineFunction &MF = DAG.getMachineFunction();
2573 MachineFrameInfo *MFI = MF.getFrameInfo();
2574 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2576 MipsFI->setVarArgsFrameIndex(0);
2578 // Used with vargs to acumulate store chains.
2579 std::vector<SDValue> OutChains;
2581 // Assign locations to all of the incoming arguments.
2582 SmallVector<CCValAssign, 16> ArgLocs;
2583 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2584 getTargetMachine(), ArgLocs, *DAG.getContext());
2585 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo);
2586 Function::const_arg_iterator FuncArg =
2587 DAG.getMachineFunction().getFunction()->arg_begin();
2588 bool UseSoftFloat = getTargetMachine().Options.UseSoftFloat;
2590 MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg);
2591 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
2592 MipsCCInfo.hasByValArg());
2594 unsigned CurArgIdx = 0;
2595 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
2597 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2598 CCValAssign &VA = ArgLocs[i];
2599 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx);
2600 CurArgIdx = Ins[i].OrigArgIndex;
2601 EVT ValVT = VA.getValVT();
2602 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2603 bool IsRegLoc = VA.isRegLoc();
2605 if (Flags.isByVal()) {
2606 assert(Flags.getByValSize() &&
2607 "ByVal args of size 0 should have been ignored by front-end.");
2608 assert(ByValArg != MipsCCInfo.byval_end());
2609 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
2610 MipsCCInfo, *ByValArg);
2615 // Arguments stored on registers
2617 EVT RegVT = VA.getLocVT();
2618 unsigned ArgReg = VA.getLocReg();
2619 const TargetRegisterClass *RC;
2621 if (RegVT == MVT::i32)
2622 RC = Subtarget->inMips16Mode()? &Mips::CPU16RegsRegClass :
2623 &Mips::CPURegsRegClass;
2624 else if (RegVT == MVT::i64)
2625 RC = &Mips::CPU64RegsRegClass;
2626 else if (RegVT == MVT::f32)
2627 RC = &Mips::FGR32RegClass;
2628 else if (RegVT == MVT::f64)
2629 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
2631 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
2633 // Transform the arguments stored on
2634 // physical registers into virtual ones
2635 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
2636 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2638 // If this is an 8 or 16-bit value, it has been passed promoted
2639 // to 32 bits. Insert an assert[sz]ext to capture this, then
2640 // truncate to the right size.
2641 if (VA.getLocInfo() != CCValAssign::Full) {
2642 unsigned Opcode = 0;
2643 if (VA.getLocInfo() == CCValAssign::SExt)
2644 Opcode = ISD::AssertSext;
2645 else if (VA.getLocInfo() == CCValAssign::ZExt)
2646 Opcode = ISD::AssertZext;
2648 ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue,
2649 DAG.getValueType(ValVT));
2650 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue);
2653 // Handle floating point arguments passed in integer registers and
2654 // long double arguments passed in floating point registers.
2655 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
2656 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
2657 (RegVT == MVT::f64 && ValVT == MVT::i64))
2658 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
2659 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
2660 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
2661 getNextIntArgReg(ArgReg), RC);
2662 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
2663 if (!Subtarget->isLittle())
2664 std::swap(ArgValue, ArgValue2);
2665 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
2666 ArgValue, ArgValue2);
2669 InVals.push_back(ArgValue);
2670 } else { // VA.isRegLoc()
2673 assert(VA.isMemLoc());
2675 // The stack pointer offset is relative to the caller stack frame.
2676 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2677 VA.getLocMemOffset(), true);
2679 // Create load nodes to retrieve arguments from the stack
2680 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2681 InVals.push_back(DAG.getLoad(ValVT, DL, Chain, FIN,
2682 MachinePointerInfo::getFixedStack(FI),
2683 false, false, false, 0));
2687 // The mips ABIs for returning structs by value requires that we copy
2688 // the sret argument into $v0 for the return. Save the argument into
2689 // a virtual register so that we can access it from the return points.
2690 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
2691 unsigned Reg = MipsFI->getSRetReturnReg();
2693 Reg = MF.getRegInfo().
2694 createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32));
2695 MipsFI->setSRetReturnReg(Reg);
2697 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
2698 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
2702 writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG);
2704 // All stores are grouped in one node to allow the matching between
2705 // the size of Ins and InVals. This only happens when on varg functions
2706 if (!OutChains.empty()) {
2707 OutChains.push_back(Chain);
2708 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
2709 &OutChains[0], OutChains.size());
2715 //===----------------------------------------------------------------------===//
2716 // Return Value Calling Convention Implementation
2717 //===----------------------------------------------------------------------===//
2720 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2721 MachineFunction &MF, bool IsVarArg,
2722 const SmallVectorImpl<ISD::OutputArg> &Outs,
2723 LLVMContext &Context) const {
2724 SmallVector<CCValAssign, 16> RVLocs;
2725 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(),
2727 return CCInfo.CheckReturn(Outs, RetCC_Mips);
2731 MipsTargetLowering::LowerReturn(SDValue Chain,
2732 CallingConv::ID CallConv, bool IsVarArg,
2733 const SmallVectorImpl<ISD::OutputArg> &Outs,
2734 const SmallVectorImpl<SDValue> &OutVals,
2735 SDLoc DL, SelectionDAG &DAG) const {
2736 // CCValAssign - represent the assignment of
2737 // the return value to a location
2738 SmallVector<CCValAssign, 16> RVLocs;
2739 MachineFunction &MF = DAG.getMachineFunction();
2741 // CCState - Info about the registers and stack slot.
2742 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs,
2744 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo);
2746 // Analyze return values.
2747 MipsCCInfo.analyzeReturn(Outs, getTargetMachine().Options.UseSoftFloat,
2748 MF.getFunction()->getReturnType());
2751 SmallVector<SDValue, 4> RetOps(1, Chain);
2753 // Copy the result values into the output registers.
2754 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2755 SDValue Val = OutVals[i];
2756 CCValAssign &VA = RVLocs[i];
2757 assert(VA.isRegLoc() && "Can only return in registers!");
2759 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
2760 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val);
2762 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
2764 // Guarantee that all emitted copies are stuck together with flags.
2765 Flag = Chain.getValue(1);
2766 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2769 // The mips ABIs for returning structs by value requires that we copy
2770 // the sret argument into $v0 for the return. We saved the argument into
2771 // a virtual register in the entry block, so now we copy the value out
2773 if (MF.getFunction()->hasStructRetAttr()) {
2774 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2775 unsigned Reg = MipsFI->getSRetReturnReg();
2778 llvm_unreachable("sret virtual register not created in the entry block");
2779 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
2780 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0;
2782 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
2783 Flag = Chain.getValue(1);
2784 RetOps.push_back(DAG.getRegister(V0, getPointerTy()));
2787 RetOps[0] = Chain; // Update chain.
2789 // Add the flag if we have it.
2791 RetOps.push_back(Flag);
2793 // Return on Mips is always a "jr $ra"
2794 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, &RetOps[0], RetOps.size());
2797 //===----------------------------------------------------------------------===//
2798 // Mips Inline Assembly Support
2799 //===----------------------------------------------------------------------===//
2801 /// getConstraintType - Given a constraint letter, return the type of
2802 /// constraint it is for this target.
2803 MipsTargetLowering::ConstraintType MipsTargetLowering::
2804 getConstraintType(const std::string &Constraint) const
2806 // Mips specific constrainy
2807 // GCC config/mips/constraints.md
2809 // 'd' : An address register. Equivalent to r
2810 // unless generating MIPS16 code.
2811 // 'y' : Equivalent to r; retained for
2812 // backwards compatibility.
2813 // 'c' : A register suitable for use in an indirect
2814 // jump. This will always be $25 for -mabicalls.
2815 // 'l' : The lo register. 1 word storage.
2816 // 'x' : The hilo register pair. Double word storage.
2817 if (Constraint.size() == 1) {
2818 switch (Constraint[0]) {
2826 return C_RegisterClass;
2831 return TargetLowering::getConstraintType(Constraint);
2834 /// Examine constraint type and operand type and determine a weight value.
2835 /// This object must already have been set up with the operand type
2836 /// and the current alternative constraint selected.
2837 TargetLowering::ConstraintWeight
2838 MipsTargetLowering::getSingleConstraintMatchWeight(
2839 AsmOperandInfo &info, const char *constraint) const {
2840 ConstraintWeight weight = CW_Invalid;
2841 Value *CallOperandVal = info.CallOperandVal;
2842 // If we don't have a value, we can't do a match,
2843 // but allow it at the lowest weight.
2844 if (CallOperandVal == NULL)
2846 Type *type = CallOperandVal->getType();
2847 // Look at the constraint type.
2848 switch (*constraint) {
2850 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
2854 if (type->isIntegerTy())
2855 weight = CW_Register;
2858 if (type->isFloatTy())
2859 weight = CW_Register;
2861 case 'c': // $25 for indirect jumps
2862 case 'l': // lo register
2863 case 'x': // hilo register pair
2864 if (type->isIntegerTy())
2865 weight = CW_SpecificReg;
2867 case 'I': // signed 16 bit immediate
2868 case 'J': // integer zero
2869 case 'K': // unsigned 16 bit immediate
2870 case 'L': // signed 32 bit immediate where lower 16 bits are 0
2871 case 'N': // immediate in the range of -65535 to -1 (inclusive)
2872 case 'O': // signed 15 bit immediate (+- 16383)
2873 case 'P': // immediate in the range of 65535 to 1 (inclusive)
2874 if (isa<ConstantInt>(CallOperandVal))
2875 weight = CW_Constant;
2884 /// Given a register class constraint, like 'r', if this corresponds directly
2885 /// to an LLVM register class, return a register of 0 and the register class
2887 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
2888 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
2890 if (Constraint.size() == 1) {
2891 switch (Constraint[0]) {
2892 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
2893 case 'y': // Same as 'r'. Exists for compatibility.
2895 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
2896 if (Subtarget->inMips16Mode())
2897 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
2898 return std::make_pair(0U, &Mips::CPURegsRegClass);
2900 if (VT == MVT::i64 && !HasMips64)
2901 return std::make_pair(0U, &Mips::CPURegsRegClass);
2902 if (VT == MVT::i64 && HasMips64)
2903 return std::make_pair(0U, &Mips::CPU64RegsRegClass);
2904 // This will generate an error message
2905 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2908 return std::make_pair(0U, &Mips::FGR32RegClass);
2909 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
2910 if (Subtarget->isFP64bit())
2911 return std::make_pair(0U, &Mips::FGR64RegClass);
2912 return std::make_pair(0U, &Mips::AFGR64RegClass);
2915 case 'c': // register suitable for indirect jump
2917 return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass);
2918 assert(VT == MVT::i64 && "Unexpected type.");
2919 return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass);
2920 case 'l': // register suitable for indirect jump
2922 return std::make_pair((unsigned)Mips::LO, &Mips::LORegsRegClass);
2923 return std::make_pair((unsigned)Mips::LO64, &Mips::LORegs64RegClass);
2924 case 'x': // register suitable for indirect jump
2925 // Fixme: Not triggering the use of both hi and low
2926 // This will generate an error message
2927 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2930 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2933 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2934 /// vector. If it is invalid, don't add anything to Ops.
2935 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2936 std::string &Constraint,
2937 std::vector<SDValue>&Ops,
2938 SelectionDAG &DAG) const {
2939 SDValue Result(0, 0);
2941 // Only support length 1 constraints for now.
2942 if (Constraint.length() > 1) return;
2944 char ConstraintLetter = Constraint[0];
2945 switch (ConstraintLetter) {
2946 default: break; // This will fall through to the generic implementation
2947 case 'I': // Signed 16 bit constant
2948 // If this fails, the parent routine will give an error
2949 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2950 EVT Type = Op.getValueType();
2951 int64_t Val = C->getSExtValue();
2952 if (isInt<16>(Val)) {
2953 Result = DAG.getTargetConstant(Val, Type);
2958 case 'J': // integer zero
2959 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2960 EVT Type = Op.getValueType();
2961 int64_t Val = C->getZExtValue();
2963 Result = DAG.getTargetConstant(0, Type);
2968 case 'K': // unsigned 16 bit immediate
2969 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2970 EVT Type = Op.getValueType();
2971 uint64_t Val = (uint64_t)C->getZExtValue();
2972 if (isUInt<16>(Val)) {
2973 Result = DAG.getTargetConstant(Val, Type);
2978 case 'L': // signed 32 bit immediate where lower 16 bits are 0
2979 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2980 EVT Type = Op.getValueType();
2981 int64_t Val = C->getSExtValue();
2982 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
2983 Result = DAG.getTargetConstant(Val, Type);
2988 case 'N': // immediate in the range of -65535 to -1 (inclusive)
2989 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2990 EVT Type = Op.getValueType();
2991 int64_t Val = C->getSExtValue();
2992 if ((Val >= -65535) && (Val <= -1)) {
2993 Result = DAG.getTargetConstant(Val, Type);
2998 case 'O': // signed 15 bit immediate
2999 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3000 EVT Type = Op.getValueType();
3001 int64_t Val = C->getSExtValue();
3002 if ((isInt<15>(Val))) {
3003 Result = DAG.getTargetConstant(Val, Type);
3008 case 'P': // immediate in the range of 1 to 65535 (inclusive)
3009 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3010 EVT Type = Op.getValueType();
3011 int64_t Val = C->getSExtValue();
3012 if ((Val <= 65535) && (Val >= 1)) {
3013 Result = DAG.getTargetConstant(Val, Type);
3020 if (Result.getNode()) {
3021 Ops.push_back(Result);
3025 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3029 MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const {
3030 // No global is ever allowed as a base.
3035 case 0: // "r+i" or just "i", depending on HasBaseReg.
3038 if (!AM.HasBaseReg) // allow "r+i".
3040 return false; // disallow "r+r" or "r+r+i".
3049 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3050 // The Mips target isn't yet aware of offsets.
3054 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3056 bool IsMemset, bool ZeroMemset,
3058 MachineFunction &MF) const {
3059 if (Subtarget->hasMips64())
3065 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3066 if (VT != MVT::f32 && VT != MVT::f64)
3068 if (Imm.isNegZero())
3070 return Imm.isZero();
3073 unsigned MipsTargetLowering::getJumpTableEncoding() const {
3075 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
3077 return TargetLowering::getJumpTableEncoding();
3080 /// This function returns true if CallSym is a long double emulation routine.
3081 static bool isF128SoftLibCall(const char *CallSym) {
3082 const char *const LibCalls[] =
3083 {"__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", "__extendsftf2",
3084 "__fixtfdi", "__fixtfsi", "__fixtfti", "__fixunstfdi", "__fixunstfsi",
3085 "__fixunstfti", "__floatditf", "__floatsitf", "__floattitf",
3086 "__floatunditf", "__floatunsitf", "__floatuntitf", "__getf2", "__gttf2",
3087 "__letf2", "__lttf2", "__multf3", "__netf2", "__powitf2", "__subtf3",
3088 "__trunctfdf2", "__trunctfsf2", "__unordtf2",
3089 "ceill", "copysignl", "cosl", "exp2l", "expl", "floorl", "fmal", "fmodl",
3090 "log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl",
3093 const char * const *End = LibCalls + array_lengthof(LibCalls);
3095 // Check that LibCalls is sorted alphabetically.
3096 MipsTargetLowering::LTStr Comp;
3099 for (const char * const *I = LibCalls; I < End - 1; ++I)
3100 assert(Comp(*I, *(I + 1)));
3103 return std::binary_search(LibCalls, End, CallSym, Comp);
3106 /// This function returns true if Ty is fp128 or i128 which was originally a
3108 static bool originalTypeIsF128(const Type *Ty, const SDNode *CallNode) {
3109 if (Ty->isFP128Ty())
3112 const ExternalSymbolSDNode *ES =
3113 dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode);
3115 // If the Ty is i128 and the function being called is a long double emulation
3116 // routine, then the original type is f128.
3117 return (ES && Ty->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol()));
3120 MipsTargetLowering::MipsCC::SpecialCallingConvType
3121 MipsTargetLowering::getSpecialCallingConv(SDValue Callee) const {
3122 MipsCC::SpecialCallingConvType SpecialCallingConv =
3123 MipsCC::NoSpecialCallingConv;;
3124 if (Subtarget->inMips16HardFloat()) {
3125 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3126 llvm::StringRef Sym = G->getGlobal()->getName();
3127 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
3128 if (F->hasFnAttribute("__Mips16RetHelper")) {
3129 SpecialCallingConv = MipsCC::Mips16RetHelperConv;
3133 return SpecialCallingConv;
3136 MipsTargetLowering::MipsCC::MipsCC(
3137 CallingConv::ID CC, bool IsO32_, CCState &Info,
3138 MipsCC::SpecialCallingConvType SpecialCallingConv_)
3139 : CCInfo(Info), CallConv(CC), IsO32(IsO32_),
3140 SpecialCallingConv(SpecialCallingConv_){
3141 // Pre-allocate reserved argument area.
3142 CCInfo.AllocateStack(reservedArgArea(), 1);
3146 void MipsTargetLowering::MipsCC::
3147 analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args,
3148 bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode,
3149 std::vector<ArgListEntry> &FuncArgs) {
3150 assert((CallConv != CallingConv::Fast || !IsVarArg) &&
3151 "CallingConv::Fast shouldn't be used for vararg functions.");
3153 unsigned NumOpnds = Args.size();
3154 llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn();
3156 for (unsigned I = 0; I != NumOpnds; ++I) {
3157 MVT ArgVT = Args[I].VT;
3158 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
3161 if (ArgFlags.isByVal()) {
3162 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
3166 if (IsVarArg && !Args[I].IsFixed)
3167 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
3169 MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode,
3171 R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo);
3176 dbgs() << "Call operand #" << I << " has unhandled type "
3177 << EVT(ArgVT).getEVTString();
3179 llvm_unreachable(0);
3184 void MipsTargetLowering::MipsCC::
3185 analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args,
3186 bool IsSoftFloat, Function::const_arg_iterator FuncArg) {
3187 unsigned NumArgs = Args.size();
3188 llvm::CCAssignFn *FixedFn = fixedArgFn();
3189 unsigned CurArgIdx = 0;
3191 for (unsigned I = 0; I != NumArgs; ++I) {
3192 MVT ArgVT = Args[I].VT;
3193 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
3194 std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx);
3195 CurArgIdx = Args[I].OrigArgIndex;
3197 if (ArgFlags.isByVal()) {
3198 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
3202 MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), 0, IsSoftFloat);
3204 if (!FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo))
3208 dbgs() << "Formal Arg #" << I << " has unhandled type "
3209 << EVT(ArgVT).getEVTString();
3211 llvm_unreachable(0);
3215 template<typename Ty>
3216 void MipsTargetLowering::MipsCC::
3217 analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
3218 const SDNode *CallNode, const Type *RetTy) const {
3221 if (IsSoftFloat && originalTypeIsF128(RetTy, CallNode))
3222 Fn = RetCC_F128Soft;
3226 for (unsigned I = 0, E = RetVals.size(); I < E; ++I) {
3227 MVT VT = RetVals[I].VT;
3228 ISD::ArgFlagsTy Flags = RetVals[I].Flags;
3229 MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat);
3231 if (Fn(I, VT, RegVT, CCValAssign::Full, Flags, this->CCInfo)) {
3233 dbgs() << "Call result #" << I << " has unhandled type "
3234 << EVT(VT).getEVTString() << '\n';
3236 llvm_unreachable(0);
3241 void MipsTargetLowering::MipsCC::
3242 analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat,
3243 const SDNode *CallNode, const Type *RetTy) const {
3244 analyzeReturn(Ins, IsSoftFloat, CallNode, RetTy);
3247 void MipsTargetLowering::MipsCC::
3248 analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat,
3249 const Type *RetTy) const {
3250 analyzeReturn(Outs, IsSoftFloat, 0, RetTy);
3254 MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
3256 CCValAssign::LocInfo LocInfo,
3257 ISD::ArgFlagsTy ArgFlags) {
3258 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0.");
3260 struct ByValArgInfo ByVal;
3261 unsigned RegSize = regSize();
3262 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize);
3263 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize),
3266 if (useRegsForByval())
3267 allocateRegs(ByVal, ByValSize, Align);
3269 // Allocate space on caller's stack.
3270 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs,
3272 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT,
3274 ByValArgs.push_back(ByVal);
3277 unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const {
3278 return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs);
3281 unsigned MipsTargetLowering::MipsCC::reservedArgArea() const {
3282 return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0;
3285 const uint16_t *MipsTargetLowering::MipsCC::intArgRegs() const {
3286 return IsO32 ? O32IntRegs : Mips64IntRegs;
3289 llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const {
3290 if (CallConv == CallingConv::Fast)
3291 return CC_Mips_FastCC;
3293 if (SpecialCallingConv == Mips16RetHelperConv)
3294 return CC_Mips16RetHelper;
3295 return IsO32 ? CC_MipsO32 : CC_MipsN;
3298 llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const {
3299 return IsO32 ? CC_MipsO32 : CC_MipsN_VarArg;
3302 const uint16_t *MipsTargetLowering::MipsCC::shadowRegs() const {
3303 return IsO32 ? O32IntRegs : Mips64DPRegs;
3306 void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
3309 unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs();
3310 const uint16_t *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs();
3311 assert(!(ByValSize % RegSize) && !(Align % RegSize) &&
3312 "Byval argument's size and alignment should be a multiple of"
3315 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs);
3317 // If Align > RegSize, the first arg register must be even.
3318 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) {
3319 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]);
3323 // Mark the registers allocated.
3324 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs);
3325 ByValSize -= RegSize, ++I, ++ByVal.NumRegs)
3326 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]);
3329 MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy,
3330 const SDNode *CallNode,
3331 bool IsSoftFloat) const {
3332 if (IsSoftFloat || IsO32)
3335 // Check if the original type was fp128.
3336 if (originalTypeIsF128(OrigTy, CallNode)) {
3337 assert(VT == MVT::i64);
3344 void MipsTargetLowering::
3345 copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
3346 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
3347 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
3348 const MipsCC &CC, const ByValArgInfo &ByVal) const {
3349 MachineFunction &MF = DAG.getMachineFunction();
3350 MachineFrameInfo *MFI = MF.getFrameInfo();
3351 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize();
3352 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
3356 FrameObjOffset = (int)CC.reservedArgArea() -
3357 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize());
3359 FrameObjOffset = ByVal.Address;
3361 // Create frame object.
3362 EVT PtrTy = getPointerTy();
3363 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
3364 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
3365 InVals.push_back(FIN);
3370 // Copy arg registers.
3371 MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
3372 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3374 for (unsigned I = 0; I < ByVal.NumRegs; ++I) {
3375 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I];
3376 unsigned VReg = addLiveIn(MF, ArgReg, RC);
3377 unsigned Offset = I * CC.regSize();
3378 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
3379 DAG.getConstant(Offset, PtrTy));
3380 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
3381 StorePtr, MachinePointerInfo(FuncArg, Offset),
3383 OutChains.push_back(Store);
3387 // Copy byVal arg to registers and stack.
3388 void MipsTargetLowering::
3389 passByValArg(SDValue Chain, SDLoc DL,
3390 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
3391 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
3392 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
3393 const MipsCC &CC, const ByValArgInfo &ByVal,
3394 const ISD::ArgFlagsTy &Flags, bool isLittle) const {
3395 unsigned ByValSize = Flags.getByValSize();
3396 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
3397 unsigned RegSize = CC.regSize();
3398 unsigned Alignment = std::min(Flags.getByValAlign(), RegSize);
3399 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8);
3401 if (ByVal.NumRegs) {
3402 const uint16_t *ArgRegs = CC.intArgRegs();
3403 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize);
3406 // Copy words to registers.
3407 for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) {
3408 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3409 DAG.getConstant(Offset, PtrTy));
3410 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
3411 MachinePointerInfo(), false, false, false,
3413 MemOpChains.push_back(LoadVal.getValue(1));
3414 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
3415 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
3418 // Return if the struct has been fully copied.
3419 if (ByValSize == Offset)
3422 // Copy the remainder of the byval argument with sub-word loads and shifts.
3423 if (LeftoverBytes) {
3424 assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) &&
3425 "Size of the remainder should be smaller than RegSize.");
3428 for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0;
3429 Offset < ByValSize; LoadSize /= 2) {
3430 unsigned RemSize = ByValSize - Offset;
3432 if (RemSize < LoadSize)
3436 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3437 DAG.getConstant(Offset, PtrTy));
3439 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr,
3440 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
3441 false, false, Alignment);
3442 MemOpChains.push_back(LoadVal.getValue(1));
3444 // Shift the loaded value.
3448 Shamt = TotalSizeLoaded;
3450 Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8;
3452 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
3453 DAG.getConstant(Shamt, MVT::i32));
3456 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
3461 TotalSizeLoaded += LoadSize;
3462 Alignment = std::min(Alignment, LoadSize);
3465 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
3466 RegsToPass.push_back(std::make_pair(ArgReg, Val));
3471 // Copy remainder of byval arg to it with memcpy.
3472 unsigned MemCpySize = ByValSize - Offset;
3473 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3474 DAG.getConstant(Offset, PtrTy));
3475 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
3476 DAG.getIntPtrConstant(ByVal.Address));
3477 Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
3478 DAG.getConstant(MemCpySize, PtrTy), Alignment,
3479 /*isVolatile=*/false, /*AlwaysInline=*/false,
3480 MachinePointerInfo(0), MachinePointerInfo(0));
3481 MemOpChains.push_back(Chain);
3485 MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
3486 const MipsCC &CC, SDValue Chain,
3487 SDLoc DL, SelectionDAG &DAG) const {
3488 unsigned NumRegs = CC.numIntArgRegs();
3489 const uint16_t *ArgRegs = CC.intArgRegs();
3490 const CCState &CCInfo = CC.getCCInfo();
3491 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs);
3492 unsigned RegSize = CC.regSize();
3493 MVT RegTy = MVT::getIntegerVT(RegSize * 8);
3494 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3495 MachineFunction &MF = DAG.getMachineFunction();
3496 MachineFrameInfo *MFI = MF.getFrameInfo();
3497 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3499 // Offset of the first variable argument from stack pointer.
3503 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize);
3506 (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx));
3508 // Record the frame index of the first variable argument
3509 // which is a value necessary to VASTART.
3510 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
3511 MipsFI->setVarArgsFrameIndex(FI);
3513 // Copy the integer registers that have not been used for argument passing
3514 // to the argument register save area. For O32, the save area is allocated
3515 // in the caller's stack frame, while for N32/64, it is allocated in the
3516 // callee's stack frame.
3517 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) {
3518 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
3519 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
3520 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
3521 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
3522 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
3523 MachinePointerInfo(), false, false, 0);
3524 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0);
3525 OutChains.push_back(Store);