1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
36 const char *MipsTargetLowering::
37 getTargetNodeName(unsigned Opcode) const
41 case MipsISD::JmpLink : return "MipsISD::JmpLink";
42 case MipsISD::Hi : return "MipsISD::Hi";
43 case MipsISD::Lo : return "MipsISD::Lo";
44 case MipsISD::GPRel : return "MipsISD::GPRel";
45 case MipsISD::Ret : return "MipsISD::Ret";
46 case MipsISD::CMov : return "MipsISD::CMov";
47 case MipsISD::SelectCC : return "MipsISD::SelectCC";
48 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
49 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
50 case MipsISD::FPCmp : return "MipsISD::FPCmp";
51 default : return NULL;
56 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
58 Subtarget = &TM.getSubtarget<MipsSubtarget>();
60 // Mips does not have i1 type, so use i32 for
61 // setcc operations results (slt, sgt, ...).
62 setBooleanContents(ZeroOrOneBooleanContent);
64 // JumpTable targets must use GOT when using PIC_
65 setUsesGlobalOffsetTable(true);
67 // Set up the register classes
68 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
70 // When dealing with single precision only, use libcalls
71 if (!Subtarget->isSingleFloat()) {
72 addRegisterClass(MVT::f32, Mips::AFGR32RegisterClass);
73 if (!Subtarget->isFP64bit())
74 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
76 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
79 addLegalFPImmediate(APFloat(+0.0f));
81 // Load extented operations for i1 types must be promoted
82 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
83 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
86 // Used by legalize types to correctly generate the setcc result.
87 // Without this, every float setcc comes with a AND/OR with the result,
88 // we don't want this, since the fpcmp result goes to a flag register,
89 // which is used implicitly by brcond and select operations.
90 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
92 // Mips Custom Operations
93 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
94 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
95 setOperationAction(ISD::RET, MVT::Other, Custom);
96 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
97 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
98 setOperationAction(ISD::SELECT, MVT::f32, Custom);
99 setOperationAction(ISD::SELECT, MVT::i32, Custom);
100 setOperationAction(ISD::SETCC, MVT::f32, Custom);
101 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
102 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
104 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
105 // with operands comming from setcc fp comparions. This is necessary since
106 // the result from these setcc are in a flag registers (FCR31).
107 setOperationAction(ISD::AND, MVT::i32, Custom);
108 setOperationAction(ISD::OR, MVT::i32, Custom);
110 // Operations not directly supported by Mips.
111 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
112 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
113 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
114 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
115 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
117 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
118 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
119 setOperationAction(ISD::ROTL, MVT::i32, Expand);
120 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
121 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
122 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
123 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
125 // We don't have line number support yet.
126 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
127 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
128 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
129 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
131 // Use the default for now
132 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
133 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
134 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
136 if (Subtarget->isSingleFloat())
137 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
139 if (!Subtarget->hasSEInReg()) {
140 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
141 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
144 if (!Subtarget->hasBitCount())
145 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
147 if (!Subtarget->hasSwap())
148 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
150 setStackPointerRegisterToSaveRestore(Mips::SP);
151 computeRegisterProperties();
155 MVT MipsTargetLowering::getSetCCResultType(MVT VT) const {
160 SDValue MipsTargetLowering::
161 LowerOperation(SDValue Op, SelectionDAG &DAG)
163 switch (Op.getOpcode())
165 case ISD::AND: return LowerANDOR(Op, DAG);
166 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
167 case ISD::CALL: return LowerCALL(Op, DAG);
168 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
169 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
170 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
171 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
172 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
173 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
174 case ISD::OR: return LowerANDOR(Op, DAG);
175 case ISD::RET: return LowerRET(Op, DAG);
176 case ISD::SELECT: return LowerSELECT(Op, DAG);
177 case ISD::SETCC: return LowerSETCC(Op, DAG);
182 //===----------------------------------------------------------------------===//
183 // Lower helper functions
184 //===----------------------------------------------------------------------===//
186 // AddLiveIn - This helper function adds the specified physical register to the
187 // MachineFunction as a live in value. It also creates a corresponding
188 // virtual register for it.
190 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
192 assert(RC->contains(PReg) && "Not the correct regclass!");
193 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
194 MF.getRegInfo().addLiveIn(PReg, VReg);
198 // A address must be loaded from a small section if its size is less than the
199 // small section size threshold. Data in this section must be addressed using
201 bool MipsTargetLowering::IsInSmallSection(unsigned Size) {
202 return (Size > 0 && (Size <= Subtarget->getSSectionThreshold()));
205 // Discover if this global address can be placed into small data/bss section.
206 bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV)
208 const TargetData *TD = getTargetData();
209 const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV);
214 const Type *Ty = GV->getType()->getElementType();
215 unsigned Size = TD->getTypePaddedSize(Ty);
217 // if this is a internal constant string, there is a special
218 // section for it, but not in small data/bss.
219 if (GVA->hasInitializer() && GV->hasLocalLinkage()) {
220 Constant *C = GVA->getInitializer();
221 const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
222 if (CVA && CVA->isCString())
226 return IsInSmallSection(Size);
229 // Get fp branch code (not opcode) from condition code.
230 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
231 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
232 return Mips::BRANCH_T;
234 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
235 return Mips::BRANCH_F;
237 return Mips::BRANCH_INVALID;
240 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
243 assert(0 && "Unknown branch code");
244 case Mips::BRANCH_T : return Mips::BC1T;
245 case Mips::BRANCH_F : return Mips::BC1F;
246 case Mips::BRANCH_TL : return Mips::BC1TL;
247 case Mips::BRANCH_FL : return Mips::BC1FL;
251 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
253 default: assert(0 && "Unknown fp condition code!");
255 case ISD::SETOEQ: return Mips::FCOND_EQ;
256 case ISD::SETUNE: return Mips::FCOND_OGL;
258 case ISD::SETOLT: return Mips::FCOND_OLT;
260 case ISD::SETOGT: return Mips::FCOND_OGT;
262 case ISD::SETOLE: return Mips::FCOND_OLE;
264 case ISD::SETOGE: return Mips::FCOND_OGE;
265 case ISD::SETULT: return Mips::FCOND_ULT;
266 case ISD::SETULE: return Mips::FCOND_ULE;
267 case ISD::SETUGT: return Mips::FCOND_UGT;
268 case ISD::SETUGE: return Mips::FCOND_UGE;
269 case ISD::SETUO: return Mips::FCOND_UN;
270 case ISD::SETO: return Mips::FCOND_OR;
272 case ISD::SETONE: return Mips::FCOND_NEQ;
273 case ISD::SETUEQ: return Mips::FCOND_UEQ;
278 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
279 MachineBasicBlock *BB) const {
280 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
281 bool isFPCmp = false;
282 DebugLoc dl = MI->getDebugLoc();
284 switch (MI->getOpcode()) {
285 default: assert(false && "Unexpected instr type to insert");
286 case Mips::Select_FCC:
287 case Mips::Select_FCC_SO32:
288 case Mips::Select_FCC_AS32:
289 case Mips::Select_FCC_D32:
290 isFPCmp = true; // FALL THROUGH
291 case Mips::Select_CC:
292 case Mips::Select_CC_SO32:
293 case Mips::Select_CC_AS32:
294 case Mips::Select_CC_D32: {
295 // To "insert" a SELECT_CC instruction, we actually have to insert the
296 // diamond control-flow pattern. The incoming instruction knows the
297 // destination vreg to set, the condition code register to branch on, the
298 // true/false values to select between, and a branch opcode to use.
299 const BasicBlock *LLVM_BB = BB->getBasicBlock();
300 MachineFunction::iterator It = BB;
307 // bNE r1, r0, copy1MBB
308 // fallthrough --> copy0MBB
309 MachineBasicBlock *thisMBB = BB;
310 MachineFunction *F = BB->getParent();
311 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
312 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
314 // Emit the right instruction according to the type of the operands compared
316 // Find the condiction code present in the setcc operation.
317 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
318 // Get the branch opcode from the branch code.
319 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
320 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
322 BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
323 .addReg(Mips::ZERO).addMBB(sinkMBB);
325 F->insert(It, copy0MBB);
326 F->insert(It, sinkMBB);
327 // Update machine-CFG edges by first adding all successors of the current
328 // block to the new block which will contain the Phi node for the select.
329 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
330 e = BB->succ_end(); i != e; ++i)
331 sinkMBB->addSuccessor(*i);
332 // Next, remove all successors of the current block, and add the true
333 // and fallthrough blocks as its successors.
334 while(!BB->succ_empty())
335 BB->removeSuccessor(BB->succ_begin());
336 BB->addSuccessor(copy0MBB);
337 BB->addSuccessor(sinkMBB);
341 // # fallthrough to sinkMBB
344 // Update machine-CFG edges
345 BB->addSuccessor(sinkMBB);
348 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
351 BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg())
352 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
353 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
355 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
361 //===----------------------------------------------------------------------===//
362 // Misc Lower Operation implementation
363 //===----------------------------------------------------------------------===//
365 SDValue MipsTargetLowering::
366 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
368 SDValue Chain = Op.getOperand(0);
369 SDValue Size = Op.getOperand(1);
370 DebugLoc dl = Op.getDebugLoc();
372 // Get a reference from Mips stack pointer
373 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
375 // Subtract the dynamic size from the actual stack size to
376 // obtain the new stack size.
377 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
379 // The Sub result contains the new stack start address, so it
380 // must be placed in the stack pointer register.
381 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
383 // This node always has two return values: a new stack pointer
385 SDValue Ops[2] = { Sub, Chain };
386 return DAG.getMergeValues(Ops, 2, dl);
389 SDValue MipsTargetLowering::
390 LowerANDOR(SDValue Op, SelectionDAG &DAG)
392 SDValue LHS = Op.getOperand(0);
393 SDValue RHS = Op.getOperand(1);
394 DebugLoc dl = Op.getDebugLoc();
396 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
399 SDValue True = DAG.getConstant(1, MVT::i32);
400 SDValue False = DAG.getConstant(0, MVT::i32);
402 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
403 LHS, True, False, LHS.getOperand(2));
404 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
405 RHS, True, False, RHS.getOperand(2));
407 return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
410 SDValue MipsTargetLowering::
411 LowerBRCOND(SDValue Op, SelectionDAG &DAG)
413 // The first operand is the chain, the second is the condition, the third is
414 // the block to branch to if the condition is true.
415 SDValue Chain = Op.getOperand(0);
416 SDValue Dest = Op.getOperand(2);
417 DebugLoc dl = Op.getDebugLoc();
419 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
422 SDValue CondRes = Op.getOperand(1);
423 SDValue CCNode = CondRes.getOperand(2);
425 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
426 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
428 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
432 SDValue MipsTargetLowering::
433 LowerSETCC(SDValue Op, SelectionDAG &DAG)
435 // The operands to this are the left and right operands to compare (ops #0,
436 // and #1) and the condition code to compare them with (op #2) as a
438 SDValue LHS = Op.getOperand(0);
439 SDValue RHS = Op.getOperand(1);
440 DebugLoc dl = Op.getDebugLoc();
442 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
444 return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
445 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
448 SDValue MipsTargetLowering::
449 LowerSELECT(SDValue Op, SelectionDAG &DAG)
451 SDValue Cond = Op.getOperand(0);
452 SDValue True = Op.getOperand(1);
453 SDValue False = Op.getOperand(2);
454 DebugLoc dl = Op.getDebugLoc();
456 // if the incomming condition comes from a integer compare, the select
457 // operation must be SelectCC or a conditional move if the subtarget
459 if (Cond.getOpcode() != MipsISD::FPCmp) {
460 if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
462 return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(),
466 // if the incomming condition comes from fpcmp, the select
467 // operation must use FPSelectCC.
468 SDValue CCNode = Cond.getOperand(2);
469 return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
470 Cond, True, False, CCNode);
473 SDValue MipsTargetLowering::
474 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
476 // FIXME there isn't actually debug info here
477 DebugLoc dl = Op.getDebugLoc();
478 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
479 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
481 if (!Subtarget->hasABICall()) {
482 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
483 SDValue Ops[] = { GA };
484 // %gp_rel relocation
485 if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) {
486 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, 1, Ops, 1);
487 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
488 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
490 // %hi/%lo relocation
491 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, 1, Ops, 1);
492 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
493 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
495 } else { // Abicall relocations, TODO: make this cleaner.
496 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
497 DAG.getEntryNode(), GA, NULL, 0);
498 // On functions and global targets not internal linked only
499 // a load from got/GP is necessary for PIC to work.
500 if (!GV->hasLocalLinkage() || isa<Function>(GV))
502 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
503 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
506 assert(0 && "Dont know how to handle GlobalAddress");
510 SDValue MipsTargetLowering::
511 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
513 assert(0 && "TLS not implemented for MIPS.");
514 return SDValue(); // Not reached
517 SDValue MipsTargetLowering::
518 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
522 // FIXME there isn't actually debug info here
523 DebugLoc dl = Op.getDebugLoc();
525 MVT PtrVT = Op.getValueType();
526 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
527 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
529 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
530 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
531 SDValue Ops[] = { JTI };
532 HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, 1, Ops, 1);
533 } else // Emit Load from Global Pointer
534 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
536 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
537 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
542 SDValue MipsTargetLowering::
543 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
546 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
547 Constant *C = N->getConstVal();
548 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
549 // FIXME there isn't actually debug info here
550 DebugLoc dl = Op.getDebugLoc();
553 // FIXME: we should reference the constant pool using small data sections,
554 // but the asm printer currently doens't support this feature without
555 // hacking it. This feature should come soon so we can uncomment the
557 //if (!Subtarget->hasABICall() &&
558 // IsInSmallSection(getTargetData()->getTypePaddedSize(C->getType()))) {
559 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
560 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
561 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
562 //} else { // %hi/%lo relocation
563 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
564 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
565 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
571 //===----------------------------------------------------------------------===//
572 // Calling Convention Implementation
574 // The lower operations present on calling convention works on this order:
575 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
576 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
577 // LowerRET (virt regs --> phys regs)
578 // LowerCALL (phys regs --> virt regs)
580 //===----------------------------------------------------------------------===//
582 #include "MipsGenCallingConv.inc"
584 //===----------------------------------------------------------------------===//
585 // TODO: Implement a generic logic using tblgen that can support this.
586 // Mips O32 ABI rules:
588 // i32 - Passed in A0, A1, A2, A3 and stack
589 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
590 // an argument. Otherwise, passed in A1, A2, A3 and stack.
591 // f64 - Only passed in two aliased f32 registers if no int reg has been used
592 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
593 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
595 //===----------------------------------------------------------------------===//
597 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
598 MVT LocVT, CCValAssign::LocInfo LocInfo,
599 ISD::ArgFlagsTy ArgFlags, CCState &State) {
601 static const unsigned IntRegsSize=4, FloatRegsSize=2;
603 static const unsigned IntRegs[] = {
604 Mips::A0, Mips::A1, Mips::A2, Mips::A3
606 static const unsigned F32Regs[] = {
609 static const unsigned F64Regs[] = {
614 unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
615 bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0)));
617 // Promote i8 and i16
618 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
620 if (ArgFlags.isSExt())
621 LocInfo = CCValAssign::SExt;
622 else if (ArgFlags.isZExt())
623 LocInfo = CCValAssign::ZExt;
625 LocInfo = CCValAssign::AExt;
628 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) {
629 Reg = State.AllocateReg(IntRegs, IntRegsSize);
634 if (ValVT.isFloatingPoint() && !IntRegUsed) {
635 if (ValVT == MVT::f32)
636 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
638 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
641 if (ValVT == MVT::f64 && IntRegUsed) {
642 if (UnallocIntReg != IntRegsSize) {
643 // If we hit register A3 as the first not allocated, we must
644 // mark it as allocated (shadow) and use the stack instead.
645 if (IntRegs[UnallocIntReg] != (unsigned (Mips::A3)))
647 for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg)
648 State.AllocateReg(UnallocIntReg);
654 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
655 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
656 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
658 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
660 return false; // CC must always match
663 //===----------------------------------------------------------------------===//
664 // CALL Calling Convention Implementation
665 //===----------------------------------------------------------------------===//
667 /// LowerCALL - functions arguments are copied from virtual regs to
668 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
669 /// TODO: isVarArg, isTailCall.
670 SDValue MipsTargetLowering::
671 LowerCALL(SDValue Op, SelectionDAG &DAG)
673 MachineFunction &MF = DAG.getMachineFunction();
675 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
676 SDValue Chain = TheCall->getChain();
677 SDValue Callee = TheCall->getCallee();
678 bool isVarArg = TheCall->isVarArg();
679 unsigned CC = TheCall->getCallingConv();
680 DebugLoc dl = TheCall->getDebugLoc();
682 MachineFrameInfo *MFI = MF.getFrameInfo();
684 // Analyze operands of the call, assigning locations to each operand.
685 SmallVector<CCValAssign, 16> ArgLocs;
686 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
688 // To meet O32 ABI, Mips must always allocate 16 bytes on
689 // the stack (even if less than 4 are used as arguments)
690 if (Subtarget->isABI_O32()) {
691 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
692 MFI->CreateFixedObject(VTsize, (VTsize*3));
693 CCInfo.AnalyzeCallOperands(TheCall, CC_MipsO32);
695 CCInfo.AnalyzeCallOperands(TheCall, CC_Mips);
697 // Get a count of how many bytes are to be pushed on the stack.
698 unsigned NumBytes = CCInfo.getNextStackOffset();
699 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
701 // With EABI is it possible to have 16 args on registers.
702 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
703 SmallVector<SDValue, 8> MemOpChains;
705 // First/LastArgStackLoc contains the first/last
706 // "at stack" argument location.
707 int LastArgStackLoc = 0;
708 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
710 // Walk the register/memloc assignments, inserting copies/loads.
711 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
712 SDValue Arg = TheCall->getArg(i);
713 CCValAssign &VA = ArgLocs[i];
715 // Promote the value if needed.
716 switch (VA.getLocInfo()) {
717 default: assert(0 && "Unknown loc info!");
718 case CCValAssign::Full:
719 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
720 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
721 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg);
722 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
723 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
724 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
725 DAG.getConstant(0, getPointerTy()));
726 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
727 DAG.getConstant(1, getPointerTy()));
728 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
729 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
734 case CCValAssign::SExt:
735 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
737 case CCValAssign::ZExt:
738 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
740 case CCValAssign::AExt:
741 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
745 // Arguments that can be passed on register must be kept at
748 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
752 // Register can't get to this point...
753 assert(VA.isMemLoc());
755 // Create the frame index object for this incoming parameter
756 // This guarantees that when allocating Local Area the firsts
757 // 16 bytes which are alwayes reserved won't be overwritten
758 // if O32 ABI is used. For EABI the first address is zero.
759 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
760 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
763 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
765 // emit ISD::STORE whichs stores the
766 // parameter value to a stack Location
767 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
770 // Transform all store nodes into one single node because all store
771 // nodes are independent of each other.
772 if (!MemOpChains.empty())
773 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
774 &MemOpChains[0], MemOpChains.size());
776 // Build a sequence of copy-to-reg nodes chained together with token
777 // chain and flag operands which copy the outgoing args into registers.
778 // The InFlag in necessary since all emited instructions must be
781 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
782 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
783 RegsToPass[i].second, InFlag);
784 InFlag = Chain.getValue(1);
787 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
788 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
789 // node so that legalize doesn't hack it.
790 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
791 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
792 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
793 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
795 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
796 // = Chain, Callee, Reg#1, Reg#2, ...
798 // Returns a chain & a flag for retval copy to use.
799 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
800 SmallVector<SDValue, 8> Ops;
801 Ops.push_back(Chain);
802 Ops.push_back(Callee);
804 // Add argument registers to the end of the list so that they are
805 // known live into the call.
806 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
807 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
808 RegsToPass[i].second.getValueType()));
810 if (InFlag.getNode())
811 Ops.push_back(InFlag);
813 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
814 InFlag = Chain.getValue(1);
816 // Create the CALLSEQ_END node.
817 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
818 DAG.getIntPtrConstant(0, true), InFlag);
819 InFlag = Chain.getValue(1);
821 // Create a stack location to hold GP when PIC is used. This stack
822 // location is used on function prologue to save GP and also after all
823 // emited CALL's to restore GP.
824 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
825 // Function can have an arbitrary number of calls, so
826 // hold the LastArgStackLoc with the biggest offset.
828 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
829 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
830 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
831 // Create the frame index only once. SPOffset here can be anything
832 // (this will be fixed on processFunctionBeforeFrameFinalized)
833 if (MipsFI->getGPStackOffset() == -1) {
834 FI = MFI->CreateFixedObject(4, 0);
837 MipsFI->setGPStackOffset(LastArgStackLoc);
841 FI = MipsFI->getGPFI();
842 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
843 SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0);
844 Chain = GPLoad.getValue(1);
845 Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
846 GPLoad, SDValue(0,0));
847 InFlag = Chain.getValue(1);
850 // Handle result values, copying them out of physregs into vregs that we
852 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG), Op.getResNo());
855 /// LowerCallResult - Lower the result values of an ISD::CALL into the
856 /// appropriate copies out of appropriate physical registers. This assumes that
857 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
858 /// being lowered. Returns a SDNode with the same number of values as the
860 SDNode *MipsTargetLowering::
861 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
862 unsigned CallingConv, SelectionDAG &DAG) {
864 bool isVarArg = TheCall->isVarArg();
865 DebugLoc dl = TheCall->getDebugLoc();
867 // Assign locations to each value returned by this call.
868 SmallVector<CCValAssign, 16> RVLocs;
869 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
871 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
872 SmallVector<SDValue, 8> ResultVals;
874 // Copy all of the result registers out of their specified physreg.
875 for (unsigned i = 0; i != RVLocs.size(); ++i) {
876 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
877 RVLocs[i].getValVT(), InFlag).getValue(1);
878 InFlag = Chain.getValue(2);
879 ResultVals.push_back(Chain.getValue(0));
882 ResultVals.push_back(Chain);
884 // Merge everything together with a MERGE_VALUES node.
885 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
886 &ResultVals[0], ResultVals.size()).getNode();
889 //===----------------------------------------------------------------------===//
890 // FORMAL_ARGUMENTS Calling Convention Implementation
891 //===----------------------------------------------------------------------===//
893 /// LowerFORMAL_ARGUMENTS - transform physical registers into
894 /// virtual registers and generate load operations for
895 /// arguments places on the stack.
897 SDValue MipsTargetLowering::
898 LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
900 SDValue Root = Op.getOperand(0);
901 MachineFunction &MF = DAG.getMachineFunction();
902 MachineFrameInfo *MFI = MF.getFrameInfo();
903 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
904 DebugLoc dl = Op.getDebugLoc();
906 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
907 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
909 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
911 // GP must be live into PIC and non-PIC call target.
912 AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
914 // Assign locations to all of the incoming arguments.
915 SmallVector<CCValAssign, 16> ArgLocs;
916 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
918 if (Subtarget->isABI_O32())
919 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MipsO32);
921 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_Mips);
923 SmallVector<SDValue, 16> ArgValues;
926 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
928 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
929 CCValAssign &VA = ArgLocs[i];
931 // Arguments stored on registers
933 MVT RegVT = VA.getLocVT();
934 TargetRegisterClass *RC = 0;
936 if (RegVT == MVT::i32)
937 RC = Mips::CPURegsRegisterClass;
938 else if (RegVT == MVT::f32) {
939 if (Subtarget->isSingleFloat())
940 RC = Mips::FGR32RegisterClass;
942 RC = Mips::AFGR32RegisterClass;
943 } else if (RegVT == MVT::f64) {
944 if (!Subtarget->isSingleFloat())
945 RC = Mips::AFGR64RegisterClass;
947 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
949 // Transform the arguments stored on
950 // physical registers into virtual ones
951 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
952 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
954 // If this is an 8 or 16-bit value, it has been passed promoted
955 // to 32 bits. Insert an assert[sz]ext to capture this, then
956 // truncate to the right size.
957 if (VA.getLocInfo() != CCValAssign::Full) {
959 if (VA.getLocInfo() == CCValAssign::SExt)
960 Opcode = ISD::AssertSext;
961 else if (VA.getLocInfo() == CCValAssign::ZExt)
962 Opcode = ISD::AssertZext;
963 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
964 DAG.getValueType(VA.getValVT()));
965 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
968 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
969 if (Subtarget->isABI_O32()) {
970 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
971 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
972 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
973 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
974 VA.getLocReg()+1, RC);
975 SDValue ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg2, RegVT);
976 SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
977 SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2);
978 ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi);
982 ArgValues.push_back(ArgValue);
984 // To meet ABI, when VARARGS are passed on registers, the registers
985 // must have their values written to the caller stack frame.
986 if ((isVarArg) && (Subtarget->isABI_O32())) {
987 if (StackPtr.getNode() == 0)
988 StackPtr = DAG.getRegister(StackReg, getPointerTy());
990 // The stack pointer offset is relative to the caller stack frame.
991 // Since the real stack size is unknown here, a negative SPOffset
992 // is used so there's a way to adjust these offsets when the stack
993 // size get known (on EliminateFrameIndex). A dummy SPOffset is
994 // used instead of a direct negative address (which is recorded to
995 // be used on emitPrologue) to avoid mis-calc of the first stack
996 // offset on PEI::calculateFrameObjectOffsets.
997 // Arguments are always 32-bit.
998 int FI = MFI->CreateFixedObject(4, 0);
999 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
1000 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
1002 // emit ISD::STORE whichs stores the
1003 // parameter value to a stack Location
1004 ArgValues.push_back(DAG.getStore(Root, dl, ArgValue, PtrOff, NULL, 0));
1007 } else { // VA.isRegLoc()
1010 assert(VA.isMemLoc());
1012 // The stack pointer offset is relative to the caller stack frame.
1013 // Since the real stack size is unknown here, a negative SPOffset
1014 // is used so there's a way to adjust these offsets when the stack
1015 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1016 // used instead of a direct negative address (which is recorded to
1017 // be used on emitPrologue) to avoid mis-calc of the first stack
1018 // offset on PEI::calculateFrameObjectOffsets.
1019 // Arguments are always 32-bit.
1020 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1021 int FI = MFI->CreateFixedObject(ArgSize, 0);
1022 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
1023 (FirstStackArgLoc + VA.getLocMemOffset())));
1025 // Create load nodes to retrieve arguments from the stack
1026 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1027 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0));
1031 // The mips ABIs for returning structs by value requires that we copy
1032 // the sret argument into $v0 for the return. Save the argument into
1033 // a virtual register so that we can access it from the return points.
1034 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1035 unsigned Reg = MipsFI->getSRetReturnReg();
1037 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1038 MipsFI->setSRetReturnReg(Reg);
1040 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]);
1041 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root);
1044 ArgValues.push_back(Root);
1046 // Return the new list of results.
1047 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1048 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1051 //===----------------------------------------------------------------------===//
1052 // Return Value Calling Convention Implementation
1053 //===----------------------------------------------------------------------===//
1055 SDValue MipsTargetLowering::
1056 LowerRET(SDValue Op, SelectionDAG &DAG)
1058 // CCValAssign - represent the assignment of
1059 // the return value to a location
1060 SmallVector<CCValAssign, 16> RVLocs;
1061 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1062 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1063 DebugLoc dl = Op.getDebugLoc();
1065 // CCState - Info about the registers and stack slot.
1066 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
1068 // Analize return values of ISD::RET
1069 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Mips);
1071 // If this is the first return lowered for this function, add
1072 // the regs to the liveout set for the function.
1073 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1074 for (unsigned i = 0; i != RVLocs.size(); ++i)
1075 if (RVLocs[i].isRegLoc())
1076 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1079 // The chain is always operand #0
1080 SDValue Chain = Op.getOperand(0);
1083 // Copy the result values into the output registers.
1084 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1085 CCValAssign &VA = RVLocs[i];
1086 assert(VA.isRegLoc() && "Can only return in registers!");
1088 // ISD::RET => ret chain, (regnum1,val1), ...
1089 // So i*2+1 index only the regnums
1090 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1091 Op.getOperand(i*2+1), Flag);
1093 // guarantee that all emitted copies are
1094 // stuck together, avoiding something bad
1095 Flag = Chain.getValue(1);
1098 // The mips ABIs for returning structs by value requires that we copy
1099 // the sret argument into $v0 for the return. We saved the argument into
1100 // a virtual register in the entry block, so now we copy the value out
1102 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1103 MachineFunction &MF = DAG.getMachineFunction();
1104 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1105 unsigned Reg = MipsFI->getSRetReturnReg();
1108 assert(0 && "sret virtual register not created in the entry block");
1109 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1111 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1112 Flag = Chain.getValue(1);
1115 // Return on Mips is always a "jr $ra"
1117 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1118 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1120 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1121 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1124 //===----------------------------------------------------------------------===//
1125 // Mips Inline Assembly Support
1126 //===----------------------------------------------------------------------===//
1128 /// getConstraintType - Given a constraint letter, return the type of
1129 /// constraint it is for this target.
1130 MipsTargetLowering::ConstraintType MipsTargetLowering::
1131 getConstraintType(const std::string &Constraint) const
1133 // Mips specific constrainy
1134 // GCC config/mips/constraints.md
1136 // 'd' : An address register. Equivalent to r
1137 // unless generating MIPS16 code.
1138 // 'y' : Equivalent to r; retained for
1139 // backwards compatibility.
1140 // 'f' : Floating Point registers.
1141 if (Constraint.size() == 1) {
1142 switch (Constraint[0]) {
1147 return C_RegisterClass;
1151 return TargetLowering::getConstraintType(Constraint);
1154 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1155 /// return a list of registers that can be used to satisfy the constraint.
1156 /// This should only be used for C_RegisterClass constraints.
1157 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1158 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
1160 if (Constraint.size() == 1) {
1161 switch (Constraint[0]) {
1163 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1165 if (VT == MVT::f32) {
1166 if (Subtarget->isSingleFloat())
1167 return std::make_pair(0U, Mips::FGR32RegisterClass);
1169 return std::make_pair(0U, Mips::AFGR32RegisterClass);
1172 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1173 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1176 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1179 /// Given a register class constraint, like 'r', if this corresponds directly
1180 /// to an LLVM register class, return a register of 0 and the register class
1182 std::vector<unsigned> MipsTargetLowering::
1183 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1186 if (Constraint.size() != 1)
1187 return std::vector<unsigned>();
1189 switch (Constraint[0]) {
1192 // GCC Mips Constraint Letters
1195 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1196 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1197 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1201 if (VT == MVT::f32) {
1202 if (Subtarget->isSingleFloat())
1203 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1204 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1205 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1206 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1207 Mips::F30, Mips::F31, 0);
1209 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1210 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1211 Mips::F28, Mips::F30, 0);
1215 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1216 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1217 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1218 Mips::D14, Mips::D15, 0);
1220 return std::vector<unsigned>();
1224 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1225 // The Mips target isn't yet aware of offsets.