1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "MipsTargetObjectFile.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
37 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
39 case MipsISD::JmpLink : return "MipsISD::JmpLink";
40 case MipsISD::Hi : return "MipsISD::Hi";
41 case MipsISD::Lo : return "MipsISD::Lo";
42 case MipsISD::GPRel : return "MipsISD::GPRel";
43 case MipsISD::Ret : return "MipsISD::Ret";
44 case MipsISD::CMov : return "MipsISD::CMov";
45 case MipsISD::SelectCC : return "MipsISD::SelectCC";
46 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
47 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
48 case MipsISD::FPCmp : return "MipsISD::FPCmp";
49 case MipsISD::FPRound : return "MipsISD::FPRound";
50 default : return NULL;
55 MipsTargetLowering(MipsTargetMachine &TM)
56 : TargetLowering(TM, new MipsTargetObjectFile()) {
57 Subtarget = &TM.getSubtarget<MipsSubtarget>();
59 // Mips does not have i1 type, so use i32 for
60 // setcc operations results (slt, sgt, ...).
61 setBooleanContents(ZeroOrOneBooleanContent);
63 // JumpTable targets must use GOT when using PIC_
64 setUsesGlobalOffsetTable(true);
66 // Set up the register classes
67 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
68 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
70 // When dealing with single precision only, use libcalls
71 if (!Subtarget->isSingleFloat())
72 if (!Subtarget->isFP64bit())
73 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
76 addLegalFPImmediate(APFloat(+0.0f));
78 // Load extented operations for i1 types must be promoted
79 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
80 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
83 // MIPS doesn't have extending float->double load/store
84 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
85 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
87 // Used by legalize types to correctly generate the setcc result.
88 // Without this, every float setcc comes with a AND/OR with the result,
89 // we don't want this, since the fpcmp result goes to a flag register,
90 // which is used implicitly by brcond and select operations.
91 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
93 // Mips Custom Operations
94 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
95 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
96 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
97 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
98 setOperationAction(ISD::SELECT, MVT::f32, Custom);
99 setOperationAction(ISD::SELECT, MVT::f64, Custom);
100 setOperationAction(ISD::SELECT, MVT::i32, Custom);
101 setOperationAction(ISD::SETCC, MVT::f32, Custom);
102 setOperationAction(ISD::SETCC, MVT::f64, Custom);
103 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
104 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
105 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
107 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
108 // with operands comming from setcc fp comparions. This is necessary since
109 // the result from these setcc are in a flag registers (FCR31).
110 setOperationAction(ISD::AND, MVT::i32, Custom);
111 setOperationAction(ISD::OR, MVT::i32, Custom);
113 // Operations not directly supported by Mips.
114 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
115 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
116 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
117 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
118 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
120 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
121 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
122 setOperationAction(ISD::ROTL, MVT::i32, Expand);
123 setOperationAction(ISD::ROTR, MVT::i32, Expand);
124 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
125 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
126 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
127 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
128 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
129 setOperationAction(ISD::FSIN, MVT::f32, Expand);
130 setOperationAction(ISD::FCOS, MVT::f32, Expand);
131 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
132 setOperationAction(ISD::FPOW, MVT::f32, Expand);
133 setOperationAction(ISD::FLOG, MVT::f32, Expand);
134 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
135 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
136 setOperationAction(ISD::FEXP, MVT::f32, Expand);
138 // We don't have line number support yet.
139 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
140 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
141 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
142 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
144 // Use the default for now
145 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
146 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
147 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
149 if (Subtarget->isSingleFloat())
150 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
152 if (!Subtarget->hasSEInReg()) {
153 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
154 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
157 if (!Subtarget->hasBitCount())
158 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
160 if (!Subtarget->hasSwap())
161 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
163 setStackPointerRegisterToSaveRestore(Mips::SP);
164 computeRegisterProperties();
167 MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
171 /// getFunctionAlignment - Return the Log2 alignment of this function.
172 unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const {
176 SDValue MipsTargetLowering::
177 LowerOperation(SDValue Op, SelectionDAG &DAG)
179 switch (Op.getOpcode())
181 case ISD::AND: return LowerANDOR(Op, DAG);
182 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
183 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
184 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
185 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
186 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
187 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
188 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
189 case ISD::OR: return LowerANDOR(Op, DAG);
190 case ISD::SELECT: return LowerSELECT(Op, DAG);
191 case ISD::SETCC: return LowerSETCC(Op, DAG);
196 //===----------------------------------------------------------------------===//
197 // Lower helper functions
198 //===----------------------------------------------------------------------===//
200 // AddLiveIn - This helper function adds the specified physical register to the
201 // MachineFunction as a live in value. It also creates a corresponding
202 // virtual register for it.
204 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
206 assert(RC->contains(PReg) && "Not the correct regclass!");
207 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
208 MF.getRegInfo().addLiveIn(PReg, VReg);
212 // Get fp branch code (not opcode) from condition code.
213 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
214 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
215 return Mips::BRANCH_T;
217 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
218 return Mips::BRANCH_F;
220 return Mips::BRANCH_INVALID;
223 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
226 llvm_unreachable("Unknown branch code");
227 case Mips::BRANCH_T : return Mips::BC1T;
228 case Mips::BRANCH_F : return Mips::BC1F;
229 case Mips::BRANCH_TL : return Mips::BC1TL;
230 case Mips::BRANCH_FL : return Mips::BC1FL;
234 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
236 default: llvm_unreachable("Unknown fp condition code!");
238 case ISD::SETOEQ: return Mips::FCOND_EQ;
239 case ISD::SETUNE: return Mips::FCOND_OGL;
241 case ISD::SETOLT: return Mips::FCOND_OLT;
243 case ISD::SETOGT: return Mips::FCOND_OGT;
245 case ISD::SETOLE: return Mips::FCOND_OLE;
247 case ISD::SETOGE: return Mips::FCOND_OGE;
248 case ISD::SETULT: return Mips::FCOND_ULT;
249 case ISD::SETULE: return Mips::FCOND_ULE;
250 case ISD::SETUGT: return Mips::FCOND_UGT;
251 case ISD::SETUGE: return Mips::FCOND_UGE;
252 case ISD::SETUO: return Mips::FCOND_UN;
253 case ISD::SETO: return Mips::FCOND_OR;
255 case ISD::SETONE: return Mips::FCOND_NEQ;
256 case ISD::SETUEQ: return Mips::FCOND_UEQ;
261 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
262 MachineBasicBlock *BB) const {
263 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
264 bool isFPCmp = false;
265 DebugLoc dl = MI->getDebugLoc();
267 switch (MI->getOpcode()) {
268 default: assert(false && "Unexpected instr type to insert");
269 case Mips::Select_FCC:
270 case Mips::Select_FCC_S32:
271 case Mips::Select_FCC_D32:
272 isFPCmp = true; // FALL THROUGH
273 case Mips::Select_CC:
274 case Mips::Select_CC_S32:
275 case Mips::Select_CC_D32: {
276 // To "insert" a SELECT_CC instruction, we actually have to insert the
277 // diamond control-flow pattern. The incoming instruction knows the
278 // destination vreg to set, the condition code register to branch on, the
279 // true/false values to select between, and a branch opcode to use.
280 const BasicBlock *LLVM_BB = BB->getBasicBlock();
281 MachineFunction::iterator It = BB;
288 // bNE r1, r0, copy1MBB
289 // fallthrough --> copy0MBB
290 MachineBasicBlock *thisMBB = BB;
291 MachineFunction *F = BB->getParent();
292 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
293 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
295 // Emit the right instruction according to the type of the operands compared
297 // Find the condiction code present in the setcc operation.
298 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
299 // Get the branch opcode from the branch code.
300 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
301 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
303 BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
304 .addReg(Mips::ZERO).addMBB(sinkMBB);
306 F->insert(It, copy0MBB);
307 F->insert(It, sinkMBB);
308 // Update machine-CFG edges by first adding all successors of the current
309 // block to the new block which will contain the Phi node for the select.
310 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
311 e = BB->succ_end(); i != e; ++i)
312 sinkMBB->addSuccessor(*i);
313 // Next, remove all successors of the current block, and add the true
314 // and fallthrough blocks as its successors.
315 while(!BB->succ_empty())
316 BB->removeSuccessor(BB->succ_begin());
317 BB->addSuccessor(copy0MBB);
318 BB->addSuccessor(sinkMBB);
322 // # fallthrough to sinkMBB
325 // Update machine-CFG edges
326 BB->addSuccessor(sinkMBB);
329 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
332 BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg())
333 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
334 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
336 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
342 //===----------------------------------------------------------------------===//
343 // Misc Lower Operation implementation
344 //===----------------------------------------------------------------------===//
346 SDValue MipsTargetLowering::
347 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG)
349 if (!Subtarget->isMips1())
352 MachineFunction &MF = DAG.getMachineFunction();
353 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
355 SDValue Chain = DAG.getEntryNode();
356 DebugLoc dl = Op.getDebugLoc();
357 SDValue Src = Op.getOperand(0);
359 // Set the condition register
360 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
361 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
362 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
364 SDValue Cst = DAG.getConstant(3, MVT::i32);
365 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
366 Cst = DAG.getConstant(2, MVT::i32);
367 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
369 SDValue InFlag(0, 0);
370 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
372 // Emit the round instruction and bit convert to integer
373 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
374 Src, CondReg.getValue(1));
375 SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Trunc);
379 SDValue MipsTargetLowering::
380 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
382 SDValue Chain = Op.getOperand(0);
383 SDValue Size = Op.getOperand(1);
384 DebugLoc dl = Op.getDebugLoc();
386 // Get a reference from Mips stack pointer
387 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
389 // Subtract the dynamic size from the actual stack size to
390 // obtain the new stack size.
391 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
393 // The Sub result contains the new stack start address, so it
394 // must be placed in the stack pointer register.
395 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
397 // This node always has two return values: a new stack pointer
399 SDValue Ops[2] = { Sub, Chain };
400 return DAG.getMergeValues(Ops, 2, dl);
403 SDValue MipsTargetLowering::
404 LowerANDOR(SDValue Op, SelectionDAG &DAG)
406 SDValue LHS = Op.getOperand(0);
407 SDValue RHS = Op.getOperand(1);
408 DebugLoc dl = Op.getDebugLoc();
410 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
413 SDValue True = DAG.getConstant(1, MVT::i32);
414 SDValue False = DAG.getConstant(0, MVT::i32);
416 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
417 LHS, True, False, LHS.getOperand(2));
418 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
419 RHS, True, False, RHS.getOperand(2));
421 return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
424 SDValue MipsTargetLowering::
425 LowerBRCOND(SDValue Op, SelectionDAG &DAG)
427 // The first operand is the chain, the second is the condition, the third is
428 // the block to branch to if the condition is true.
429 SDValue Chain = Op.getOperand(0);
430 SDValue Dest = Op.getOperand(2);
431 DebugLoc dl = Op.getDebugLoc();
433 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
436 SDValue CondRes = Op.getOperand(1);
437 SDValue CCNode = CondRes.getOperand(2);
439 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
440 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
442 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
446 SDValue MipsTargetLowering::
447 LowerSETCC(SDValue Op, SelectionDAG &DAG)
449 // The operands to this are the left and right operands to compare (ops #0,
450 // and #1) and the condition code to compare them with (op #2) as a
452 SDValue LHS = Op.getOperand(0);
453 SDValue RHS = Op.getOperand(1);
454 DebugLoc dl = Op.getDebugLoc();
456 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
458 return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
459 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
462 SDValue MipsTargetLowering::
463 LowerSELECT(SDValue Op, SelectionDAG &DAG)
465 SDValue Cond = Op.getOperand(0);
466 SDValue True = Op.getOperand(1);
467 SDValue False = Op.getOperand(2);
468 DebugLoc dl = Op.getDebugLoc();
470 // if the incomming condition comes from a integer compare, the select
471 // operation must be SelectCC or a conditional move if the subtarget
473 if (Cond.getOpcode() != MipsISD::FPCmp) {
474 if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
476 return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(),
480 // if the incomming condition comes from fpcmp, the select
481 // operation must use FPSelectCC.
482 SDValue CCNode = Cond.getOperand(2);
483 return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
484 Cond, True, False, CCNode);
487 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
488 // FIXME there isn't actually debug info here
489 DebugLoc dl = Op.getDebugLoc();
490 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
491 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
493 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
494 SDVTList VTs = DAG.getVTList(MVT::i32);
496 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
498 // %gp_rel relocation
499 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
500 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
501 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
502 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
504 // %hi/%lo relocation
505 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GA, 1);
506 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
507 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
509 } else { // Abicall relocations, TODO: make this cleaner.
510 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
511 DAG.getEntryNode(), GA, NULL, 0);
512 // On functions and global targets not internal linked only
513 // a load from got/GP is necessary for PIC to work.
514 if (!GV->hasLocalLinkage() || isa<Function>(GV))
516 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
517 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
520 llvm_unreachable("Dont know how to handle GlobalAddress");
524 SDValue MipsTargetLowering::
525 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
527 llvm_unreachable("TLS not implemented for MIPS.");
528 return SDValue(); // Not reached
531 SDValue MipsTargetLowering::
532 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
536 // FIXME there isn't actually debug info here
537 DebugLoc dl = Op.getDebugLoc();
539 EVT PtrVT = Op.getValueType();
540 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
541 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
543 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
544 SDVTList VTs = DAG.getVTList(MVT::i32);
545 SDValue Ops[] = { JTI };
546 HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1);
547 } else // Emit Load from Global Pointer
548 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
550 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
551 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
556 SDValue MipsTargetLowering::
557 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
560 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
561 Constant *C = N->getConstVal();
562 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
563 // FIXME there isn't actually debug info here
564 DebugLoc dl = Op.getDebugLoc();
567 // FIXME: we should reference the constant pool using small data sections,
568 // but the asm printer currently doens't support this feature without
569 // hacking it. This feature should come soon so we can uncomment the
571 //if (IsInSmallSection(C->getType())) {
572 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
573 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
574 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
575 //} else { // %hi/%lo relocation
576 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
577 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
578 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
584 //===----------------------------------------------------------------------===//
585 // Calling Convention Implementation
586 //===----------------------------------------------------------------------===//
588 #include "MipsGenCallingConv.inc"
590 //===----------------------------------------------------------------------===//
591 // TODO: Implement a generic logic using tblgen that can support this.
592 // Mips O32 ABI rules:
594 // i32 - Passed in A0, A1, A2, A3 and stack
595 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
596 // an argument. Otherwise, passed in A1, A2, A3 and stack.
597 // f64 - Only passed in two aliased f32 registers if no int reg has been used
598 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
599 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
601 //===----------------------------------------------------------------------===//
603 static bool CC_MipsO32(unsigned ValNo, EVT ValVT,
604 EVT LocVT, CCValAssign::LocInfo LocInfo,
605 ISD::ArgFlagsTy ArgFlags, CCState &State) {
607 static const unsigned IntRegsSize=4, FloatRegsSize=2;
609 static const unsigned IntRegs[] = {
610 Mips::A0, Mips::A1, Mips::A2, Mips::A3
612 static const unsigned F32Regs[] = {
615 static const unsigned F64Regs[] = {
620 unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
621 bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0)));
623 // Promote i8 and i16
624 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
626 if (ArgFlags.isSExt())
627 LocInfo = CCValAssign::SExt;
628 else if (ArgFlags.isZExt())
629 LocInfo = CCValAssign::ZExt;
631 LocInfo = CCValAssign::AExt;
634 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) {
635 Reg = State.AllocateReg(IntRegs, IntRegsSize);
640 if (ValVT.isFloatingPoint() && !IntRegUsed) {
641 if (ValVT == MVT::f32)
642 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
644 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
647 if (ValVT == MVT::f64 && IntRegUsed) {
648 if (UnallocIntReg != IntRegsSize) {
649 // If we hit register A3 as the first not allocated, we must
650 // mark it as allocated (shadow) and use the stack instead.
651 if (IntRegs[UnallocIntReg] != (unsigned (Mips::A3)))
653 for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg)
654 State.AllocateReg(UnallocIntReg);
660 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
661 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
662 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
664 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
666 return false; // CC must always match
669 //===----------------------------------------------------------------------===//
670 // Call Calling Convention Implementation
671 //===----------------------------------------------------------------------===//
673 /// LowerCall - functions arguments are copied from virtual regs to
674 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
675 /// TODO: isVarArg, isTailCall.
677 MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
678 unsigned CallConv, bool isVarArg,
680 const SmallVectorImpl<ISD::OutputArg> &Outs,
681 const SmallVectorImpl<ISD::InputArg> &Ins,
682 DebugLoc dl, SelectionDAG &DAG,
683 SmallVectorImpl<SDValue> &InVals) {
685 MachineFunction &MF = DAG.getMachineFunction();
686 MachineFrameInfo *MFI = MF.getFrameInfo();
688 // Analyze operands of the call, assigning locations to each operand.
689 SmallVector<CCValAssign, 16> ArgLocs;
690 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
693 // To meet O32 ABI, Mips must always allocate 16 bytes on
694 // the stack (even if less than 4 are used as arguments)
695 if (Subtarget->isABI_O32()) {
696 int VTsize = EVT(MVT::i32).getSizeInBits()/8;
697 MFI->CreateFixedObject(VTsize, (VTsize*3));
698 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
700 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
702 // Get a count of how many bytes are to be pushed on the stack.
703 unsigned NumBytes = CCInfo.getNextStackOffset();
704 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
706 // With EABI is it possible to have 16 args on registers.
707 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
708 SmallVector<SDValue, 8> MemOpChains;
710 // First/LastArgStackLoc contains the first/last
711 // "at stack" argument location.
712 int LastArgStackLoc = 0;
713 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
715 // Walk the register/memloc assignments, inserting copies/loads.
716 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
717 SDValue Arg = Outs[i].Val;
718 CCValAssign &VA = ArgLocs[i];
720 // Promote the value if needed.
721 switch (VA.getLocInfo()) {
722 default: llvm_unreachable("Unknown loc info!");
723 case CCValAssign::Full:
724 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
725 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
726 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg);
727 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
728 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
729 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
730 DAG.getConstant(0, getPointerTy()));
731 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
732 DAG.getConstant(1, getPointerTy()));
733 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
734 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
739 case CCValAssign::SExt:
740 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
742 case CCValAssign::ZExt:
743 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
745 case CCValAssign::AExt:
746 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
750 // Arguments that can be passed on register must be kept at
753 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
757 // Register can't get to this point...
758 assert(VA.isMemLoc());
760 // Create the frame index object for this incoming parameter
761 // This guarantees that when allocating Local Area the firsts
762 // 16 bytes which are alwayes reserved won't be overwritten
763 // if O32 ABI is used. For EABI the first address is zero.
764 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
765 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
768 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
770 // emit ISD::STORE whichs stores the
771 // parameter value to a stack Location
772 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
775 // Transform all store nodes into one single node because all store
776 // nodes are independent of each other.
777 if (!MemOpChains.empty())
778 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
779 &MemOpChains[0], MemOpChains.size());
781 // Build a sequence of copy-to-reg nodes chained together with token
782 // chain and flag operands which copy the outgoing args into registers.
783 // The InFlag in necessary since all emited instructions must be
786 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
787 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
788 RegsToPass[i].second, InFlag);
789 InFlag = Chain.getValue(1);
792 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
793 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
794 // node so that legalize doesn't hack it.
795 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
796 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
797 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
798 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
800 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
801 // = Chain, Callee, Reg#1, Reg#2, ...
803 // Returns a chain & a flag for retval copy to use.
804 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
805 SmallVector<SDValue, 8> Ops;
806 Ops.push_back(Chain);
807 Ops.push_back(Callee);
809 // Add argument registers to the end of the list so that they are
810 // known live into the call.
811 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
812 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
813 RegsToPass[i].second.getValueType()));
815 if (InFlag.getNode())
816 Ops.push_back(InFlag);
818 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
819 InFlag = Chain.getValue(1);
821 // Create the CALLSEQ_END node.
822 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
823 DAG.getIntPtrConstant(0, true), InFlag);
824 InFlag = Chain.getValue(1);
826 // Create a stack location to hold GP when PIC is used. This stack
827 // location is used on function prologue to save GP and also after all
828 // emited CALL's to restore GP.
829 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
830 // Function can have an arbitrary number of calls, so
831 // hold the LastArgStackLoc with the biggest offset.
833 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
834 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
835 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
836 // Create the frame index only once. SPOffset here can be anything
837 // (this will be fixed on processFunctionBeforeFrameFinalized)
838 if (MipsFI->getGPStackOffset() == -1) {
839 FI = MFI->CreateFixedObject(4, 0);
842 MipsFI->setGPStackOffset(LastArgStackLoc);
846 FI = MipsFI->getGPFI();
847 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
848 SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0);
849 Chain = GPLoad.getValue(1);
850 Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
851 GPLoad, SDValue(0,0));
852 InFlag = Chain.getValue(1);
855 // Handle result values, copying them out of physregs into vregs that we
857 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
858 Ins, dl, DAG, InVals);
861 /// LowerCallResult - Lower the result values of a call into the
862 /// appropriate copies out of appropriate physical registers.
864 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
865 unsigned CallConv, bool isVarArg,
866 const SmallVectorImpl<ISD::InputArg> &Ins,
867 DebugLoc dl, SelectionDAG &DAG,
868 SmallVectorImpl<SDValue> &InVals) {
870 // Assign locations to each value returned by this call.
871 SmallVector<CCValAssign, 16> RVLocs;
872 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
873 RVLocs, *DAG.getContext());
875 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
877 // Copy all of the result registers out of their specified physreg.
878 for (unsigned i = 0; i != RVLocs.size(); ++i) {
879 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
880 RVLocs[i].getValVT(), InFlag).getValue(1);
881 InFlag = Chain.getValue(2);
882 InVals.push_back(Chain.getValue(0));
888 //===----------------------------------------------------------------------===//
889 // Formal Arguments Calling Convention Implementation
890 //===----------------------------------------------------------------------===//
892 /// LowerFormalArguments - transform physical registers into
893 /// virtual registers and generate load operations for
894 /// arguments places on the stack.
897 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
898 unsigned CallConv, bool isVarArg,
899 const SmallVectorImpl<ISD::InputArg>
901 DebugLoc dl, SelectionDAG &DAG,
902 SmallVectorImpl<SDValue> &InVals) {
904 MachineFunction &MF = DAG.getMachineFunction();
905 MachineFrameInfo *MFI = MF.getFrameInfo();
906 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
908 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
910 // Assign locations to all of the incoming arguments.
911 SmallVector<CCValAssign, 16> ArgLocs;
912 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
913 ArgLocs, *DAG.getContext());
915 if (Subtarget->isABI_O32())
916 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
918 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
922 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
924 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
925 CCValAssign &VA = ArgLocs[i];
927 // Arguments stored on registers
929 EVT RegVT = VA.getLocVT();
930 TargetRegisterClass *RC = 0;
932 if (RegVT == MVT::i32)
933 RC = Mips::CPURegsRegisterClass;
934 else if (RegVT == MVT::f32)
935 RC = Mips::FGR32RegisterClass;
936 else if (RegVT == MVT::f64) {
937 if (!Subtarget->isSingleFloat())
938 RC = Mips::AFGR64RegisterClass;
940 llvm_unreachable("RegVT not supported by LowerFormalArguments Lowering");
942 // Transform the arguments stored on
943 // physical registers into virtual ones
944 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
945 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
947 // If this is an 8 or 16-bit value, it has been passed promoted
948 // to 32 bits. Insert an assert[sz]ext to capture this, then
949 // truncate to the right size.
950 if (VA.getLocInfo() != CCValAssign::Full) {
952 if (VA.getLocInfo() == CCValAssign::SExt)
953 Opcode = ISD::AssertSext;
954 else if (VA.getLocInfo() == CCValAssign::ZExt)
955 Opcode = ISD::AssertZext;
957 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
958 DAG.getValueType(VA.getValVT()));
959 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
962 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
963 if (Subtarget->isABI_O32()) {
964 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
965 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
966 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
967 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
968 VA.getLocReg()+1, RC);
969 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
970 SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
971 SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2);
972 ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi);
976 InVals.push_back(ArgValue);
978 // To meet ABI, when VARARGS are passed on registers, the registers
979 // must have their values written to the caller stack frame.
980 if ((isVarArg) && (Subtarget->isABI_O32())) {
981 if (StackPtr.getNode() == 0)
982 StackPtr = DAG.getRegister(StackReg, getPointerTy());
984 // The stack pointer offset is relative to the caller stack frame.
985 // Since the real stack size is unknown here, a negative SPOffset
986 // is used so there's a way to adjust these offsets when the stack
987 // size get known (on EliminateFrameIndex). A dummy SPOffset is
988 // used instead of a direct negative address (which is recorded to
989 // be used on emitPrologue) to avoid mis-calc of the first stack
990 // offset on PEI::calculateFrameObjectOffsets.
991 // Arguments are always 32-bit.
992 int FI = MFI->CreateFixedObject(4, 0);
993 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
994 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
996 // emit ISD::STORE whichs stores the
997 // parameter value to a stack Location
998 InVals.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, NULL, 0));
1001 } else { // VA.isRegLoc()
1004 assert(VA.isMemLoc());
1006 // The stack pointer offset is relative to the caller stack frame.
1007 // Since the real stack size is unknown here, a negative SPOffset
1008 // is used so there's a way to adjust these offsets when the stack
1009 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1010 // used instead of a direct negative address (which is recorded to
1011 // be used on emitPrologue) to avoid mis-calc of the first stack
1012 // offset on PEI::calculateFrameObjectOffsets.
1013 // Arguments are always 32-bit.
1014 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1015 int FI = MFI->CreateFixedObject(ArgSize, 0);
1016 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
1017 (FirstStackArgLoc + VA.getLocMemOffset())));
1019 // Create load nodes to retrieve arguments from the stack
1020 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1021 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
1025 // The mips ABIs for returning structs by value requires that we copy
1026 // the sret argument into $v0 for the return. Save the argument into
1027 // a virtual register so that we can access it from the return points.
1028 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1029 unsigned Reg = MipsFI->getSRetReturnReg();
1031 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1032 MipsFI->setSRetReturnReg(Reg);
1034 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1035 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1041 //===----------------------------------------------------------------------===//
1042 // Return Value Calling Convention Implementation
1043 //===----------------------------------------------------------------------===//
1046 MipsTargetLowering::LowerReturn(SDValue Chain,
1047 unsigned CallConv, bool isVarArg,
1048 const SmallVectorImpl<ISD::OutputArg> &Outs,
1049 DebugLoc dl, SelectionDAG &DAG) {
1051 // CCValAssign - represent the assignment of
1052 // the return value to a location
1053 SmallVector<CCValAssign, 16> RVLocs;
1055 // CCState - Info about the registers and stack slot.
1056 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1057 RVLocs, *DAG.getContext());
1059 // Analize return values.
1060 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
1062 // If this is the first return lowered for this function, add
1063 // the regs to the liveout set for the function.
1064 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1065 for (unsigned i = 0; i != RVLocs.size(); ++i)
1066 if (RVLocs[i].isRegLoc())
1067 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1072 // Copy the result values into the output registers.
1073 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1074 CCValAssign &VA = RVLocs[i];
1075 assert(VA.isRegLoc() && "Can only return in registers!");
1077 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1080 // guarantee that all emitted copies are
1081 // stuck together, avoiding something bad
1082 Flag = Chain.getValue(1);
1085 // The mips ABIs for returning structs by value requires that we copy
1086 // the sret argument into $v0 for the return. We saved the argument into
1087 // a virtual register in the entry block, so now we copy the value out
1089 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1090 MachineFunction &MF = DAG.getMachineFunction();
1091 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1092 unsigned Reg = MipsFI->getSRetReturnReg();
1095 llvm_unreachable("sret virtual register not created in the entry block");
1096 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1098 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1099 Flag = Chain.getValue(1);
1102 // Return on Mips is always a "jr $ra"
1104 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1105 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1107 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1108 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1111 //===----------------------------------------------------------------------===//
1112 // Mips Inline Assembly Support
1113 //===----------------------------------------------------------------------===//
1115 /// getConstraintType - Given a constraint letter, return the type of
1116 /// constraint it is for this target.
1117 MipsTargetLowering::ConstraintType MipsTargetLowering::
1118 getConstraintType(const std::string &Constraint) const
1120 // Mips specific constrainy
1121 // GCC config/mips/constraints.md
1123 // 'd' : An address register. Equivalent to r
1124 // unless generating MIPS16 code.
1125 // 'y' : Equivalent to r; retained for
1126 // backwards compatibility.
1127 // 'f' : Floating Point registers.
1128 if (Constraint.size() == 1) {
1129 switch (Constraint[0]) {
1134 return C_RegisterClass;
1138 return TargetLowering::getConstraintType(Constraint);
1141 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1142 /// return a list of registers that can be used to satisfy the constraint.
1143 /// This should only be used for C_RegisterClass constraints.
1144 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1145 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
1147 if (Constraint.size() == 1) {
1148 switch (Constraint[0]) {
1150 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1153 return std::make_pair(0U, Mips::FGR32RegisterClass);
1155 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1156 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1159 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1162 /// Given a register class constraint, like 'r', if this corresponds directly
1163 /// to an LLVM register class, return a register of 0 and the register class
1165 std::vector<unsigned> MipsTargetLowering::
1166 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1169 if (Constraint.size() != 1)
1170 return std::vector<unsigned>();
1172 switch (Constraint[0]) {
1175 // GCC Mips Constraint Letters
1178 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1179 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1180 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1184 if (VT == MVT::f32) {
1185 if (Subtarget->isSingleFloat())
1186 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1187 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1188 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1189 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1190 Mips::F30, Mips::F31, 0);
1192 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1193 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1194 Mips::F28, Mips::F30, 0);
1198 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1199 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1200 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1201 Mips::D14, Mips::D15, 0);
1203 return std::vector<unsigned>();
1207 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1208 // The Mips target isn't yet aware of offsets.