1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-lower"
16 #include "MipsISelLowering.h"
17 #include "InstPrinter/MipsInstPrinter.h"
18 #include "MCTargetDesc/MipsBaseInfo.h"
19 #include "MipsMachineFunction.h"
20 #include "MipsSubtarget.h"
21 #include "MipsTargetMachine.h"
22 #include "MipsTargetObjectFile.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/CodeGen/ValueTypes.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/GlobalVariable.h"
35 #include "llvm/IR/Intrinsics.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumTailCalls, "Number of tail calls");
46 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
47 cl::desc("MIPS: Enable tail calls."), cl::init(false));
50 LargeGOT("mxgot", cl::Hidden,
51 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
54 Mips16HardFloat("mips16-hard-float", cl::NotHidden,
55 cl::desc("MIPS: mips16 hard float enable."),
58 static cl::opt<bool> DontExpandCondPseudos16(
59 "mips16-dont-expand-cond-pseudo",
61 cl::desc("Dont expand conditional move related "
62 "pseudos for Mips 16"),
66 static const uint16_t O32IntRegs[4] = {
67 Mips::A0, Mips::A1, Mips::A2, Mips::A3
70 static const uint16_t Mips64IntRegs[8] = {
71 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
72 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
75 static const uint16_t Mips64DPRegs[8] = {
76 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
77 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
80 // If I is a shifted mask, set the size (Size) and the first bit of the
81 // mask (Pos), and return true.
82 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
83 static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
84 if (!isShiftedMask_64(I))
87 Size = CountPopulation_64(I);
88 Pos = CountTrailingZeros_64(I);
92 static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) {
93 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
94 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
97 static SDValue getTargetNode(SDValue Op, SelectionDAG &DAG, unsigned Flag) {
98 EVT Ty = Op.getValueType();
100 if (GlobalAddressSDNode *N = dyn_cast<GlobalAddressSDNode>(Op))
101 return DAG.getTargetGlobalAddress(N->getGlobal(), Op.getDebugLoc(), Ty, 0,
103 if (ExternalSymbolSDNode *N = dyn_cast<ExternalSymbolSDNode>(Op))
104 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
105 if (BlockAddressSDNode *N = dyn_cast<BlockAddressSDNode>(Op))
106 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
107 if (JumpTableSDNode *N = dyn_cast<JumpTableSDNode>(Op))
108 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
109 if (ConstantPoolSDNode *N = dyn_cast<ConstantPoolSDNode>(Op))
110 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
111 N->getOffset(), Flag);
113 llvm_unreachable("Unexpected node type.");
117 static SDValue getAddrNonPIC(SDValue Op, SelectionDAG &DAG) {
118 DebugLoc DL = Op.getDebugLoc();
119 EVT Ty = Op.getValueType();
120 SDValue Hi = getTargetNode(Op, DAG, MipsII::MO_ABS_HI);
121 SDValue Lo = getTargetNode(Op, DAG, MipsII::MO_ABS_LO);
122 return DAG.getNode(ISD::ADD, DL, Ty,
123 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
124 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
127 static SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) {
128 DebugLoc DL = Op.getDebugLoc();
129 EVT Ty = Op.getValueType();
130 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
131 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, GetGlobalReg(DAG, Ty),
132 getTargetNode(Op, DAG, GOTFlag));
133 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
134 MachinePointerInfo::getGOT(), false, false, false,
136 unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
137 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, getTargetNode(Op, DAG, LoFlag));
138 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
141 static SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) {
142 DebugLoc DL = Op.getDebugLoc();
143 EVT Ty = Op.getValueType();
144 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, GetGlobalReg(DAG, Ty),
145 getTargetNode(Op, DAG, Flag));
146 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Tgt,
147 MachinePointerInfo::getGOT(), false, false, false, 0);
150 static SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
151 unsigned HiFlag, unsigned LoFlag) {
152 DebugLoc DL = Op.getDebugLoc();
153 EVT Ty = Op.getValueType();
154 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(Op, DAG, HiFlag));
155 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, GetGlobalReg(DAG, Ty));
156 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
157 getTargetNode(Op, DAG, LoFlag));
158 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Wrapper,
159 MachinePointerInfo::getGOT(), false, false, false, 0);
162 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
164 case MipsISD::JmpLink: return "MipsISD::JmpLink";
165 case MipsISD::TailCall: return "MipsISD::TailCall";
166 case MipsISD::Hi: return "MipsISD::Hi";
167 case MipsISD::Lo: return "MipsISD::Lo";
168 case MipsISD::GPRel: return "MipsISD::GPRel";
169 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
170 case MipsISD::Ret: return "MipsISD::Ret";
171 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
172 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
173 case MipsISD::FPCmp: return "MipsISD::FPCmp";
174 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
175 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
176 case MipsISD::FPRound: return "MipsISD::FPRound";
177 case MipsISD::MAdd: return "MipsISD::MAdd";
178 case MipsISD::MAddu: return "MipsISD::MAddu";
179 case MipsISD::MSub: return "MipsISD::MSub";
180 case MipsISD::MSubu: return "MipsISD::MSubu";
181 case MipsISD::DivRem: return "MipsISD::DivRem";
182 case MipsISD::DivRemU: return "MipsISD::DivRemU";
183 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
184 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
185 case MipsISD::Wrapper: return "MipsISD::Wrapper";
186 case MipsISD::Sync: return "MipsISD::Sync";
187 case MipsISD::Ext: return "MipsISD::Ext";
188 case MipsISD::Ins: return "MipsISD::Ins";
189 case MipsISD::LWL: return "MipsISD::LWL";
190 case MipsISD::LWR: return "MipsISD::LWR";
191 case MipsISD::SWL: return "MipsISD::SWL";
192 case MipsISD::SWR: return "MipsISD::SWR";
193 case MipsISD::LDL: return "MipsISD::LDL";
194 case MipsISD::LDR: return "MipsISD::LDR";
195 case MipsISD::SDL: return "MipsISD::SDL";
196 case MipsISD::SDR: return "MipsISD::SDR";
197 case MipsISD::EXTP: return "MipsISD::EXTP";
198 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
199 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
200 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
201 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
202 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
203 case MipsISD::SHILO: return "MipsISD::SHILO";
204 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
205 case MipsISD::MULT: return "MipsISD::MULT";
206 case MipsISD::MULTU: return "MipsISD::MULTU";
207 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSPDSP";
208 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
209 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
210 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
211 default: return NULL;
217 bool operator()(const char *s1, const char *s2) const
219 return strcmp(s1, s2) < 0;
223 std::set<const char*, ltstr> noHelperNeeded;
226 void MipsTargetLowering::SetMips16LibcallName
227 (RTLIB::Libcall l, const char *Name) {
228 setLibcallName(l, Name);
229 noHelperNeeded.insert(Name);
232 void MipsTargetLowering::setMips16HardFloatLibCalls() {
233 SetMips16LibcallName(RTLIB::ADD_F32, "__mips16_addsf3");
234 SetMips16LibcallName(RTLIB::ADD_F64, "__mips16_adddf3");
235 SetMips16LibcallName(RTLIB::SUB_F32, "__mips16_subsf3");
236 SetMips16LibcallName(RTLIB::SUB_F64, "__mips16_subdf3");
237 SetMips16LibcallName(RTLIB::MUL_F32, "__mips16_mulsf3");
238 SetMips16LibcallName(RTLIB::MUL_F64, "__mips16_muldf3");
239 SetMips16LibcallName(RTLIB::DIV_F32, "__mips16_divsf3");
240 SetMips16LibcallName(RTLIB::DIV_F64, "__mips16_divdf3");
241 SetMips16LibcallName(RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2");
242 SetMips16LibcallName(RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2");
243 SetMips16LibcallName(RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi");
244 SetMips16LibcallName(RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi");
245 SetMips16LibcallName(RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf");
246 SetMips16LibcallName(RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf");
247 SetMips16LibcallName(RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf");
248 SetMips16LibcallName(RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf");
249 SetMips16LibcallName(RTLIB::OEQ_F32, "__mips16_eqsf2");
250 SetMips16LibcallName(RTLIB::OEQ_F64, "__mips16_eqdf2");
251 SetMips16LibcallName(RTLIB::UNE_F32, "__mips16_nesf2");
252 SetMips16LibcallName(RTLIB::UNE_F64, "__mips16_nedf2");
253 SetMips16LibcallName(RTLIB::OGE_F32, "__mips16_gesf2");
254 SetMips16LibcallName(RTLIB::OGE_F64, "__mips16_gedf2");
255 SetMips16LibcallName(RTLIB::OLT_F32, "__mips16_ltsf2");
256 SetMips16LibcallName(RTLIB::OLT_F64, "__mips16_ltdf2");
257 SetMips16LibcallName(RTLIB::OLE_F32, "__mips16_lesf2");
258 SetMips16LibcallName(RTLIB::OLE_F64, "__mips16_ledf2");
259 SetMips16LibcallName(RTLIB::OGT_F32, "__mips16_gtsf2");
260 SetMips16LibcallName(RTLIB::OGT_F64, "__mips16_gtdf2");
261 SetMips16LibcallName(RTLIB::UO_F32, "__mips16_unordsf2");
262 SetMips16LibcallName(RTLIB::UO_F64, "__mips16_unorddf2");
263 SetMips16LibcallName(RTLIB::O_F32, "__mips16_unordsf2");
264 SetMips16LibcallName(RTLIB::O_F64, "__mips16_unorddf2");
268 MipsTargetLowering(MipsTargetMachine &TM)
269 : TargetLowering(TM, new MipsTargetObjectFile()),
270 Subtarget(&TM.getSubtarget<MipsSubtarget>()),
271 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
272 IsO32(Subtarget->isABI_O32()) {
274 // Mips does not have i1 type, so use i32 for
275 // setcc operations results (slt, sgt, ...).
276 setBooleanContents(ZeroOrOneBooleanContent);
277 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
279 // Set up the register classes
280 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
283 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
285 if (Subtarget->inMips16Mode()) {
286 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
288 setMips16HardFloatLibCalls();
291 if (Subtarget->hasDSP()) {
292 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
294 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
295 addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass);
297 // Expand all builtin opcodes.
298 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
299 setOperationAction(Opc, VecTys[i], Expand);
301 setOperationAction(ISD::LOAD, VecTys[i], Legal);
302 setOperationAction(ISD::STORE, VecTys[i], Legal);
303 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
307 if (!TM.Options.UseSoftFloat) {
308 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
310 // When dealing with single precision only, use libcalls
311 if (!Subtarget->isSingleFloat()) {
313 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
315 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
319 // Load extented operations for i1 types must be promoted
320 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
321 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
322 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
324 // MIPS doesn't have extending float->double load/store
325 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
326 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
328 // Used by legalize types to correctly generate the setcc result.
329 // Without this, every float setcc comes with a AND/OR with the result,
330 // we don't want this, since the fpcmp result goes to a flag register,
331 // which is used implicitly by brcond and select operations.
332 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
334 // Mips Custom Operations
335 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
336 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
337 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
338 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
339 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
340 setOperationAction(ISD::SELECT, MVT::f32, Custom);
341 setOperationAction(ISD::SELECT, MVT::f64, Custom);
342 setOperationAction(ISD::SELECT, MVT::i32, Custom);
343 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
344 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
345 setOperationAction(ISD::SETCC, MVT::f32, Custom);
346 setOperationAction(ISD::SETCC, MVT::f64, Custom);
347 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
348 setOperationAction(ISD::VASTART, MVT::Other, Custom);
349 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
350 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
351 if (Subtarget->inMips16Mode()) {
352 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
353 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
356 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
357 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
359 if (!Subtarget->inMips16Mode()) {
360 setOperationAction(ISD::LOAD, MVT::i32, Custom);
361 setOperationAction(ISD::STORE, MVT::i32, Custom);
364 if (!TM.Options.NoNaNsFPMath) {
365 setOperationAction(ISD::FABS, MVT::f32, Custom);
366 setOperationAction(ISD::FABS, MVT::f64, Custom);
370 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
371 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
372 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
373 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
374 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
375 setOperationAction(ISD::SELECT, MVT::i64, Custom);
376 setOperationAction(ISD::LOAD, MVT::i64, Custom);
377 setOperationAction(ISD::STORE, MVT::i64, Custom);
381 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
382 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
383 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
386 setOperationAction(ISD::ADD, MVT::i32, Custom);
388 setOperationAction(ISD::ADD, MVT::i64, Custom);
390 setOperationAction(ISD::SDIV, MVT::i32, Expand);
391 setOperationAction(ISD::SREM, MVT::i32, Expand);
392 setOperationAction(ISD::UDIV, MVT::i32, Expand);
393 setOperationAction(ISD::UREM, MVT::i32, Expand);
394 setOperationAction(ISD::SDIV, MVT::i64, Expand);
395 setOperationAction(ISD::SREM, MVT::i64, Expand);
396 setOperationAction(ISD::UDIV, MVT::i64, Expand);
397 setOperationAction(ISD::UREM, MVT::i64, Expand);
399 // Operations not directly supported by Mips.
400 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
401 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
402 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
403 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
404 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
405 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
406 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
407 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
408 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
409 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
410 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
411 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
412 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
413 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
415 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
416 setOperationAction(ISD::ROTL, MVT::i32, Expand);
417 setOperationAction(ISD::ROTL, MVT::i64, Expand);
418 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
419 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
421 if (!Subtarget->hasMips32r2())
422 setOperationAction(ISD::ROTR, MVT::i32, Expand);
424 if (!Subtarget->hasMips64r2())
425 setOperationAction(ISD::ROTR, MVT::i64, Expand);
427 setOperationAction(ISD::FSIN, MVT::f32, Expand);
428 setOperationAction(ISD::FSIN, MVT::f64, Expand);
429 setOperationAction(ISD::FCOS, MVT::f32, Expand);
430 setOperationAction(ISD::FCOS, MVT::f64, Expand);
431 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
432 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
433 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
434 setOperationAction(ISD::FPOW, MVT::f32, Expand);
435 setOperationAction(ISD::FPOW, MVT::f64, Expand);
436 setOperationAction(ISD::FLOG, MVT::f32, Expand);
437 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
438 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
439 setOperationAction(ISD::FEXP, MVT::f32, Expand);
440 setOperationAction(ISD::FMA, MVT::f32, Expand);
441 setOperationAction(ISD::FMA, MVT::f64, Expand);
442 setOperationAction(ISD::FREM, MVT::f32, Expand);
443 setOperationAction(ISD::FREM, MVT::f64, Expand);
445 if (!TM.Options.NoNaNsFPMath) {
446 setOperationAction(ISD::FNEG, MVT::f32, Expand);
447 setOperationAction(ISD::FNEG, MVT::f64, Expand);
450 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
451 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
452 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
453 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
455 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
457 setOperationAction(ISD::VAARG, MVT::Other, Expand);
458 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
459 setOperationAction(ISD::VAEND, MVT::Other, Expand);
461 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
462 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
464 // Use the default for now
465 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
466 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
468 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
469 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
470 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
471 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
473 if (Subtarget->inMips16Mode()) {
474 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
475 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
476 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
477 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
478 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
479 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
480 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
481 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
482 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
483 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
484 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
485 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
488 setInsertFencesForAtomic(true);
490 if (!Subtarget->hasSEInReg()) {
491 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
492 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
495 if (!Subtarget->hasBitCount()) {
496 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
497 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
500 if (!Subtarget->hasSwap()) {
501 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
502 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
506 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
507 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
508 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
509 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
512 setTargetDAGCombine(ISD::ADDE);
513 setTargetDAGCombine(ISD::SUBE);
514 setTargetDAGCombine(ISD::SDIVREM);
515 setTargetDAGCombine(ISD::UDIVREM);
516 setTargetDAGCombine(ISD::SELECT);
517 setTargetDAGCombine(ISD::AND);
518 setTargetDAGCombine(ISD::OR);
519 setTargetDAGCombine(ISD::ADD);
521 setMinFunctionAlignment(HasMips64 ? 3 : 2);
523 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
524 computeRegisterProperties();
526 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
527 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
529 MaxStoresPerMemcpy = 16;
533 MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
534 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
536 if (Subtarget->inMips16Mode())
550 EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
553 return VT.changeVectorElementTypeToInteger();
557 // Transforms a subgraph in CurDAG if the following pattern is found:
558 // (addc multLo, Lo0), (adde multHi, Hi0),
560 // multHi/Lo: product of multiplication
561 // Lo0: initial value of Lo register
562 // Hi0: initial value of Hi register
563 // Return true if pattern matching was successful.
564 static bool SelectMadd(SDNode *ADDENode, SelectionDAG *CurDAG) {
565 // ADDENode's second operand must be a flag output of an ADDC node in order
566 // for the matching to be successful.
567 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
569 if (ADDCNode->getOpcode() != ISD::ADDC)
572 SDValue MultHi = ADDENode->getOperand(0);
573 SDValue MultLo = ADDCNode->getOperand(0);
574 SDNode *MultNode = MultHi.getNode();
575 unsigned MultOpc = MultHi.getOpcode();
577 // MultHi and MultLo must be generated by the same node,
578 if (MultLo.getNode() != MultNode)
581 // and it must be a multiplication.
582 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
585 // MultLo amd MultHi must be the first and second output of MultNode
587 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
590 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
591 // of the values of MultNode, in which case MultNode will be removed in later
593 // If there exist users other than ADDENode or ADDCNode, this function returns
594 // here, which will result in MultNode being mapped to a single MULT
595 // instruction node rather than a pair of MULT and MADD instructions being
597 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
600 SDValue Chain = CurDAG->getEntryNode();
601 DebugLoc dl = ADDENode->getDebugLoc();
603 // create MipsMAdd(u) node
604 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
606 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue,
607 MultNode->getOperand(0),// Factor 0
608 MultNode->getOperand(1),// Factor 1
609 ADDCNode->getOperand(1),// Lo0
610 ADDENode->getOperand(1));// Hi0
612 // create CopyFromReg nodes
613 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
615 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
617 CopyFromLo.getValue(2));
619 // replace uses of adde and addc here
620 if (!SDValue(ADDCNode, 0).use_empty())
621 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
623 if (!SDValue(ADDENode, 0).use_empty())
624 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
630 // Transforms a subgraph in CurDAG if the following pattern is found:
631 // (addc Lo0, multLo), (sube Hi0, multHi),
633 // multHi/Lo: product of multiplication
634 // Lo0: initial value of Lo register
635 // Hi0: initial value of Hi register
636 // Return true if pattern matching was successful.
637 static bool SelectMsub(SDNode *SUBENode, SelectionDAG *CurDAG) {
638 // SUBENode's second operand must be a flag output of an SUBC node in order
639 // for the matching to be successful.
640 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
642 if (SUBCNode->getOpcode() != ISD::SUBC)
645 SDValue MultHi = SUBENode->getOperand(1);
646 SDValue MultLo = SUBCNode->getOperand(1);
647 SDNode *MultNode = MultHi.getNode();
648 unsigned MultOpc = MultHi.getOpcode();
650 // MultHi and MultLo must be generated by the same node,
651 if (MultLo.getNode() != MultNode)
654 // and it must be a multiplication.
655 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
658 // MultLo amd MultHi must be the first and second output of MultNode
660 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
663 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
664 // of the values of MultNode, in which case MultNode will be removed in later
666 // If there exist users other than SUBENode or SUBCNode, this function returns
667 // here, which will result in MultNode being mapped to a single MULT
668 // instruction node rather than a pair of MULT and MSUB instructions being
670 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
673 SDValue Chain = CurDAG->getEntryNode();
674 DebugLoc dl = SUBENode->getDebugLoc();
676 // create MipsSub(u) node
677 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
679 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue,
680 MultNode->getOperand(0),// Factor 0
681 MultNode->getOperand(1),// Factor 1
682 SUBCNode->getOperand(0),// Lo0
683 SUBENode->getOperand(0));// Hi0
685 // create CopyFromReg nodes
686 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
688 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
690 CopyFromLo.getValue(2));
692 // replace uses of sube and subc here
693 if (!SDValue(SUBCNode, 0).use_empty())
694 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
696 if (!SDValue(SUBENode, 0).use_empty())
697 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
702 static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG,
703 TargetLowering::DAGCombinerInfo &DCI,
704 const MipsSubtarget *Subtarget) {
705 if (DCI.isBeforeLegalize())
708 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
710 return SDValue(N, 0);
715 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG,
716 TargetLowering::DAGCombinerInfo &DCI,
717 const MipsSubtarget *Subtarget) {
718 if (DCI.isBeforeLegalize())
721 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
723 return SDValue(N, 0);
728 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG,
729 TargetLowering::DAGCombinerInfo &DCI,
730 const MipsSubtarget *Subtarget) {
731 if (DCI.isBeforeLegalizeOps())
734 EVT Ty = N->getValueType(0);
735 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
736 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
737 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
739 DebugLoc dl = N->getDebugLoc();
741 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
742 N->getOperand(0), N->getOperand(1));
743 SDValue InChain = DAG.getEntryNode();
744 SDValue InGlue = DivRem;
747 if (N->hasAnyUseOfValue(0)) {
748 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty,
750 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
751 InChain = CopyFromLo.getValue(1);
752 InGlue = CopyFromLo.getValue(2);
756 if (N->hasAnyUseOfValue(1)) {
757 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
759 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
765 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
767 default: llvm_unreachable("Unknown fp condition code!");
769 case ISD::SETOEQ: return Mips::FCOND_OEQ;
770 case ISD::SETUNE: return Mips::FCOND_UNE;
772 case ISD::SETOLT: return Mips::FCOND_OLT;
774 case ISD::SETOGT: return Mips::FCOND_OGT;
776 case ISD::SETOLE: return Mips::FCOND_OLE;
778 case ISD::SETOGE: return Mips::FCOND_OGE;
779 case ISD::SETULT: return Mips::FCOND_ULT;
780 case ISD::SETULE: return Mips::FCOND_ULE;
781 case ISD::SETUGT: return Mips::FCOND_UGT;
782 case ISD::SETUGE: return Mips::FCOND_UGE;
783 case ISD::SETUO: return Mips::FCOND_UN;
784 case ISD::SETO: return Mips::FCOND_OR;
786 case ISD::SETONE: return Mips::FCOND_ONE;
787 case ISD::SETUEQ: return Mips::FCOND_UEQ;
792 // Returns true if condition code has to be inverted.
793 static bool InvertFPCondCode(Mips::CondCode CC) {
794 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
797 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
798 "Illegal Condition Code");
803 // Creates and returns an FPCmp node from a setcc node.
804 // Returns Op if setcc is not a floating point comparison.
805 static SDValue CreateFPCmp(SelectionDAG &DAG, const SDValue &Op) {
806 // must be a SETCC node
807 if (Op.getOpcode() != ISD::SETCC)
810 SDValue LHS = Op.getOperand(0);
812 if (!LHS.getValueType().isFloatingPoint())
815 SDValue RHS = Op.getOperand(1);
816 DebugLoc dl = Op.getDebugLoc();
818 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
819 // node if necessary.
820 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
822 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
823 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
826 // Creates and returns a CMovFPT/F node.
827 static SDValue CreateCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
828 SDValue False, DebugLoc DL) {
829 bool invert = InvertFPCondCode((Mips::CondCode)
830 cast<ConstantSDNode>(Cond.getOperand(2))
833 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
834 True.getValueType(), True, False, Cond);
837 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
838 TargetLowering::DAGCombinerInfo &DCI,
839 const MipsSubtarget *Subtarget) {
840 if (DCI.isBeforeLegalizeOps())
843 SDValue SetCC = N->getOperand(0);
845 if ((SetCC.getOpcode() != ISD::SETCC) ||
846 !SetCC.getOperand(0).getValueType().isInteger())
849 SDValue False = N->getOperand(2);
850 EVT FalseTy = False.getValueType();
852 if (!FalseTy.isInteger())
855 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
857 if (!CN || CN->getZExtValue())
860 const DebugLoc DL = N->getDebugLoc();
861 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
862 SDValue True = N->getOperand(1);
864 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
865 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
867 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
870 static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG,
871 TargetLowering::DAGCombinerInfo &DCI,
872 const MipsSubtarget *Subtarget) {
873 // Pattern match EXT.
874 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
875 // => ext $dst, $src, size, pos
876 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
879 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
880 unsigned ShiftRightOpc = ShiftRight.getOpcode();
882 // Op's first operand must be a shift right.
883 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
886 // The second operand of the shift must be an immediate.
888 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
891 uint64_t Pos = CN->getZExtValue();
892 uint64_t SMPos, SMSize;
894 // Op's second operand must be a shifted mask.
895 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
896 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize))
899 // Return if the shifted mask does not start at bit 0 or the sum of its size
900 // and Pos exceeds the word's size.
901 EVT ValTy = N->getValueType(0);
902 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
905 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy,
906 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
907 DAG.getConstant(SMSize, MVT::i32));
910 static SDValue PerformORCombine(SDNode *N, SelectionDAG &DAG,
911 TargetLowering::DAGCombinerInfo &DCI,
912 const MipsSubtarget *Subtarget) {
913 // Pattern match INS.
914 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
915 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
916 // => ins $dst, $src, size, pos, $src1
917 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
920 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
921 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
924 // See if Op's first operand matches (and $src1 , mask0).
925 if (And0.getOpcode() != ISD::AND)
928 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
929 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
932 // See if Op's second operand matches (and (shl $src, pos), mask1).
933 if (And1.getOpcode() != ISD::AND)
936 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
937 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
940 // The shift masks must have the same position and size.
941 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
944 SDValue Shl = And1.getOperand(0);
945 if (Shl.getOpcode() != ISD::SHL)
948 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
951 unsigned Shamt = CN->getZExtValue();
953 // Return if the shift amount and the first bit position of mask are not the
955 EVT ValTy = N->getValueType(0);
956 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
959 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0),
960 DAG.getConstant(SMPos0, MVT::i32),
961 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
964 static SDValue PerformADDCombine(SDNode *N, SelectionDAG &DAG,
965 TargetLowering::DAGCombinerInfo &DCI,
966 const MipsSubtarget *Subtarget) {
967 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
969 if (DCI.isBeforeLegalizeOps())
972 SDValue Add = N->getOperand(1);
974 if (Add.getOpcode() != ISD::ADD)
977 SDValue Lo = Add.getOperand(1);
979 if ((Lo.getOpcode() != MipsISD::Lo) ||
980 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
983 EVT ValTy = N->getValueType(0);
984 DebugLoc DL = N->getDebugLoc();
986 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
988 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
991 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
993 SelectionDAG &DAG = DCI.DAG;
994 unsigned opc = N->getOpcode();
999 return PerformADDECombine(N, DAG, DCI, Subtarget);
1001 return PerformSUBECombine(N, DAG, DCI, Subtarget);
1004 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
1006 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
1008 return PerformANDCombine(N, DAG, DCI, Subtarget);
1010 return PerformORCombine(N, DAG, DCI, Subtarget);
1012 return PerformADDCombine(N, DAG, DCI, Subtarget);
1019 MipsTargetLowering::LowerOperationWrapper(SDNode *N,
1020 SmallVectorImpl<SDValue> &Results,
1021 SelectionDAG &DAG) const {
1022 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
1024 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
1025 Results.push_back(Res.getValue(I));
1029 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
1030 SmallVectorImpl<SDValue> &Results,
1031 SelectionDAG &DAG) const {
1032 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
1034 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
1035 Results.push_back(Res.getValue(I));
1038 SDValue MipsTargetLowering::
1039 LowerOperation(SDValue Op, SelectionDAG &DAG) const
1041 switch (Op.getOpcode())
1043 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
1044 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1045 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
1046 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
1047 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
1048 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
1049 case ISD::SELECT: return LowerSELECT(Op, DAG);
1050 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
1051 case ISD::SETCC: return LowerSETCC(Op, DAG);
1052 case ISD::VASTART: return LowerVASTART(Op, DAG);
1053 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
1054 case ISD::FABS: return LowerFABS(Op, DAG);
1055 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
1056 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
1057 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
1058 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
1059 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
1060 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
1061 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG, true);
1062 case ISD::SRL_PARTS: return LowerShiftRightParts(Op, DAG, false);
1063 case ISD::LOAD: return LowerLOAD(Op, DAG);
1064 case ISD::STORE: return LowerSTORE(Op, DAG);
1065 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1066 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
1067 case ISD::ADD: return LowerADD(Op, DAG);
1072 //===----------------------------------------------------------------------===//
1073 // Lower helper functions
1074 //===----------------------------------------------------------------------===//
1076 // AddLiveIn - This helper function adds the specified physical register to the
1077 // MachineFunction as a live in value. It also creates a corresponding
1078 // virtual register for it.
1080 AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
1082 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1083 MF.getRegInfo().addLiveIn(PReg, VReg);
1087 // Get fp branch code (not opcode) from condition code.
1088 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
1089 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
1090 return Mips::BRANCH_T;
1092 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
1093 "Invalid CondCode.");
1095 return Mips::BRANCH_F;
1099 static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
1101 const MipsSubtarget *Subtarget,
1102 const TargetInstrInfo *TII,
1103 bool isFPCmp, unsigned Opc) {
1104 // There is no need to expand CMov instructions if target has
1105 // conditional moves.
1106 if (Subtarget->hasCondMov())
1109 // To "insert" a SELECT_CC instruction, we actually have to insert the
1110 // diamond control-flow pattern. The incoming instruction knows the
1111 // destination vreg to set, the condition code register to branch on, the
1112 // true/false values to select between, and a branch opcode to use.
1113 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1114 MachineFunction::iterator It = BB;
1121 // bNE r1, r0, copy1MBB
1122 // fallthrough --> copy0MBB
1123 MachineBasicBlock *thisMBB = BB;
1124 MachineFunction *F = BB->getParent();
1125 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1126 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1127 F->insert(It, copy0MBB);
1128 F->insert(It, sinkMBB);
1130 // Transfer the remainder of BB and its successor edges to sinkMBB.
1131 sinkMBB->splice(sinkMBB->begin(), BB,
1132 llvm::next(MachineBasicBlock::iterator(MI)),
1134 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1136 // Next, add the true and fallthrough blocks as its successors.
1137 BB->addSuccessor(copy0MBB);
1138 BB->addSuccessor(sinkMBB);
1140 // Emit the right instruction according to the type of the operands compared
1142 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
1144 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
1145 .addReg(Mips::ZERO).addMBB(sinkMBB);
1148 // %FalseValue = ...
1149 // # fallthrough to sinkMBB
1152 // Update machine-CFG edges
1153 BB->addSuccessor(sinkMBB);
1156 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
1161 BuildMI(*BB, BB->begin(), dl,
1162 TII->get(Mips::PHI), MI->getOperand(0).getReg())
1163 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
1164 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
1166 BuildMI(*BB, BB->begin(), dl,
1167 TII->get(Mips::PHI), MI->getOperand(0).getReg())
1168 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
1169 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
1171 MI->eraseFromParent(); // The pseudo instruction is gone now.
1177 MipsTargetLowering::EmitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
1179 // bposge32_pseudo $vr0
1189 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
1191 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1192 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1193 const TargetRegisterClass *RC = &Mips::CPURegsRegClass;
1194 DebugLoc DL = MI->getDebugLoc();
1195 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1196 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1197 MachineFunction *F = BB->getParent();
1198 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1199 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1200 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
1203 F->insert(It, Sink);
1205 // Transfer the remainder of BB and its successor edges to Sink.
1206 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1208 Sink->transferSuccessorsAndUpdatePHIs(BB);
1211 BB->addSuccessor(FBB);
1212 BB->addSuccessor(TBB);
1213 FBB->addSuccessor(Sink);
1214 TBB->addSuccessor(Sink);
1216 // Insert the real bposge32 instruction to $BB.
1217 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
1220 unsigned VR2 = RegInfo.createVirtualRegister(RC);
1221 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
1222 .addReg(Mips::ZERO).addImm(0);
1223 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1226 unsigned VR1 = RegInfo.createVirtualRegister(RC);
1227 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
1228 .addReg(Mips::ZERO).addImm(1);
1230 // Insert phi function to $Sink.
1231 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1232 MI->getOperand(0).getReg())
1233 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
1235 MI->eraseFromParent(); // The pseudo instruction is gone now.
1239 MachineBasicBlock *MipsTargetLowering::EmitSel16(unsigned Opc, MachineInstr *MI,
1240 MachineBasicBlock *BB) const {
1241 if (DontExpandCondPseudos16)
1243 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1244 DebugLoc dl = MI->getDebugLoc();
1245 // To "insert" a SELECT_CC instruction, we actually have to insert the
1246 // diamond control-flow pattern. The incoming instruction knows the
1247 // destination vreg to set, the condition code register to branch on, the
1248 // true/false values to select between, and a branch opcode to use.
1249 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1250 MachineFunction::iterator It = BB;
1257 // bNE r1, r0, copy1MBB
1258 // fallthrough --> copy0MBB
1259 MachineBasicBlock *thisMBB = BB;
1260 MachineFunction *F = BB->getParent();
1261 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1262 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1263 F->insert(It, copy0MBB);
1264 F->insert(It, sinkMBB);
1266 // Transfer the remainder of BB and its successor edges to sinkMBB.
1267 sinkMBB->splice(sinkMBB->begin(), BB,
1268 llvm::next(MachineBasicBlock::iterator(MI)),
1270 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1272 // Next, add the true and fallthrough blocks as its successors.
1273 BB->addSuccessor(copy0MBB);
1274 BB->addSuccessor(sinkMBB);
1276 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(3).getReg())
1280 // %FalseValue = ...
1281 // # fallthrough to sinkMBB
1284 // Update machine-CFG edges
1285 BB->addSuccessor(sinkMBB);
1288 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
1292 BuildMI(*BB, BB->begin(), dl,
1293 TII->get(Mips::PHI), MI->getOperand(0).getReg())
1294 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
1295 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
1297 MI->eraseFromParent(); // The pseudo instruction is gone now.
1301 MachineBasicBlock *MipsTargetLowering::EmitSelT16
1302 (unsigned Opc1, unsigned Opc2,
1303 MachineInstr *MI, MachineBasicBlock *BB) const {
1304 if (DontExpandCondPseudos16)
1306 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1307 DebugLoc dl = MI->getDebugLoc();
1308 // To "insert" a SELECT_CC instruction, we actually have to insert the
1309 // diamond control-flow pattern. The incoming instruction knows the
1310 // destination vreg to set, the condition code register to branch on, the
1311 // true/false values to select between, and a branch opcode to use.
1312 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1313 MachineFunction::iterator It = BB;
1320 // bNE r1, r0, copy1MBB
1321 // fallthrough --> copy0MBB
1322 MachineBasicBlock *thisMBB = BB;
1323 MachineFunction *F = BB->getParent();
1324 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1325 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1326 F->insert(It, copy0MBB);
1327 F->insert(It, sinkMBB);
1329 // Transfer the remainder of BB and its successor edges to sinkMBB.
1330 sinkMBB->splice(sinkMBB->begin(), BB,
1331 llvm::next(MachineBasicBlock::iterator(MI)),
1333 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1335 // Next, add the true and fallthrough blocks as its successors.
1336 BB->addSuccessor(copy0MBB);
1337 BB->addSuccessor(sinkMBB);
1339 BuildMI(BB, dl, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
1340 .addReg(MI->getOperand(4).getReg());
1341 BuildMI(BB, dl, TII->get(Opc1)).addMBB(sinkMBB);
1344 // %FalseValue = ...
1345 // # fallthrough to sinkMBB
1348 // Update machine-CFG edges
1349 BB->addSuccessor(sinkMBB);
1352 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
1356 BuildMI(*BB, BB->begin(), dl,
1357 TII->get(Mips::PHI), MI->getOperand(0).getReg())
1358 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
1359 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
1361 MI->eraseFromParent(); // The pseudo instruction is gone now.
1367 MachineBasicBlock *MipsTargetLowering::EmitSeliT16
1368 (unsigned Opc1, unsigned Opc2,
1369 MachineInstr *MI, MachineBasicBlock *BB) const {
1370 if (DontExpandCondPseudos16)
1372 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1373 DebugLoc dl = MI->getDebugLoc();
1374 // To "insert" a SELECT_CC instruction, we actually have to insert the
1375 // diamond control-flow pattern. The incoming instruction knows the
1376 // destination vreg to set, the condition code register to branch on, the
1377 // true/false values to select between, and a branch opcode to use.
1378 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1379 MachineFunction::iterator It = BB;
1386 // bNE r1, r0, copy1MBB
1387 // fallthrough --> copy0MBB
1388 MachineBasicBlock *thisMBB = BB;
1389 MachineFunction *F = BB->getParent();
1390 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1391 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1392 F->insert(It, copy0MBB);
1393 F->insert(It, sinkMBB);
1395 // Transfer the remainder of BB and its successor edges to sinkMBB.
1396 sinkMBB->splice(sinkMBB->begin(), BB,
1397 llvm::next(MachineBasicBlock::iterator(MI)),
1399 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1401 // Next, add the true and fallthrough blocks as its successors.
1402 BB->addSuccessor(copy0MBB);
1403 BB->addSuccessor(sinkMBB);
1405 BuildMI(BB, dl, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
1406 .addImm(MI->getOperand(4).getImm());
1407 BuildMI(BB, dl, TII->get(Opc1)).addMBB(sinkMBB);
1410 // %FalseValue = ...
1411 // # fallthrough to sinkMBB
1414 // Update machine-CFG edges
1415 BB->addSuccessor(sinkMBB);
1418 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
1422 BuildMI(*BB, BB->begin(), dl,
1423 TII->get(Mips::PHI), MI->getOperand(0).getReg())
1424 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
1425 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
1427 MI->eraseFromParent(); // The pseudo instruction is gone now.
1434 *MipsTargetLowering::EmitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
1436 MachineBasicBlock *BB) const {
1437 if (DontExpandCondPseudos16)
1439 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1440 unsigned regX = MI->getOperand(0).getReg();
1441 unsigned regY = MI->getOperand(1).getReg();
1442 MachineBasicBlock *target = MI->getOperand(2).getMBB();
1443 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addReg(regY);
1444 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
1445 MI->eraseFromParent(); // The pseudo instruction is gone now.
1450 MachineBasicBlock *MipsTargetLowering::EmitFEXT_T8I8I16_ins(
1451 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc,
1452 MachineInstr *MI, MachineBasicBlock *BB) const {
1453 if (DontExpandCondPseudos16)
1455 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1456 unsigned regX = MI->getOperand(0).getReg();
1457 int64_t imm = MI->getOperand(1).getImm();
1458 MachineBasicBlock *target = MI->getOperand(2).getMBB();
1462 else if (isUInt<16>(imm))
1465 llvm_unreachable("immediate field not usable");
1466 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
1467 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
1468 MI->eraseFromParent(); // The pseudo instruction is gone now.
1473 static unsigned Mips16WhichOp8uOr16simm
1474 (unsigned shortOp, unsigned longOp, int64_t Imm) {
1477 else if (isInt<16>(Imm))
1480 llvm_unreachable("immediate field not usable");
1483 MachineBasicBlock *MipsTargetLowering::EmitFEXT_CCRX16_ins(
1485 MachineInstr *MI, MachineBasicBlock *BB) const {
1486 if (DontExpandCondPseudos16)
1488 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1489 unsigned CC = MI->getOperand(0).getReg();
1490 unsigned regX = MI->getOperand(1).getReg();
1491 unsigned regY = MI->getOperand(2).getReg();
1492 BuildMI(*BB, MI, MI->getDebugLoc(),
1493 TII->get(SltOpc)).addReg(regX).addReg(regY);
1494 BuildMI(*BB, MI, MI->getDebugLoc(),
1495 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
1496 MI->eraseFromParent(); // The pseudo instruction is gone now.
1499 MachineBasicBlock *MipsTargetLowering::EmitFEXT_CCRXI16_ins(
1500 unsigned SltiOpc, unsigned SltiXOpc,
1501 MachineInstr *MI, MachineBasicBlock *BB )const {
1502 if (DontExpandCondPseudos16)
1504 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1505 unsigned CC = MI->getOperand(0).getReg();
1506 unsigned regX = MI->getOperand(1).getReg();
1507 int64_t Imm = MI->getOperand(2).getImm();
1508 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
1509 BuildMI(*BB, MI, MI->getDebugLoc(),
1510 TII->get(SltOpc)).addReg(regX).addImm(Imm);
1511 BuildMI(*BB, MI, MI->getDebugLoc(),
1512 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
1513 MI->eraseFromParent(); // The pseudo instruction is gone now.
1518 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1519 MachineBasicBlock *BB) const {
1520 switch (MI->getOpcode()) {
1522 llvm_unreachable("Unexpected instr type to insert");
1523 case Mips::ATOMIC_LOAD_ADD_I8:
1524 case Mips::ATOMIC_LOAD_ADD_I8_P8:
1525 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
1526 case Mips::ATOMIC_LOAD_ADD_I16:
1527 case Mips::ATOMIC_LOAD_ADD_I16_P8:
1528 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
1529 case Mips::ATOMIC_LOAD_ADD_I32:
1530 case Mips::ATOMIC_LOAD_ADD_I32_P8:
1531 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
1532 case Mips::ATOMIC_LOAD_ADD_I64:
1533 case Mips::ATOMIC_LOAD_ADD_I64_P8:
1534 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu);
1536 case Mips::ATOMIC_LOAD_AND_I8:
1537 case Mips::ATOMIC_LOAD_AND_I8_P8:
1538 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
1539 case Mips::ATOMIC_LOAD_AND_I16:
1540 case Mips::ATOMIC_LOAD_AND_I16_P8:
1541 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
1542 case Mips::ATOMIC_LOAD_AND_I32:
1543 case Mips::ATOMIC_LOAD_AND_I32_P8:
1544 return EmitAtomicBinary(MI, BB, 4, Mips::AND);
1545 case Mips::ATOMIC_LOAD_AND_I64:
1546 case Mips::ATOMIC_LOAD_AND_I64_P8:
1547 return EmitAtomicBinary(MI, BB, 8, Mips::AND64);
1549 case Mips::ATOMIC_LOAD_OR_I8:
1550 case Mips::ATOMIC_LOAD_OR_I8_P8:
1551 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
1552 case Mips::ATOMIC_LOAD_OR_I16:
1553 case Mips::ATOMIC_LOAD_OR_I16_P8:
1554 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
1555 case Mips::ATOMIC_LOAD_OR_I32:
1556 case Mips::ATOMIC_LOAD_OR_I32_P8:
1557 return EmitAtomicBinary(MI, BB, 4, Mips::OR);
1558 case Mips::ATOMIC_LOAD_OR_I64:
1559 case Mips::ATOMIC_LOAD_OR_I64_P8:
1560 return EmitAtomicBinary(MI, BB, 8, Mips::OR64);
1562 case Mips::ATOMIC_LOAD_XOR_I8:
1563 case Mips::ATOMIC_LOAD_XOR_I8_P8:
1564 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
1565 case Mips::ATOMIC_LOAD_XOR_I16:
1566 case Mips::ATOMIC_LOAD_XOR_I16_P8:
1567 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
1568 case Mips::ATOMIC_LOAD_XOR_I32:
1569 case Mips::ATOMIC_LOAD_XOR_I32_P8:
1570 return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
1571 case Mips::ATOMIC_LOAD_XOR_I64:
1572 case Mips::ATOMIC_LOAD_XOR_I64_P8:
1573 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64);
1575 case Mips::ATOMIC_LOAD_NAND_I8:
1576 case Mips::ATOMIC_LOAD_NAND_I8_P8:
1577 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
1578 case Mips::ATOMIC_LOAD_NAND_I16:
1579 case Mips::ATOMIC_LOAD_NAND_I16_P8:
1580 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
1581 case Mips::ATOMIC_LOAD_NAND_I32:
1582 case Mips::ATOMIC_LOAD_NAND_I32_P8:
1583 return EmitAtomicBinary(MI, BB, 4, 0, true);
1584 case Mips::ATOMIC_LOAD_NAND_I64:
1585 case Mips::ATOMIC_LOAD_NAND_I64_P8:
1586 return EmitAtomicBinary(MI, BB, 8, 0, true);
1588 case Mips::ATOMIC_LOAD_SUB_I8:
1589 case Mips::ATOMIC_LOAD_SUB_I8_P8:
1590 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
1591 case Mips::ATOMIC_LOAD_SUB_I16:
1592 case Mips::ATOMIC_LOAD_SUB_I16_P8:
1593 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
1594 case Mips::ATOMIC_LOAD_SUB_I32:
1595 case Mips::ATOMIC_LOAD_SUB_I32_P8:
1596 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
1597 case Mips::ATOMIC_LOAD_SUB_I64:
1598 case Mips::ATOMIC_LOAD_SUB_I64_P8:
1599 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu);
1601 case Mips::ATOMIC_SWAP_I8:
1602 case Mips::ATOMIC_SWAP_I8_P8:
1603 return EmitAtomicBinaryPartword(MI, BB, 1, 0);
1604 case Mips::ATOMIC_SWAP_I16:
1605 case Mips::ATOMIC_SWAP_I16_P8:
1606 return EmitAtomicBinaryPartword(MI, BB, 2, 0);
1607 case Mips::ATOMIC_SWAP_I32:
1608 case Mips::ATOMIC_SWAP_I32_P8:
1609 return EmitAtomicBinary(MI, BB, 4, 0);
1610 case Mips::ATOMIC_SWAP_I64:
1611 case Mips::ATOMIC_SWAP_I64_P8:
1612 return EmitAtomicBinary(MI, BB, 8, 0);
1614 case Mips::ATOMIC_CMP_SWAP_I8:
1615 case Mips::ATOMIC_CMP_SWAP_I8_P8:
1616 return EmitAtomicCmpSwapPartword(MI, BB, 1);
1617 case Mips::ATOMIC_CMP_SWAP_I16:
1618 case Mips::ATOMIC_CMP_SWAP_I16_P8:
1619 return EmitAtomicCmpSwapPartword(MI, BB, 2);
1620 case Mips::ATOMIC_CMP_SWAP_I32:
1621 case Mips::ATOMIC_CMP_SWAP_I32_P8:
1622 return EmitAtomicCmpSwap(MI, BB, 4);
1623 case Mips::ATOMIC_CMP_SWAP_I64:
1624 case Mips::ATOMIC_CMP_SWAP_I64_P8:
1625 return EmitAtomicCmpSwap(MI, BB, 8);
1626 case Mips::BPOSGE32_PSEUDO:
1627 return EmitBPOSGE32(MI, BB);
1629 return EmitSel16(Mips::BeqzRxImm16, MI, BB);
1631 return EmitSel16(Mips::BnezRxImm16, MI, BB);
1632 case Mips::SelTBteqZCmpi:
1633 return EmitSeliT16(Mips::BteqzX16, Mips::CmpiRxImmX16, MI, BB);
1634 case Mips::SelTBteqZSlti:
1635 return EmitSeliT16(Mips::BteqzX16, Mips::SltiRxImmX16, MI, BB);
1636 case Mips::SelTBteqZSltiu:
1637 return EmitSeliT16(Mips::BteqzX16, Mips::SltiuRxImmX16, MI, BB);
1638 case Mips::SelTBtneZCmpi:
1639 return EmitSeliT16(Mips::BtnezX16, Mips::CmpiRxImmX16, MI, BB);
1640 case Mips::SelTBtneZSlti:
1641 return EmitSeliT16(Mips::BtnezX16, Mips::SltiRxImmX16, MI, BB);
1642 case Mips::SelTBtneZSltiu:
1643 return EmitSeliT16(Mips::BtnezX16, Mips::SltiuRxImmX16, MI, BB);
1644 case Mips::SelTBteqZCmp:
1645 return EmitSelT16(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
1646 case Mips::SelTBteqZSlt:
1647 return EmitSelT16(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
1648 case Mips::SelTBteqZSltu:
1649 return EmitSelT16(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
1650 case Mips::SelTBtneZCmp:
1651 return EmitSelT16(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
1652 case Mips::SelTBtneZSlt:
1653 return EmitSelT16(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
1654 case Mips::SelTBtneZSltu:
1655 return EmitSelT16(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
1656 case Mips::BteqzT8CmpX16:
1657 return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
1658 case Mips::BteqzT8SltX16:
1659 return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
1660 case Mips::BteqzT8SltuX16:
1661 // TBD: figure out a way to get this or remove the instruction
1663 return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
1664 case Mips::BtnezT8CmpX16:
1665 return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
1666 case Mips::BtnezT8SltX16:
1667 return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
1668 case Mips::BtnezT8SltuX16:
1669 // TBD: figure out a way to get this or remove the instruction
1671 return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
1672 case Mips::BteqzT8CmpiX16: return EmitFEXT_T8I8I16_ins(
1673 Mips::BteqzX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, MI, BB);
1674 case Mips::BteqzT8SltiX16: return EmitFEXT_T8I8I16_ins(
1675 Mips::BteqzX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
1676 case Mips::BteqzT8SltiuX16: return EmitFEXT_T8I8I16_ins(
1677 Mips::BteqzX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
1678 case Mips::BtnezT8CmpiX16: return EmitFEXT_T8I8I16_ins(
1679 Mips::BtnezX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, MI, BB);
1680 case Mips::BtnezT8SltiX16: return EmitFEXT_T8I8I16_ins(
1681 Mips::BtnezX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
1682 case Mips::BtnezT8SltiuX16: return EmitFEXT_T8I8I16_ins(
1683 Mips::BtnezX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
1685 case Mips::SltCCRxRy16:
1686 return EmitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB);
1688 case Mips::SltiCCRxImmX16:
1689 return EmitFEXT_CCRXI16_ins
1690 (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
1691 case Mips::SltiuCCRxImmX16:
1692 return EmitFEXT_CCRXI16_ins
1693 (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
1694 case Mips::SltuCCRxRy16:
1695 return EmitFEXT_CCRX16_ins
1696 (Mips::SltuRxRy16, MI, BB);
1700 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1701 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1703 MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
1704 unsigned Size, unsigned BinOpcode,
1706 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
1708 MachineFunction *MF = BB->getParent();
1709 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1710 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1711 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1712 DebugLoc dl = MI->getDebugLoc();
1713 unsigned LL, SC, AND, NOR, ZERO, BEQ;
1716 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1717 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1724 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1725 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1728 ZERO = Mips::ZERO_64;
1732 unsigned OldVal = MI->getOperand(0).getReg();
1733 unsigned Ptr = MI->getOperand(1).getReg();
1734 unsigned Incr = MI->getOperand(2).getReg();
1736 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1737 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1738 unsigned Success = RegInfo.createVirtualRegister(RC);
1740 // insert new blocks after the current block
1741 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1742 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1743 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1744 MachineFunction::iterator It = BB;
1746 MF->insert(It, loopMBB);
1747 MF->insert(It, exitMBB);
1749 // Transfer the remainder of BB and its successor edges to exitMBB.
1750 exitMBB->splice(exitMBB->begin(), BB,
1751 llvm::next(MachineBasicBlock::iterator(MI)),
1753 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1757 // fallthrough --> loopMBB
1758 BB->addSuccessor(loopMBB);
1759 loopMBB->addSuccessor(loopMBB);
1760 loopMBB->addSuccessor(exitMBB);
1763 // ll oldval, 0(ptr)
1764 // <binop> storeval, oldval, incr
1765 // sc success, storeval, 0(ptr)
1766 // beq success, $0, loopMBB
1768 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1770 // and andres, oldval, incr
1771 // nor storeval, $0, andres
1772 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1773 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1774 } else if (BinOpcode) {
1775 // <binop> storeval, oldval, incr
1776 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1780 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1781 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1783 MI->eraseFromParent(); // The instruction is gone now.
1789 MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
1790 MachineBasicBlock *BB,
1791 unsigned Size, unsigned BinOpcode,
1793 assert((Size == 1 || Size == 2) &&
1794 "Unsupported size for EmitAtomicBinaryPartial.");
1796 MachineFunction *MF = BB->getParent();
1797 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1798 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1799 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1800 DebugLoc dl = MI->getDebugLoc();
1801 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1802 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1804 unsigned Dest = MI->getOperand(0).getReg();
1805 unsigned Ptr = MI->getOperand(1).getReg();
1806 unsigned Incr = MI->getOperand(2).getReg();
1808 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1809 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1810 unsigned Mask = RegInfo.createVirtualRegister(RC);
1811 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1812 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1813 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1814 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1815 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1816 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1817 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1818 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1819 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1820 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1821 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1822 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1823 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1824 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1825 unsigned Success = RegInfo.createVirtualRegister(RC);
1827 // insert new blocks after the current block
1828 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1829 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1830 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1831 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1832 MachineFunction::iterator It = BB;
1834 MF->insert(It, loopMBB);
1835 MF->insert(It, sinkMBB);
1836 MF->insert(It, exitMBB);
1838 // Transfer the remainder of BB and its successor edges to exitMBB.
1839 exitMBB->splice(exitMBB->begin(), BB,
1840 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1841 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1843 BB->addSuccessor(loopMBB);
1844 loopMBB->addSuccessor(loopMBB);
1845 loopMBB->addSuccessor(sinkMBB);
1846 sinkMBB->addSuccessor(exitMBB);
1849 // addiu masklsb2,$0,-4 # 0xfffffffc
1850 // and alignedaddr,ptr,masklsb2
1851 // andi ptrlsb2,ptr,3
1852 // sll shiftamt,ptrlsb2,3
1853 // ori maskupper,$0,255 # 0xff
1854 // sll mask,maskupper,shiftamt
1855 // nor mask2,$0,mask
1856 // sll incr2,incr,shiftamt
1858 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1859 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1860 .addReg(Mips::ZERO).addImm(-4);
1861 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1862 .addReg(Ptr).addReg(MaskLSB2);
1863 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1864 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1865 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1866 .addReg(Mips::ZERO).addImm(MaskImm);
1867 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1868 .addReg(ShiftAmt).addReg(MaskUpper);
1869 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1870 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
1872 // atomic.load.binop
1874 // ll oldval,0(alignedaddr)
1875 // binop binopres,oldval,incr2
1876 // and newval,binopres,mask
1877 // and maskedoldval0,oldval,mask2
1878 // or storeval,maskedoldval0,newval
1879 // sc success,storeval,0(alignedaddr)
1880 // beq success,$0,loopMBB
1884 // ll oldval,0(alignedaddr)
1885 // and newval,incr2,mask
1886 // and maskedoldval0,oldval,mask2
1887 // or storeval,maskedoldval0,newval
1888 // sc success,storeval,0(alignedaddr)
1889 // beq success,$0,loopMBB
1892 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1894 // and andres, oldval, incr2
1895 // nor binopres, $0, andres
1896 // and newval, binopres, mask
1897 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1898 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes)
1899 .addReg(Mips::ZERO).addReg(AndRes);
1900 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1901 } else if (BinOpcode) {
1902 // <binop> binopres, oldval, incr2
1903 // and newval, binopres, mask
1904 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1905 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1906 } else {// atomic.swap
1907 // and newval, incr2, mask
1908 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1911 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1912 .addReg(OldVal).addReg(Mask2);
1913 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1914 .addReg(MaskedOldVal0).addReg(NewVal);
1915 BuildMI(BB, dl, TII->get(SC), Success)
1916 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1917 BuildMI(BB, dl, TII->get(Mips::BEQ))
1918 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1921 // and maskedoldval1,oldval,mask
1922 // srl srlres,maskedoldval1,shiftamt
1923 // sll sllres,srlres,24
1924 // sra dest,sllres,24
1926 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1928 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1929 .addReg(OldVal).addReg(Mask);
1930 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1931 .addReg(ShiftAmt).addReg(MaskedOldVal1);
1932 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1933 .addReg(SrlRes).addImm(ShiftImm);
1934 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
1935 .addReg(SllRes).addImm(ShiftImm);
1937 MI->eraseFromParent(); // The instruction is gone now.
1943 MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
1944 MachineBasicBlock *BB,
1945 unsigned Size) const {
1946 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1948 MachineFunction *MF = BB->getParent();
1949 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1950 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1951 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1952 DebugLoc dl = MI->getDebugLoc();
1953 unsigned LL, SC, ZERO, BNE, BEQ;
1956 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1957 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1963 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1964 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1965 ZERO = Mips::ZERO_64;
1970 unsigned Dest = MI->getOperand(0).getReg();
1971 unsigned Ptr = MI->getOperand(1).getReg();
1972 unsigned OldVal = MI->getOperand(2).getReg();
1973 unsigned NewVal = MI->getOperand(3).getReg();
1975 unsigned Success = RegInfo.createVirtualRegister(RC);
1977 // insert new blocks after the current block
1978 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1979 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1980 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1981 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1982 MachineFunction::iterator It = BB;
1984 MF->insert(It, loop1MBB);
1985 MF->insert(It, loop2MBB);
1986 MF->insert(It, exitMBB);
1988 // Transfer the remainder of BB and its successor edges to exitMBB.
1989 exitMBB->splice(exitMBB->begin(), BB,
1990 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1991 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1995 // fallthrough --> loop1MBB
1996 BB->addSuccessor(loop1MBB);
1997 loop1MBB->addSuccessor(exitMBB);
1998 loop1MBB->addSuccessor(loop2MBB);
1999 loop2MBB->addSuccessor(loop1MBB);
2000 loop2MBB->addSuccessor(exitMBB);
2004 // bne dest, oldval, exitMBB
2006 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0);
2007 BuildMI(BB, dl, TII->get(BNE))
2008 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
2011 // sc success, newval, 0(ptr)
2012 // beq success, $0, loop1MBB
2014 BuildMI(BB, dl, TII->get(SC), Success)
2015 .addReg(NewVal).addReg(Ptr).addImm(0);
2016 BuildMI(BB, dl, TII->get(BEQ))
2017 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
2019 MI->eraseFromParent(); // The instruction is gone now.
2025 MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
2026 MachineBasicBlock *BB,
2027 unsigned Size) const {
2028 assert((Size == 1 || Size == 2) &&
2029 "Unsupported size for EmitAtomicCmpSwapPartial.");
2031 MachineFunction *MF = BB->getParent();
2032 MachineRegisterInfo &RegInfo = MF->getRegInfo();
2033 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
2034 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2035 DebugLoc dl = MI->getDebugLoc();
2036 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
2037 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
2039 unsigned Dest = MI->getOperand(0).getReg();
2040 unsigned Ptr = MI->getOperand(1).getReg();
2041 unsigned CmpVal = MI->getOperand(2).getReg();
2042 unsigned NewVal = MI->getOperand(3).getReg();
2044 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
2045 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
2046 unsigned Mask = RegInfo.createVirtualRegister(RC);
2047 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
2048 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
2049 unsigned OldVal = RegInfo.createVirtualRegister(RC);
2050 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
2051 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
2052 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
2053 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
2054 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
2055 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
2056 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
2057 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
2058 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
2059 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
2060 unsigned SllRes = RegInfo.createVirtualRegister(RC);
2061 unsigned Success = RegInfo.createVirtualRegister(RC);
2063 // insert new blocks after the current block
2064 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2065 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
2066 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
2067 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
2068 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
2069 MachineFunction::iterator It = BB;
2071 MF->insert(It, loop1MBB);
2072 MF->insert(It, loop2MBB);
2073 MF->insert(It, sinkMBB);
2074 MF->insert(It, exitMBB);
2076 // Transfer the remainder of BB and its successor edges to exitMBB.
2077 exitMBB->splice(exitMBB->begin(), BB,
2078 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
2079 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
2081 BB->addSuccessor(loop1MBB);
2082 loop1MBB->addSuccessor(sinkMBB);
2083 loop1MBB->addSuccessor(loop2MBB);
2084 loop2MBB->addSuccessor(loop1MBB);
2085 loop2MBB->addSuccessor(sinkMBB);
2086 sinkMBB->addSuccessor(exitMBB);
2088 // FIXME: computation of newval2 can be moved to loop2MBB.
2090 // addiu masklsb2,$0,-4 # 0xfffffffc
2091 // and alignedaddr,ptr,masklsb2
2092 // andi ptrlsb2,ptr,3
2093 // sll shiftamt,ptrlsb2,3
2094 // ori maskupper,$0,255 # 0xff
2095 // sll mask,maskupper,shiftamt
2096 // nor mask2,$0,mask
2097 // andi maskedcmpval,cmpval,255
2098 // sll shiftedcmpval,maskedcmpval,shiftamt
2099 // andi maskednewval,newval,255
2100 // sll shiftednewval,maskednewval,shiftamt
2101 int64_t MaskImm = (Size == 1) ? 255 : 65535;
2102 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
2103 .addReg(Mips::ZERO).addImm(-4);
2104 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
2105 .addReg(Ptr).addReg(MaskLSB2);
2106 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
2107 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
2108 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
2109 .addReg(Mips::ZERO).addImm(MaskImm);
2110 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
2111 .addReg(ShiftAmt).addReg(MaskUpper);
2112 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
2113 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal)
2114 .addReg(CmpVal).addImm(MaskImm);
2115 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal)
2116 .addReg(ShiftAmt).addReg(MaskedCmpVal);
2117 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal)
2118 .addReg(NewVal).addImm(MaskImm);
2119 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal)
2120 .addReg(ShiftAmt).addReg(MaskedNewVal);
2123 // ll oldval,0(alginedaddr)
2124 // and maskedoldval0,oldval,mask
2125 // bne maskedoldval0,shiftedcmpval,sinkMBB
2127 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
2128 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
2129 .addReg(OldVal).addReg(Mask);
2130 BuildMI(BB, dl, TII->get(Mips::BNE))
2131 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
2134 // and maskedoldval1,oldval,mask2
2135 // or storeval,maskedoldval1,shiftednewval
2136 // sc success,storeval,0(alignedaddr)
2137 // beq success,$0,loop1MBB
2139 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
2140 .addReg(OldVal).addReg(Mask2);
2141 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
2142 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
2143 BuildMI(BB, dl, TII->get(SC), Success)
2144 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
2145 BuildMI(BB, dl, TII->get(Mips::BEQ))
2146 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
2149 // srl srlres,maskedoldval0,shiftamt
2150 // sll sllres,srlres,24
2151 // sra dest,sllres,24
2153 int64_t ShiftImm = (Size == 1) ? 24 : 16;
2155 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
2156 .addReg(ShiftAmt).addReg(MaskedOldVal0);
2157 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
2158 .addReg(SrlRes).addImm(ShiftImm);
2159 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
2160 .addReg(SllRes).addImm(ShiftImm);
2162 MI->eraseFromParent(); // The instruction is gone now.
2167 //===----------------------------------------------------------------------===//
2168 // Misc Lower Operation implementation
2169 //===----------------------------------------------------------------------===//
2170 SDValue MipsTargetLowering::
2171 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
2173 // The first operand is the chain, the second is the condition, the third is
2174 // the block to branch to if the condition is true.
2175 SDValue Chain = Op.getOperand(0);
2176 SDValue Dest = Op.getOperand(2);
2177 DebugLoc dl = Op.getDebugLoc();
2179 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
2181 // Return if flag is not set by a floating point comparison.
2182 if (CondRes.getOpcode() != MipsISD::FPCmp)
2185 SDValue CCNode = CondRes.getOperand(2);
2187 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
2188 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
2190 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
2194 SDValue MipsTargetLowering::
2195 LowerSELECT(SDValue Op, SelectionDAG &DAG) const
2197 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
2199 // Return if flag is not set by a floating point comparison.
2200 if (Cond.getOpcode() != MipsISD::FPCmp)
2203 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
2207 SDValue MipsTargetLowering::
2208 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
2210 DebugLoc DL = Op.getDebugLoc();
2211 EVT Ty = Op.getOperand(0).getValueType();
2212 SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty),
2213 Op.getOperand(0), Op.getOperand(1),
2216 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
2220 SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2221 SDValue Cond = CreateFPCmp(DAG, Op);
2223 assert(Cond.getOpcode() == MipsISD::FPCmp &&
2224 "Floating point operand expected.");
2226 SDValue True = DAG.getConstant(1, MVT::i32);
2227 SDValue False = DAG.getConstant(0, MVT::i32);
2229 return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc());
2232 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
2233 SelectionDAG &DAG) const {
2234 // FIXME there isn't actually debug info here
2235 DebugLoc dl = Op.getDebugLoc();
2236 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2238 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
2239 const MipsTargetObjectFile &TLOF =
2240 (const MipsTargetObjectFile&)getObjFileLowering();
2242 // %gp_rel relocation
2243 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
2244 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
2246 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl,
2247 DAG.getVTList(MVT::i32), &GA, 1);
2248 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
2249 return DAG.getNode(ISD::ADD, dl, MVT::i32, GPReg, GPRelNode);
2252 // %hi/%lo relocation
2253 return getAddrNonPIC(Op, DAG);
2256 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
2257 return getAddrLocal(Op, DAG, HasMips64);
2260 return getAddrGlobalLargeGOT(Op, DAG, MipsII::MO_GOT_HI16,
2261 MipsII::MO_GOT_LO16);
2263 return getAddrGlobal(Op, DAG,
2264 HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16);
2267 SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
2268 SelectionDAG &DAG) const {
2269 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
2270 return getAddrNonPIC(Op, DAG);
2272 return getAddrLocal(Op, DAG, HasMips64);
2275 SDValue MipsTargetLowering::
2276 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
2278 // If the relocation model is PIC, use the General Dynamic TLS Model or
2279 // Local Dynamic TLS model, otherwise use the Initial Exec or
2280 // Local Exec TLS Model.
2282 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2283 DebugLoc dl = GA->getDebugLoc();
2284 const GlobalValue *GV = GA->getGlobal();
2285 EVT PtrVT = getPointerTy();
2287 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2289 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2290 // General Dynamic and Local Dynamic TLS Model.
2291 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
2294 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag);
2295 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT,
2296 GetGlobalReg(DAG, PtrVT), TGA);
2297 unsigned PtrSize = PtrVT.getSizeInBits();
2298 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
2300 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
2304 Entry.Node = Argument;
2306 Args.push_back(Entry);
2308 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy,
2309 false, false, false, false, 0, CallingConv::C,
2310 /*isTailCall=*/false, /*doesNotRet=*/false,
2311 /*isReturnValueUsed=*/true,
2312 TlsGetAddr, Args, DAG, dl);
2313 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2315 SDValue Ret = CallResult.first;
2317 if (model != TLSModel::LocalDynamic)
2320 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2321 MipsII::MO_DTPREL_HI);
2322 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
2323 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2324 MipsII::MO_DTPREL_LO);
2325 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
2326 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret);
2327 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo);
2331 if (model == TLSModel::InitialExec) {
2332 // Initial Exec TLS Model
2333 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2334 MipsII::MO_GOTTPREL);
2335 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
2337 Offset = DAG.getLoad(PtrVT, dl,
2338 DAG.getEntryNode(), TGA, MachinePointerInfo(),
2339 false, false, false, 0);
2341 // Local Exec TLS Model
2342 assert(model == TLSModel::LocalExec);
2343 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2344 MipsII::MO_TPREL_HI);
2345 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2346 MipsII::MO_TPREL_LO);
2347 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
2348 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
2349 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
2352 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
2353 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2356 SDValue MipsTargetLowering::
2357 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
2359 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
2360 return getAddrNonPIC(Op, DAG);
2362 return getAddrLocal(Op, DAG, HasMips64);
2365 SDValue MipsTargetLowering::
2366 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
2368 // gp_rel relocation
2369 // FIXME: we should reference the constant pool using small data sections,
2370 // but the asm printer currently doesn't support this feature without
2371 // hacking it. This feature should come soon so we can uncomment the
2373 //if (IsInSmallSection(C->getType())) {
2374 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
2375 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
2376 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
2378 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
2379 return getAddrNonPIC(Op, DAG);
2381 return getAddrLocal(Op, DAG, HasMips64);
2384 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2385 MachineFunction &MF = DAG.getMachineFunction();
2386 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2388 DebugLoc dl = Op.getDebugLoc();
2389 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2392 // vastart just stores the address of the VarArgsFrameIndex slot into the
2393 // memory location argument.
2394 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2395 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
2396 MachinePointerInfo(SV), false, false, 0);
2399 static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2400 EVT TyX = Op.getOperand(0).getValueType();
2401 EVT TyY = Op.getOperand(1).getValueType();
2402 SDValue Const1 = DAG.getConstant(1, MVT::i32);
2403 SDValue Const31 = DAG.getConstant(31, MVT::i32);
2404 DebugLoc DL = Op.getDebugLoc();
2407 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2409 SDValue X = (TyX == MVT::f32) ?
2410 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2411 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2413 SDValue Y = (TyY == MVT::f32) ?
2414 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2415 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
2419 // ext E, Y, 31, 1 ; extract bit31 of Y
2420 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
2421 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2422 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2425 // srl SrlX, SllX, 1
2427 // sll SllY, SrlX, 31
2428 // or Or, SrlX, SllY
2429 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2430 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2431 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2432 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2433 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2436 if (TyX == MVT::f32)
2437 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2439 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2440 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
2441 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2444 static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2445 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2446 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2447 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2448 SDValue Const1 = DAG.getConstant(1, MVT::i32);
2449 DebugLoc DL = Op.getDebugLoc();
2451 // Bitcast to integer nodes.
2452 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2453 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2456 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
2457 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
2458 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2459 DAG.getConstant(WidthY - 1, MVT::i32), Const1);
2461 if (WidthX > WidthY)
2462 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2463 else if (WidthY > WidthX)
2464 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2466 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2467 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
2468 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2471 // (d)sll SllX, X, 1
2472 // (d)srl SrlX, SllX, 1
2473 // (d)srl SrlY, Y, width(Y)-1
2474 // (d)sll SllY, SrlX, width(Y)-1
2475 // or Or, SrlX, SllY
2476 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2477 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2478 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2479 DAG.getConstant(WidthY - 1, MVT::i32));
2481 if (WidthX > WidthY)
2482 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2483 else if (WidthY > WidthX)
2484 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2486 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2487 DAG.getConstant(WidthX - 1, MVT::i32));
2488 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2489 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2493 MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2494 if (Subtarget->hasMips64())
2495 return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2());
2497 return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
2500 static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2501 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
2502 DebugLoc DL = Op.getDebugLoc();
2504 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2506 SDValue X = (Op.getValueType() == MVT::f32) ?
2507 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2508 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2513 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
2514 DAG.getRegister(Mips::ZERO, MVT::i32),
2515 DAG.getConstant(31, MVT::i32), Const1, X);
2517 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2518 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2521 if (Op.getValueType() == MVT::f32)
2522 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
2524 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2525 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
2526 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2529 static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2530 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
2531 DebugLoc DL = Op.getDebugLoc();
2533 // Bitcast to integer node.
2534 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
2538 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
2539 DAG.getRegister(Mips::ZERO_64, MVT::i64),
2540 DAG.getConstant(63, MVT::i32), Const1, X);
2542 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
2543 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
2546 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
2550 MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
2551 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
2552 return LowerFABS64(Op, DAG, Subtarget->hasMips32r2());
2554 return LowerFABS32(Op, DAG, Subtarget->hasMips32r2());
2557 SDValue MipsTargetLowering::
2558 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2560 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2561 "Frame address can only be determined for current frame.");
2563 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2564 MFI->setFrameAddressIsTaken(true);
2565 EVT VT = Op.getValueType();
2566 DebugLoc dl = Op.getDebugLoc();
2567 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2568 IsN64 ? Mips::FP_64 : Mips::FP, VT);
2572 SDValue MipsTargetLowering::LowerRETURNADDR(SDValue Op,
2573 SelectionDAG &DAG) const {
2575 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2576 "Return address can be determined only for current frame.");
2578 MachineFunction &MF = DAG.getMachineFunction();
2579 MachineFrameInfo *MFI = MF.getFrameInfo();
2580 MVT VT = Op.getSimpleValueType();
2581 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
2582 MFI->setReturnAddressIsTaken(true);
2584 // Return RA, which contains the return address. Mark it an implicit live-in.
2585 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2586 return DAG.getCopyFromReg(DAG.getEntryNode(), Op.getDebugLoc(), Reg, VT);
2589 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2590 // generated from __builtin_eh_return (offset, handler)
2591 // The effect of this is to adjust the stack pointer by "offset"
2592 // and then branch to "handler".
2593 SDValue MipsTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2595 MachineFunction &MF = DAG.getMachineFunction();
2596 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2598 MipsFI->setCallsEhReturn();
2599 SDValue Chain = Op.getOperand(0);
2600 SDValue Offset = Op.getOperand(1);
2601 SDValue Handler = Op.getOperand(2);
2602 DebugLoc DL = Op.getDebugLoc();
2603 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
2605 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2606 // EH_RETURN nodes, so that instructions are emitted back-to-back.
2607 unsigned OffsetReg = IsN64 ? Mips::V1_64 : Mips::V1;
2608 unsigned AddrReg = IsN64 ? Mips::V0_64 : Mips::V0;
2609 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2610 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2611 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2612 DAG.getRegister(OffsetReg, Ty),
2613 DAG.getRegister(AddrReg, getPointerTy()),
2617 // TODO: set SType according to the desired memory barrier behavior.
2619 MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const {
2621 DebugLoc dl = Op.getDebugLoc();
2622 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2623 DAG.getConstant(SType, MVT::i32));
2626 SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
2627 SelectionDAG &DAG) const {
2628 // FIXME: Need pseudo-fence for 'singlethread' fences
2629 // FIXME: Set SType for weaker fences where supported/appropriate.
2631 DebugLoc dl = Op.getDebugLoc();
2632 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2633 DAG.getConstant(SType, MVT::i32));
2636 SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op,
2637 SelectionDAG &DAG) const {
2638 DebugLoc DL = Op.getDebugLoc();
2639 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2640 SDValue Shamt = Op.getOperand(2);
2643 // lo = (shl lo, shamt)
2644 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2647 // hi = (shl lo, shamt[4:0])
2648 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2649 DAG.getConstant(-1, MVT::i32));
2650 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
2651 DAG.getConstant(1, MVT::i32));
2652 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
2654 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
2655 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2656 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
2657 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2658 DAG.getConstant(0x20, MVT::i32));
2659 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2660 DAG.getConstant(0, MVT::i32), ShiftLeftLo);
2661 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
2663 SDValue Ops[2] = {Lo, Hi};
2664 return DAG.getMergeValues(Ops, 2, DL);
2667 SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2669 DebugLoc DL = Op.getDebugLoc();
2670 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2671 SDValue Shamt = Op.getOperand(2);
2674 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2676 // hi = (sra hi, shamt)
2678 // hi = (srl hi, shamt)
2681 // lo = (sra hi, shamt[4:0])
2682 // hi = (sra hi, 31)
2684 // lo = (srl hi, shamt[4:0])
2686 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2687 DAG.getConstant(-1, MVT::i32));
2688 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
2689 DAG.getConstant(1, MVT::i32));
2690 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
2691 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
2692 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2693 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2695 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2696 DAG.getConstant(0x20, MVT::i32));
2697 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
2698 DAG.getConstant(31, MVT::i32));
2699 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
2700 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2701 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
2704 SDValue Ops[2] = {Lo, Hi};
2705 return DAG.getMergeValues(Ops, 2, DL);
2708 static SDValue CreateLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2709 SDValue Chain, SDValue Src, unsigned Offset) {
2710 SDValue Ptr = LD->getBasePtr();
2711 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2712 EVT BasePtrVT = Ptr.getValueType();
2713 DebugLoc DL = LD->getDebugLoc();
2714 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2717 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2718 DAG.getConstant(Offset, BasePtrVT));
2720 SDValue Ops[] = { Chain, Ptr, Src };
2721 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2722 LD->getMemOperand());
2725 // Expand an unaligned 32 or 64-bit integer load node.
2726 SDValue MipsTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2727 LoadSDNode *LD = cast<LoadSDNode>(Op);
2728 EVT MemVT = LD->getMemoryVT();
2730 // Return if load is aligned or if MemVT is neither i32 nor i64.
2731 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2732 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2735 bool IsLittle = Subtarget->isLittle();
2736 EVT VT = Op.getValueType();
2737 ISD::LoadExtType ExtType = LD->getExtensionType();
2738 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2740 assert((VT == MVT::i32) || (VT == MVT::i64));
2743 // (set dst, (i64 (load baseptr)))
2745 // (set tmp, (ldl (add baseptr, 7), undef))
2746 // (set dst, (ldr baseptr, tmp))
2747 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2748 SDValue LDL = CreateLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2750 return CreateLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2754 SDValue LWL = CreateLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2756 SDValue LWR = CreateLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2760 // (set dst, (i32 (load baseptr))) or
2761 // (set dst, (i64 (sextload baseptr))) or
2762 // (set dst, (i64 (extload baseptr)))
2764 // (set tmp, (lwl (add baseptr, 3), undef))
2765 // (set dst, (lwr baseptr, tmp))
2766 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2767 (ExtType == ISD::EXTLOAD))
2770 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2773 // (set dst, (i64 (zextload baseptr)))
2775 // (set tmp0, (lwl (add baseptr, 3), undef))
2776 // (set tmp1, (lwr baseptr, tmp0))
2777 // (set tmp2, (shl tmp1, 32))
2778 // (set dst, (srl tmp2, 32))
2779 DebugLoc DL = LD->getDebugLoc();
2780 SDValue Const32 = DAG.getConstant(32, MVT::i32);
2781 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2782 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2783 SDValue Ops[] = { SRL, LWR.getValue(1) };
2784 return DAG.getMergeValues(Ops, 2, DL);
2787 static SDValue CreateStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2788 SDValue Chain, unsigned Offset) {
2789 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2790 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2791 DebugLoc DL = SD->getDebugLoc();
2792 SDVTList VTList = DAG.getVTList(MVT::Other);
2795 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2796 DAG.getConstant(Offset, BasePtrVT));
2798 SDValue Ops[] = { Chain, Value, Ptr };
2799 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2800 SD->getMemOperand());
2803 // Expand an unaligned 32 or 64-bit integer store node.
2804 SDValue MipsTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2805 StoreSDNode *SD = cast<StoreSDNode>(Op);
2806 EVT MemVT = SD->getMemoryVT();
2808 // Return if store is aligned or if MemVT is neither i32 nor i64.
2809 if ((SD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2810 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2813 bool IsLittle = Subtarget->isLittle();
2814 SDValue Value = SD->getValue(), Chain = SD->getChain();
2815 EVT VT = Value.getValueType();
2818 // (store val, baseptr) or
2819 // (truncstore val, baseptr)
2821 // (swl val, (add baseptr, 3))
2822 // (swr val, baseptr)
2823 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2824 SDValue SWL = CreateStoreLR(MipsISD::SWL, DAG, SD, Chain,
2826 return CreateStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2829 assert(VT == MVT::i64);
2832 // (store val, baseptr)
2834 // (sdl val, (add baseptr, 7))
2835 // (sdr val, baseptr)
2836 SDValue SDL = CreateStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2837 return CreateStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2840 // This function expands mips intrinsic nodes which have 64-bit input operands
2841 // or output values.
2843 // out64 = intrinsic-node in64
2845 // lo = copy (extract-element (in64, 0))
2846 // hi = copy (extract-element (in64, 1))
2847 // mips-specific-node
2850 // out64 = merge-values (v0, v1)
2852 static SDValue LowerDSPIntr(SDValue Op, SelectionDAG &DAG,
2853 unsigned Opc, bool HasI64In, bool HasI64Out) {
2854 DebugLoc DL = Op.getDebugLoc();
2855 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
2856 SDValue Chain = HasChainIn ? Op->getOperand(0) : DAG.getEntryNode();
2857 SmallVector<SDValue, 3> Ops;
2860 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
2861 Op->getOperand(1 + HasChainIn),
2862 DAG.getConstant(0, MVT::i32));
2863 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
2864 Op->getOperand(1 + HasChainIn),
2865 DAG.getConstant(1, MVT::i32));
2867 Chain = DAG.getCopyToReg(Chain, DL, Mips::LO, InLo, SDValue());
2868 Chain = DAG.getCopyToReg(Chain, DL, Mips::HI, InHi, Chain.getValue(1));
2870 Ops.push_back(Chain);
2871 Ops.append(Op->op_begin() + HasChainIn + 2, Op->op_end());
2872 Ops.push_back(Chain.getValue(1));
2874 Ops.push_back(Chain);
2875 Ops.append(Op->op_begin() + HasChainIn + 1, Op->op_end());
2879 return DAG.getNode(Opc, DL, Op->value_begin(), Op->getNumValues(),
2880 Ops.begin(), Ops.size());
2882 SDValue Intr = DAG.getNode(Opc, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2883 Ops.begin(), Ops.size());
2884 SDValue OutLo = DAG.getCopyFromReg(Intr.getValue(0), DL, Mips::LO, MVT::i32,
2886 SDValue OutHi = DAG.getCopyFromReg(OutLo.getValue(1), DL, Mips::HI, MVT::i32,
2888 SDValue Out = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, OutLo, OutHi);
2893 SDValue Vals[] = { Out, OutHi.getValue(1) };
2894 return DAG.getMergeValues(Vals, 2, DL);
2897 SDValue MipsTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
2898 SelectionDAG &DAG) const {
2899 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
2902 case Intrinsic::mips_shilo:
2903 return LowerDSPIntr(Op, DAG, MipsISD::SHILO, true, true);
2904 case Intrinsic::mips_dpau_h_qbl:
2905 return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL, true, true);
2906 case Intrinsic::mips_dpau_h_qbr:
2907 return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR, true, true);
2908 case Intrinsic::mips_dpsu_h_qbl:
2909 return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL, true, true);
2910 case Intrinsic::mips_dpsu_h_qbr:
2911 return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR, true, true);
2912 case Intrinsic::mips_dpa_w_ph:
2913 return LowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH, true, true);
2914 case Intrinsic::mips_dps_w_ph:
2915 return LowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH, true, true);
2916 case Intrinsic::mips_dpax_w_ph:
2917 return LowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH, true, true);
2918 case Intrinsic::mips_dpsx_w_ph:
2919 return LowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH, true, true);
2920 case Intrinsic::mips_mulsa_w_ph:
2921 return LowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH, true, true);
2922 case Intrinsic::mips_mult:
2923 return LowerDSPIntr(Op, DAG, MipsISD::MULT, false, true);
2924 case Intrinsic::mips_multu:
2925 return LowerDSPIntr(Op, DAG, MipsISD::MULTU, false, true);
2926 case Intrinsic::mips_madd:
2927 return LowerDSPIntr(Op, DAG, MipsISD::MADD_DSP, true, true);
2928 case Intrinsic::mips_maddu:
2929 return LowerDSPIntr(Op, DAG, MipsISD::MADDU_DSP, true, true);
2930 case Intrinsic::mips_msub:
2931 return LowerDSPIntr(Op, DAG, MipsISD::MSUB_DSP, true, true);
2932 case Intrinsic::mips_msubu:
2933 return LowerDSPIntr(Op, DAG, MipsISD::MSUBU_DSP, true, true);
2937 SDValue MipsTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
2938 SelectionDAG &DAG) const {
2939 switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) {
2942 case Intrinsic::mips_extp:
2943 return LowerDSPIntr(Op, DAG, MipsISD::EXTP, true, false);
2944 case Intrinsic::mips_extpdp:
2945 return LowerDSPIntr(Op, DAG, MipsISD::EXTPDP, true, false);
2946 case Intrinsic::mips_extr_w:
2947 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_W, true, false);
2948 case Intrinsic::mips_extr_r_w:
2949 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W, true, false);
2950 case Intrinsic::mips_extr_rs_w:
2951 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W, true, false);
2952 case Intrinsic::mips_extr_s_h:
2953 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H, true, false);
2954 case Intrinsic::mips_mthlip:
2955 return LowerDSPIntr(Op, DAG, MipsISD::MTHLIP, true, true);
2956 case Intrinsic::mips_mulsaq_s_w_ph:
2957 return LowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH, true, true);
2958 case Intrinsic::mips_maq_s_w_phl:
2959 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL, true, true);
2960 case Intrinsic::mips_maq_s_w_phr:
2961 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR, true, true);
2962 case Intrinsic::mips_maq_sa_w_phl:
2963 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL, true, true);
2964 case Intrinsic::mips_maq_sa_w_phr:
2965 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR, true, true);
2966 case Intrinsic::mips_dpaq_s_w_ph:
2967 return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH, true, true);
2968 case Intrinsic::mips_dpsq_s_w_ph:
2969 return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH, true, true);
2970 case Intrinsic::mips_dpaq_sa_l_w:
2971 return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W, true, true);
2972 case Intrinsic::mips_dpsq_sa_l_w:
2973 return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W, true, true);
2974 case Intrinsic::mips_dpaqx_s_w_ph:
2975 return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH, true, true);
2976 case Intrinsic::mips_dpaqx_sa_w_ph:
2977 return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH, true, true);
2978 case Intrinsic::mips_dpsqx_s_w_ph:
2979 return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH, true, true);
2980 case Intrinsic::mips_dpsqx_sa_w_ph:
2981 return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH, true, true);
2985 SDValue MipsTargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
2986 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
2987 || cast<ConstantSDNode>
2988 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0
2989 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
2993 // (add (frameaddr 0), (frame_to_args_offset))
2994 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
2995 // (add FrameObject, 0)
2996 // where FrameObject is a fixed StackObject with offset 0 which points to
2997 // the old stack pointer.
2998 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2999 EVT ValTy = Op->getValueType(0);
3000 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
3001 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
3002 return DAG.getNode(ISD::ADD, Op->getDebugLoc(), ValTy, InArgsAddr,
3003 DAG.getConstant(0, ValTy));
3006 //===----------------------------------------------------------------------===//
3007 // Calling Convention Implementation
3008 //===----------------------------------------------------------------------===//
3010 //===----------------------------------------------------------------------===//
3011 // TODO: Implement a generic logic using tblgen that can support this.
3012 // Mips O32 ABI rules:
3014 // i32 - Passed in A0, A1, A2, A3 and stack
3015 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
3016 // an argument. Otherwise, passed in A1, A2, A3 and stack.
3017 // f64 - Only passed in two aliased f32 registers if no int reg has been used
3018 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
3019 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
3022 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
3023 //===----------------------------------------------------------------------===//
3025 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
3026 MVT LocVT, CCValAssign::LocInfo LocInfo,
3027 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3029 static const unsigned IntRegsSize=4, FloatRegsSize=2;
3031 static const uint16_t IntRegs[] = {
3032 Mips::A0, Mips::A1, Mips::A2, Mips::A3
3034 static const uint16_t F32Regs[] = {
3035 Mips::F12, Mips::F14
3037 static const uint16_t F64Regs[] = {
3041 // Do not process byval args here.
3042 if (ArgFlags.isByVal())
3045 // Promote i8 and i16
3046 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
3048 if (ArgFlags.isSExt())
3049 LocInfo = CCValAssign::SExt;
3050 else if (ArgFlags.isZExt())
3051 LocInfo = CCValAssign::ZExt;
3053 LocInfo = CCValAssign::AExt;
3058 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
3059 // is true: function is vararg, argument is 3rd or higher, there is previous
3060 // argument which is not f32 or f64.
3061 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
3062 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
3063 unsigned OrigAlign = ArgFlags.getOrigAlign();
3064 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
3066 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
3067 Reg = State.AllocateReg(IntRegs, IntRegsSize);
3068 // If this is the first part of an i64 arg,
3069 // the allocated register must be either A0 or A2.
3070 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
3071 Reg = State.AllocateReg(IntRegs, IntRegsSize);
3073 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
3074 // Allocate int register and shadow next int register. If first
3075 // available register is Mips::A1 or Mips::A3, shadow it too.
3076 Reg = State.AllocateReg(IntRegs, IntRegsSize);
3077 if (Reg == Mips::A1 || Reg == Mips::A3)
3078 Reg = State.AllocateReg(IntRegs, IntRegsSize);
3079 State.AllocateReg(IntRegs, IntRegsSize);
3081 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
3082 // we are guaranteed to find an available float register
3083 if (ValVT == MVT::f32) {
3084 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
3085 // Shadow int register
3086 State.AllocateReg(IntRegs, IntRegsSize);
3088 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
3089 // Shadow int registers
3090 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
3091 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
3092 State.AllocateReg(IntRegs, IntRegsSize);
3093 State.AllocateReg(IntRegs, IntRegsSize);
3096 llvm_unreachable("Cannot handle this ValVT.");
3099 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
3101 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
3103 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3108 #include "MipsGenCallingConv.inc"
3110 //===----------------------------------------------------------------------===//
3111 // Call Calling Convention Implementation
3112 //===----------------------------------------------------------------------===//
3114 static const unsigned O32IntRegsSize = 4;
3116 // Return next O32 integer argument register.
3117 static unsigned getNextIntArgReg(unsigned Reg) {
3118 assert((Reg == Mips::A0) || (Reg == Mips::A2));
3119 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
3122 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3123 /// for tail call optimization.
3124 bool MipsTargetLowering::
3125 IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
3126 unsigned NextStackOffset,
3127 const MipsFunctionInfo& FI) const {
3128 if (!EnableMipsTailCalls)
3131 // No tail call optimization for mips16.
3132 if (Subtarget->inMips16Mode())
3135 // Return false if either the callee or caller has a byval argument.
3136 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
3139 // Return true if the callee's argument area is no larger than the
3141 return NextStackOffset <= FI.getIncomingArgSize();
3145 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
3146 SDValue Chain, SDValue Arg, DebugLoc DL,
3147 bool IsTailCall, SelectionDAG &DAG) const {
3149 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
3150 DAG.getIntPtrConstant(Offset));
3151 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
3155 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3156 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
3157 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3158 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
3159 /*isVolatile=*/ true, false, 0);
3163 // The Mips16 hard float is a crazy quilt inherited from gcc. I have a much
3164 // cleaner way to do all of this but it will have to wait until the traditional
3165 // gcc mechanism is completed.
3167 // For Pic, in order for Mips16 code to call Mips32 code which according the abi
3168 // have either arguments or returned values placed in floating point registers,
3169 // we use a set of helper functions. (This includes functions which return type
3170 // complex which on Mips are returned in a pair of floating point registers).
3172 // This is an encoding that we inherited from gcc.
3173 // In Mips traditional O32, N32 ABI, floating point numbers are passed in
3174 // floating point argument registers 1,2 only when the first and optionally
3175 // the second arguments are float (sf) or double (df).
3176 // For Mips16 we are only concerned with the situations where floating point
3177 // arguments are being passed in floating point registers by the ABI, because
3178 // Mips16 mode code cannot execute floating point instructions to load those
3179 // values and hence helper functions are needed.
3180 // The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df)
3181 // the helper function suffixs for these are:
3182 // 0, 1, 5, 9, 2, 6, 10
3183 // this suffix can then be calculated as follows:
3184 // for a given argument Arg:
3185 // Arg1x, Arg2x = 1 : Arg is sf
3187 // 0: Arg is neither sf or df
3188 // So this stub is the string for number Arg1x + Arg2x*4.
3189 // However not all numbers between 0 and 10 are possible, we check anyway and
3190 // assert if the impossible exists.
3193 unsigned int MipsTargetLowering::getMips16HelperFunctionStubNumber
3194 (ArgListTy &Args) const {
3195 unsigned int resultNum = 0;
3196 if (Args.size() >= 1) {
3197 Type *t = Args[0].Ty;
3198 if (t->isFloatTy()) {
3201 else if (t->isDoubleTy()) {
3206 if (Args.size() >=2) {
3207 Type *t = Args[1].Ty;
3208 if (t->isFloatTy()) {
3211 else if (t->isDoubleTy()) {
3220 // prefixs are attached to stub numbers depending on the return type .
3221 // return type: float sf_
3223 // single complex sc_
3224 // double complext dc_
3228 // The full name of a helper function is__mips16_call_stub +
3229 // return type dependent prefix + stub number
3232 // This is something that probably should be in a different source file and
3233 // perhaps done differently but my main purpose is to not waste runtime
3234 // on something that we can enumerate in the source. Another possibility is
3235 // to have a python script to generate these mapping tables. This will do
3236 // for now. There are a whole series of helper function mapping arrays, one
3237 // for each return type class as outlined above. There there are 11 possible
3238 // entries. Ones with 0 are ones which should never be selected
3240 // All the arrays are similar except for ones which return neither
3241 // sf, df, sc, dc, in which only care about ones which have sf or df as a
3244 #define P_ "__mips16_call_stub_"
3245 #define MAX_STUB_NUMBER 10
3246 #define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10"
3247 #define T P "0" , T1
3249 static char const * vMips16Helper[MAX_STUB_NUMBER+1] =
3253 static char const * sfMips16Helper[MAX_STUB_NUMBER+1] =
3257 static char const * dfMips16Helper[MAX_STUB_NUMBER+1] =
3261 static char const * scMips16Helper[MAX_STUB_NUMBER+1] =
3265 static char const * dcMips16Helper[MAX_STUB_NUMBER+1] =
3271 const char* MipsTargetLowering::
3272 getMips16HelperFunction
3273 (Type* RetTy, ArgListTy &Args, bool &needHelper) const {
3274 const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args);
3276 const unsigned int maxStubNum = 10;
3277 assert(stubNum <= maxStubNum);
3278 const bool validStubNum[maxStubNum+1] =
3279 {true, true, true, false, false, true, true, false, false, true, true};
3280 assert(validStubNum[stubNum]);
3283 if (RetTy->isFloatTy()) {
3284 result = sfMips16Helper[stubNum];
3286 else if (RetTy ->isDoubleTy()) {
3287 result = dfMips16Helper[stubNum];
3289 else if (RetTy->isStructTy()) {
3290 // check if it's complex
3291 if (RetTy->getNumContainedTypes() == 2) {
3292 if ((RetTy->getContainedType(0)->isFloatTy()) &&
3293 (RetTy->getContainedType(1)->isFloatTy())) {
3294 result = scMips16Helper[stubNum];
3296 else if ((RetTy->getContainedType(0)->isDoubleTy()) &&
3297 (RetTy->getContainedType(1)->isDoubleTy())) {
3298 result = dcMips16Helper[stubNum];
3301 llvm_unreachable("Uncovered condition");
3305 llvm_unreachable("Uncovered condition");
3313 result = vMips16Helper[stubNum];
3319 /// LowerCall - functions arguments are copied from virtual regs to
3320 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
3322 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3323 SmallVectorImpl<SDValue> &InVals) const {
3324 SelectionDAG &DAG = CLI.DAG;
3325 DebugLoc &dl = CLI.DL;
3326 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
3327 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
3328 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
3329 SDValue Chain = CLI.Chain;
3330 SDValue Callee = CLI.Callee;
3331 bool &isTailCall = CLI.IsTailCall;
3332 CallingConv::ID CallConv = CLI.CallConv;
3333 bool isVarArg = CLI.IsVarArg;
3335 const char* mips16HelperFunction = 0;
3336 bool needMips16Helper = false;
3338 if (Subtarget->inMips16Mode() && getTargetMachine().Options.UseSoftFloat &&
3341 // currently we don't have symbols tagged with the mips16 or mips32
3342 // qualifier so we will assume that we don't know what kind it is.
3343 // and generate the helper
3345 bool lookupHelper = true;
3346 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3347 if (noHelperNeeded.find(S->getSymbol()) != noHelperNeeded.end()) {
3348 lookupHelper = false;
3351 if (lookupHelper) mips16HelperFunction =
3352 getMips16HelperFunction(CLI.RetTy, CLI.Args, needMips16Helper);
3355 MachineFunction &MF = DAG.getMachineFunction();
3356 MachineFrameInfo *MFI = MF.getFrameInfo();
3357 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
3358 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
3360 // Analyze operands of the call, assigning locations to each operand.
3361 SmallVector<CCValAssign, 16> ArgLocs;
3362 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3363 getTargetMachine(), ArgLocs, *DAG.getContext());
3364 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo);
3366 MipsCCInfo.analyzeCallOperands(Outs, isVarArg);
3368 // Get a count of how many bytes are to be pushed on the stack.
3369 unsigned NextStackOffset = CCInfo.getNextStackOffset();
3371 // Check if it's really possible to do a tail call.
3374 IsEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset,
3375 *MF.getInfo<MipsFunctionInfo>());
3380 // Chain is the output chain of the last Load/Store or CopyToReg node.
3381 // ByValChain is the output chain of the last Memcpy node created for copying
3382 // byval arguments to the stack.
3383 unsigned StackAlignment = TFL->getStackAlignment();
3384 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
3385 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
3388 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal);
3390 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl,
3391 IsN64 ? Mips::SP_64 : Mips::SP,
3394 // With EABI is it possible to have 16 args on registers.
3395 std::deque< std::pair<unsigned, SDValue> > RegsToPass;
3396 SmallVector<SDValue, 8> MemOpChains;
3397 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
3399 // Walk the register/memloc assignments, inserting copies/loads.
3400 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3401 SDValue Arg = OutVals[i];
3402 CCValAssign &VA = ArgLocs[i];
3403 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
3404 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3407 if (Flags.isByVal()) {
3408 assert(Flags.getByValSize() &&
3409 "ByVal args of size 0 should have been ignored by front-end.");
3410 assert(ByValArg != MipsCCInfo.byval_end());
3411 assert(!isTailCall &&
3412 "Do not tail-call optimize if there is a byval argument.");
3413 passByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3414 MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle());
3419 // Promote the value if needed.
3420 switch (VA.getLocInfo()) {
3421 default: llvm_unreachable("Unknown loc info!");
3422 case CCValAssign::Full:
3423 if (VA.isRegLoc()) {
3424 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3425 (ValVT == MVT::f64 && LocVT == MVT::i64))
3426 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);
3427 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3428 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
3429 Arg, DAG.getConstant(0, MVT::i32));
3430 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
3431 Arg, DAG.getConstant(1, MVT::i32));
3432 if (!Subtarget->isLittle())
3434 unsigned LocRegLo = VA.getLocReg();
3435 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
3436 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
3437 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
3442 case CCValAssign::SExt:
3443 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg);
3445 case CCValAssign::ZExt:
3446 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg);
3448 case CCValAssign::AExt:
3449 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg);
3453 // Arguments that can be passed on register must be kept at
3454 // RegsToPass vector
3455 if (VA.isRegLoc()) {
3456 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3460 // Register can't get to this point...
3461 assert(VA.isMemLoc());
3463 // emit ISD::STORE whichs stores the
3464 // parameter value to a stack Location
3465 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
3466 Chain, Arg, dl, isTailCall, DAG));
3469 // Transform all store nodes into one single node because all store
3470 // nodes are independent of each other.
3471 if (!MemOpChains.empty())
3472 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3473 &MemOpChains[0], MemOpChains.size());
3475 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3476 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3477 // node so that legalize doesn't hack it.
3478 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
3479 bool GlobalOrExternal = false, InternalLinkage = false;
3482 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3484 InternalLinkage = G->getGlobal()->hasInternalLinkage();
3486 if (InternalLinkage)
3487 Callee = getAddrLocal(Callee, DAG, HasMips64);
3489 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16,
3490 MipsII::MO_CALL_LO16);
3492 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL);
3494 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0,
3495 MipsII::MO_NO_FLAG);
3496 GlobalOrExternal = true;
3498 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3499 if (!IsN64 && !IsPIC) // !N64 && static
3500 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3501 MipsII::MO_NO_FLAG);
3503 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16,
3504 MipsII::MO_CALL_LO16);
3506 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL);
3508 GlobalOrExternal = true;
3511 SDValue JumpTarget = Callee;
3513 // T9 should contain the address of the callee function if
3514 // -reloction-model=pic or it is an indirect call.
3515 if (IsPICCall || !GlobalOrExternal) {
3516 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
3517 unsigned V0Reg = Mips::V0;
3518 if (needMips16Helper) {
3519 RegsToPass.push_front(std::make_pair(V0Reg, Callee));
3520 JumpTarget = DAG.getExternalSymbol(
3521 mips16HelperFunction, getPointerTy());
3522 JumpTarget = getAddrGlobal(JumpTarget, DAG, MipsII::MO_GOT);
3525 RegsToPass.push_front(std::make_pair(T9Reg, Callee));
3527 if (!Subtarget->inMips16Mode())
3528 JumpTarget = SDValue();
3532 // Insert node "GP copy globalreg" before call to function.
3534 // R_MIPS_CALL* operators (emitted when non-internal functions are called
3535 // in PIC mode) allow symbols to be resolved via lazy binding.
3536 // The lazy binding stub requires GP to point to the GOT.
3537 if (IsPICCall && !InternalLinkage) {
3538 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP;
3539 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
3540 RegsToPass.push_back(std::make_pair(GPReg, GetGlobalReg(DAG, Ty)));
3543 // Build a sequence of copy-to-reg nodes chained together with token
3544 // chain and flag operands which copy the outgoing args into registers.
3545 // The InFlag in necessary since all emitted instructions must be
3549 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3550 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3551 RegsToPass[i].second, InFlag);
3552 InFlag = Chain.getValue(1);
3555 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
3556 // = Chain, Callee, Reg#1, Reg#2, ...
3558 // Returns a chain & a flag for retval copy to use.
3559 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3560 SmallVector<SDValue, 8> Ops(1, Chain);
3562 if (JumpTarget.getNode())
3563 Ops.push_back(JumpTarget);
3565 // Add argument registers to the end of the list so that they are
3566 // known live into the call.
3567 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3568 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3569 RegsToPass[i].second.getValueType()));
3571 // Add a register mask operand representing the call-preserved registers.
3572 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3573 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3574 assert(Mask && "Missing call preserved mask for calling convention");
3575 Ops.push_back(DAG.getRegisterMask(Mask));
3577 if (InFlag.getNode())
3578 Ops.push_back(InFlag);
3581 return DAG.getNode(MipsISD::TailCall, dl, MVT::Other, &Ops[0], Ops.size());
3583 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
3584 InFlag = Chain.getValue(1);
3586 // Create the CALLSEQ_END node.
3587 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
3588 DAG.getIntPtrConstant(0, true), InFlag);
3589 InFlag = Chain.getValue(1);
3591 // Handle result values, copying them out of physregs into vregs that we
3593 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3594 Ins, dl, DAG, InVals);
3597 /// LowerCallResult - Lower the result values of a call into the
3598 /// appropriate copies out of appropriate physical registers.
3600 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3601 CallingConv::ID CallConv, bool isVarArg,
3602 const SmallVectorImpl<ISD::InputArg> &Ins,
3603 DebugLoc dl, SelectionDAG &DAG,
3604 SmallVectorImpl<SDValue> &InVals) const {
3605 // Assign locations to each value returned by this call.
3606 SmallVector<CCValAssign, 16> RVLocs;
3607 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3608 getTargetMachine(), RVLocs, *DAG.getContext());
3610 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
3612 // Copy all of the result registers out of their specified physreg.
3613 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3614 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
3615 RVLocs[i].getValVT(), InFlag).getValue(1);
3616 InFlag = Chain.getValue(2);
3617 InVals.push_back(Chain.getValue(0));
3623 //===----------------------------------------------------------------------===//
3624 // Formal Arguments Calling Convention Implementation
3625 //===----------------------------------------------------------------------===//
3626 /// LowerFormalArguments - transform physical registers into virtual registers
3627 /// and generate load operations for arguments places on the stack.
3629 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
3630 CallingConv::ID CallConv,
3632 const SmallVectorImpl<ISD::InputArg> &Ins,
3633 DebugLoc dl, SelectionDAG &DAG,
3634 SmallVectorImpl<SDValue> &InVals)
3636 MachineFunction &MF = DAG.getMachineFunction();
3637 MachineFrameInfo *MFI = MF.getFrameInfo();
3638 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3640 MipsFI->setVarArgsFrameIndex(0);
3642 // Used with vargs to acumulate store chains.
3643 std::vector<SDValue> OutChains;
3645 // Assign locations to all of the incoming arguments.
3646 SmallVector<CCValAssign, 16> ArgLocs;
3647 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3648 getTargetMachine(), ArgLocs, *DAG.getContext());
3649 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo);
3651 MipsCCInfo.analyzeFormalArguments(Ins);
3652 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
3653 MipsCCInfo.hasByValArg());
3655 Function::const_arg_iterator FuncArg =
3656 DAG.getMachineFunction().getFunction()->arg_begin();
3657 unsigned CurArgIdx = 0;
3658 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
3660 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3661 CCValAssign &VA = ArgLocs[i];
3662 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx);
3663 CurArgIdx = Ins[i].OrigArgIndex;
3664 EVT ValVT = VA.getValVT();
3665 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3666 bool IsRegLoc = VA.isRegLoc();
3668 if (Flags.isByVal()) {
3669 assert(Flags.getByValSize() &&
3670 "ByVal args of size 0 should have been ignored by front-end.");
3671 assert(ByValArg != MipsCCInfo.byval_end());
3672 copyByValRegs(Chain, dl, OutChains, DAG, Flags, InVals, &*FuncArg,
3673 MipsCCInfo, *ByValArg);
3678 // Arguments stored on registers
3680 EVT RegVT = VA.getLocVT();
3681 unsigned ArgReg = VA.getLocReg();
3682 const TargetRegisterClass *RC;
3684 if (RegVT == MVT::i32)
3685 RC = Subtarget->inMips16Mode()? &Mips::CPU16RegsRegClass :
3686 &Mips::CPURegsRegClass;
3687 else if (RegVT == MVT::i64)
3688 RC = &Mips::CPU64RegsRegClass;
3689 else if (RegVT == MVT::f32)
3690 RC = &Mips::FGR32RegClass;
3691 else if (RegVT == MVT::f64)
3692 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
3694 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
3696 // Transform the arguments stored on
3697 // physical registers into virtual ones
3698 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3699 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3701 // If this is an 8 or 16-bit value, it has been passed promoted
3702 // to 32 bits. Insert an assert[sz]ext to capture this, then
3703 // truncate to the right size.
3704 if (VA.getLocInfo() != CCValAssign::Full) {
3705 unsigned Opcode = 0;
3706 if (VA.getLocInfo() == CCValAssign::SExt)
3707 Opcode = ISD::AssertSext;
3708 else if (VA.getLocInfo() == CCValAssign::ZExt)
3709 Opcode = ISD::AssertZext;
3711 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
3712 DAG.getValueType(ValVT));
3713 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue);
3716 // Handle floating point arguments passed in integer registers.
3717 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3718 (RegVT == MVT::i64 && ValVT == MVT::f64))
3719 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue);
3720 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
3721 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
3722 getNextIntArgReg(ArgReg), RC);
3723 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
3724 if (!Subtarget->isLittle())
3725 std::swap(ArgValue, ArgValue2);
3726 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
3727 ArgValue, ArgValue2);
3730 InVals.push_back(ArgValue);
3731 } else { // VA.isRegLoc()
3734 assert(VA.isMemLoc());
3736 // The stack pointer offset is relative to the caller stack frame.
3737 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
3738 VA.getLocMemOffset(), true);
3740 // Create load nodes to retrieve arguments from the stack
3741 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3742 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN,
3743 MachinePointerInfo::getFixedStack(FI),
3744 false, false, false, 0));
3748 // The mips ABIs for returning structs by value requires that we copy
3749 // the sret argument into $v0 for the return. Save the argument into
3750 // a virtual register so that we can access it from the return points.
3751 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3752 unsigned Reg = MipsFI->getSRetReturnReg();
3754 Reg = MF.getRegInfo().
3755 createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32));
3756 MipsFI->setSRetReturnReg(Reg);
3758 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
3759 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
3763 writeVarArgRegs(OutChains, MipsCCInfo, Chain, dl, DAG);
3765 // All stores are grouped in one node to allow the matching between
3766 // the size of Ins and InVals. This only happens when on varg functions
3767 if (!OutChains.empty()) {
3768 OutChains.push_back(Chain);
3769 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3770 &OutChains[0], OutChains.size());
3776 //===----------------------------------------------------------------------===//
3777 // Return Value Calling Convention Implementation
3778 //===----------------------------------------------------------------------===//
3781 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3782 MachineFunction &MF, bool isVarArg,
3783 const SmallVectorImpl<ISD::OutputArg> &Outs,
3784 LLVMContext &Context) const {
3785 SmallVector<CCValAssign, 16> RVLocs;
3786 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
3788 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3792 MipsTargetLowering::LowerReturn(SDValue Chain,
3793 CallingConv::ID CallConv, bool isVarArg,
3794 const SmallVectorImpl<ISD::OutputArg> &Outs,
3795 const SmallVectorImpl<SDValue> &OutVals,
3796 DebugLoc dl, SelectionDAG &DAG) const {
3798 // CCValAssign - represent the assignment of
3799 // the return value to a location
3800 SmallVector<CCValAssign, 16> RVLocs;
3802 // CCState - Info about the registers and stack slot.
3803 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3804 getTargetMachine(), RVLocs, *DAG.getContext());
3806 // Analize return values.
3807 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3810 SmallVector<SDValue, 4> RetOps(1, Chain);
3812 // Copy the result values into the output registers.
3813 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3814 CCValAssign &VA = RVLocs[i];
3815 assert(VA.isRegLoc() && "Can only return in registers!");
3817 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
3819 // Guarantee that all emitted copies are stuck together with flags.
3820 Flag = Chain.getValue(1);
3821 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3824 // The mips ABIs for returning structs by value requires that we copy
3825 // the sret argument into $v0 for the return. We saved the argument into
3826 // a virtual register in the entry block, so now we copy the value out
3828 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3829 MachineFunction &MF = DAG.getMachineFunction();
3830 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3831 unsigned Reg = MipsFI->getSRetReturnReg();
3834 llvm_unreachable("sret virtual register not created in the entry block");
3835 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
3836 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0;
3838 Chain = DAG.getCopyToReg(Chain, dl, V0, Val, Flag);
3839 Flag = Chain.getValue(1);
3840 RetOps.push_back(DAG.getRegister(V0, getPointerTy()));
3843 RetOps[0] = Chain; // Update chain.
3845 // Add the flag if we have it.
3847 RetOps.push_back(Flag);
3849 // Return on Mips is always a "jr $ra"
3850 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, &RetOps[0], RetOps.size());
3853 //===----------------------------------------------------------------------===//
3854 // Mips Inline Assembly Support
3855 //===----------------------------------------------------------------------===//
3857 /// getConstraintType - Given a constraint letter, return the type of
3858 /// constraint it is for this target.
3859 MipsTargetLowering::ConstraintType MipsTargetLowering::
3860 getConstraintType(const std::string &Constraint) const
3862 // Mips specific constrainy
3863 // GCC config/mips/constraints.md
3865 // 'd' : An address register. Equivalent to r
3866 // unless generating MIPS16 code.
3867 // 'y' : Equivalent to r; retained for
3868 // backwards compatibility.
3869 // 'c' : A register suitable for use in an indirect
3870 // jump. This will always be $25 for -mabicalls.
3871 // 'l' : The lo register. 1 word storage.
3872 // 'x' : The hilo register pair. Double word storage.
3873 if (Constraint.size() == 1) {
3874 switch (Constraint[0]) {
3882 return C_RegisterClass;
3885 return TargetLowering::getConstraintType(Constraint);
3888 /// Examine constraint type and operand type and determine a weight value.
3889 /// This object must already have been set up with the operand type
3890 /// and the current alternative constraint selected.
3891 TargetLowering::ConstraintWeight
3892 MipsTargetLowering::getSingleConstraintMatchWeight(
3893 AsmOperandInfo &info, const char *constraint) const {
3894 ConstraintWeight weight = CW_Invalid;
3895 Value *CallOperandVal = info.CallOperandVal;
3896 // If we don't have a value, we can't do a match,
3897 // but allow it at the lowest weight.
3898 if (CallOperandVal == NULL)
3900 Type *type = CallOperandVal->getType();
3901 // Look at the constraint type.
3902 switch (*constraint) {
3904 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3908 if (type->isIntegerTy())
3909 weight = CW_Register;
3912 if (type->isFloatTy())
3913 weight = CW_Register;
3915 case 'c': // $25 for indirect jumps
3916 case 'l': // lo register
3917 case 'x': // hilo register pair
3918 if (type->isIntegerTy())
3919 weight = CW_SpecificReg;
3921 case 'I': // signed 16 bit immediate
3922 case 'J': // integer zero
3923 case 'K': // unsigned 16 bit immediate
3924 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3925 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3926 case 'O': // signed 15 bit immediate (+- 16383)
3927 case 'P': // immediate in the range of 65535 to 1 (inclusive)
3928 if (isa<ConstantInt>(CallOperandVal))
3929 weight = CW_Constant;
3935 /// Given a register class constraint, like 'r', if this corresponds directly
3936 /// to an LLVM register class, return a register of 0 and the register class
3938 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
3939 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
3941 if (Constraint.size() == 1) {
3942 switch (Constraint[0]) {
3943 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3944 case 'y': // Same as 'r'. Exists for compatibility.
3946 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3947 if (Subtarget->inMips16Mode())
3948 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3949 return std::make_pair(0U, &Mips::CPURegsRegClass);
3951 if (VT == MVT::i64 && !HasMips64)
3952 return std::make_pair(0U, &Mips::CPURegsRegClass);
3953 if (VT == MVT::i64 && HasMips64)
3954 return std::make_pair(0U, &Mips::CPU64RegsRegClass);
3955 // This will generate an error message
3956 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
3959 return std::make_pair(0U, &Mips::FGR32RegClass);
3960 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
3961 if (Subtarget->isFP64bit())
3962 return std::make_pair(0U, &Mips::FGR64RegClass);
3963 return std::make_pair(0U, &Mips::AFGR64RegClass);
3966 case 'c': // register suitable for indirect jump
3968 return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass);
3969 assert(VT == MVT::i64 && "Unexpected type.");
3970 return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass);
3971 case 'l': // register suitable for indirect jump
3973 return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass);
3974 return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass);
3975 case 'x': // register suitable for indirect jump
3976 // Fixme: Not triggering the use of both hi and low
3977 // This will generate an error message
3978 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
3981 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3984 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3985 /// vector. If it is invalid, don't add anything to Ops.
3986 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3987 std::string &Constraint,
3988 std::vector<SDValue>&Ops,
3989 SelectionDAG &DAG) const {
3990 SDValue Result(0, 0);
3992 // Only support length 1 constraints for now.
3993 if (Constraint.length() > 1) return;
3995 char ConstraintLetter = Constraint[0];
3996 switch (ConstraintLetter) {
3997 default: break; // This will fall through to the generic implementation
3998 case 'I': // Signed 16 bit constant
3999 // If this fails, the parent routine will give an error
4000 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4001 EVT Type = Op.getValueType();
4002 int64_t Val = C->getSExtValue();
4003 if (isInt<16>(Val)) {
4004 Result = DAG.getTargetConstant(Val, Type);
4009 case 'J': // integer zero
4010 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4011 EVT Type = Op.getValueType();
4012 int64_t Val = C->getZExtValue();
4014 Result = DAG.getTargetConstant(0, Type);
4019 case 'K': // unsigned 16 bit immediate
4020 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4021 EVT Type = Op.getValueType();
4022 uint64_t Val = (uint64_t)C->getZExtValue();
4023 if (isUInt<16>(Val)) {
4024 Result = DAG.getTargetConstant(Val, Type);
4029 case 'L': // signed 32 bit immediate where lower 16 bits are 0
4030 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4031 EVT Type = Op.getValueType();
4032 int64_t Val = C->getSExtValue();
4033 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
4034 Result = DAG.getTargetConstant(Val, Type);
4039 case 'N': // immediate in the range of -65535 to -1 (inclusive)
4040 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4041 EVT Type = Op.getValueType();
4042 int64_t Val = C->getSExtValue();
4043 if ((Val >= -65535) && (Val <= -1)) {
4044 Result = DAG.getTargetConstant(Val, Type);
4049 case 'O': // signed 15 bit immediate
4050 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4051 EVT Type = Op.getValueType();
4052 int64_t Val = C->getSExtValue();
4053 if ((isInt<15>(Val))) {
4054 Result = DAG.getTargetConstant(Val, Type);
4059 case 'P': // immediate in the range of 1 to 65535 (inclusive)
4060 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4061 EVT Type = Op.getValueType();
4062 int64_t Val = C->getSExtValue();
4063 if ((Val <= 65535) && (Val >= 1)) {
4064 Result = DAG.getTargetConstant(Val, Type);
4071 if (Result.getNode()) {
4072 Ops.push_back(Result);
4076 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4080 MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const {
4081 // No global is ever allowed as a base.
4086 case 0: // "r+i" or just "i", depending on HasBaseReg.
4089 if (!AM.HasBaseReg) // allow "r+i".
4091 return false; // disallow "r+r" or "r+r+i".
4100 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4101 // The Mips target isn't yet aware of offsets.
4105 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
4107 bool IsMemset, bool ZeroMemset,
4109 MachineFunction &MF) const {
4110 if (Subtarget->hasMips64())
4116 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4117 if (VT != MVT::f32 && VT != MVT::f64)
4119 if (Imm.isNegZero())
4121 return Imm.isZero();
4124 unsigned MipsTargetLowering::getJumpTableEncoding() const {
4126 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
4128 return TargetLowering::getJumpTableEncoding();
4131 MipsTargetLowering::MipsCC::MipsCC(CallingConv::ID CC, bool IsO32_,
4133 : CCInfo(Info), CallConv(CC), IsO32(IsO32_) {
4134 // Pre-allocate reserved argument area.
4135 CCInfo.AllocateStack(reservedArgArea(), 1);
4138 void MipsTargetLowering::MipsCC::
4139 analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args,
4141 assert((CallConv != CallingConv::Fast || !IsVarArg) &&
4142 "CallingConv::Fast shouldn't be used for vararg functions.");
4144 unsigned NumOpnds = Args.size();
4145 llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn();
4147 for (unsigned I = 0; I != NumOpnds; ++I) {
4148 MVT ArgVT = Args[I].VT;
4149 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
4152 if (ArgFlags.isByVal()) {
4153 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
4157 if (IsVarArg && !Args[I].IsFixed)
4158 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
4160 R = FixedFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
4164 dbgs() << "Call operand #" << I << " has unhandled type "
4165 << EVT(ArgVT).getEVTString();
4167 llvm_unreachable(0);
4172 void MipsTargetLowering::MipsCC::
4173 analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args) {
4174 unsigned NumArgs = Args.size();
4175 llvm::CCAssignFn *FixedFn = fixedArgFn();
4177 for (unsigned I = 0; I != NumArgs; ++I) {
4178 MVT ArgVT = Args[I].VT;
4179 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
4181 if (ArgFlags.isByVal()) {
4182 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
4186 if (!FixedFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo))
4190 dbgs() << "Formal Arg #" << I << " has unhandled type "
4191 << EVT(ArgVT).getEVTString();
4193 llvm_unreachable(0);
4198 MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
4200 CCValAssign::LocInfo LocInfo,
4201 ISD::ArgFlagsTy ArgFlags) {
4202 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0.");
4204 struct ByValArgInfo ByVal;
4205 unsigned RegSize = regSize();
4206 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize);
4207 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize),
4210 if (useRegsForByval())
4211 allocateRegs(ByVal, ByValSize, Align);
4213 // Allocate space on caller's stack.
4214 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs,
4216 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT,
4218 ByValArgs.push_back(ByVal);
4221 unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const {
4222 return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs);
4225 unsigned MipsTargetLowering::MipsCC::reservedArgArea() const {
4226 return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0;
4229 const uint16_t *MipsTargetLowering::MipsCC::intArgRegs() const {
4230 return IsO32 ? O32IntRegs : Mips64IntRegs;
4233 llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const {
4234 if (CallConv == CallingConv::Fast)
4235 return CC_Mips_FastCC;
4237 return IsO32 ? CC_MipsO32 : CC_MipsN;
4240 llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const {
4241 return IsO32 ? CC_MipsO32 : CC_MipsN_VarArg;
4244 const uint16_t *MipsTargetLowering::MipsCC::shadowRegs() const {
4245 return IsO32 ? O32IntRegs : Mips64DPRegs;
4248 void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
4251 unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs();
4252 const uint16_t *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs();
4253 assert(!(ByValSize % RegSize) && !(Align % RegSize) &&
4254 "Byval argument's size and alignment should be a multiple of"
4257 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs);
4259 // If Align > RegSize, the first arg register must be even.
4260 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) {
4261 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]);
4265 // Mark the registers allocated.
4266 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs);
4267 ByValSize -= RegSize, ++I, ++ByVal.NumRegs)
4268 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]);
4271 void MipsTargetLowering::
4272 copyByValRegs(SDValue Chain, DebugLoc DL, std::vector<SDValue> &OutChains,
4273 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
4274 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
4275 const MipsCC &CC, const ByValArgInfo &ByVal) const {
4276 MachineFunction &MF = DAG.getMachineFunction();
4277 MachineFrameInfo *MFI = MF.getFrameInfo();
4278 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize();
4279 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
4283 FrameObjOffset = (int)CC.reservedArgArea() -
4284 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize());
4286 FrameObjOffset = ByVal.Address;
4288 // Create frame object.
4289 EVT PtrTy = getPointerTy();
4290 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
4291 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4292 InVals.push_back(FIN);
4297 // Copy arg registers.
4298 MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
4299 const TargetRegisterClass *RC = getRegClassFor(RegTy);
4301 for (unsigned I = 0; I < ByVal.NumRegs; ++I) {
4302 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I];
4303 unsigned VReg = AddLiveIn(MF, ArgReg, RC);
4304 unsigned Offset = I * CC.regSize();
4305 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
4306 DAG.getConstant(Offset, PtrTy));
4307 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
4308 StorePtr, MachinePointerInfo(FuncArg, Offset),
4310 OutChains.push_back(Store);
4314 // Copy byVal arg to registers and stack.
4315 void MipsTargetLowering::
4316 passByValArg(SDValue Chain, DebugLoc DL,
4317 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
4318 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
4319 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
4320 const MipsCC &CC, const ByValArgInfo &ByVal,
4321 const ISD::ArgFlagsTy &Flags, bool isLittle) const {
4322 unsigned ByValSize = Flags.getByValSize();
4323 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
4324 unsigned RegSize = CC.regSize();
4325 unsigned Alignment = std::min(Flags.getByValAlign(), RegSize);
4326 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8);
4328 if (ByVal.NumRegs) {
4329 const uint16_t *ArgRegs = CC.intArgRegs();
4330 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize);
4333 // Copy words to registers.
4334 for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) {
4335 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4336 DAG.getConstant(Offset, PtrTy));
4337 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
4338 MachinePointerInfo(), false, false, false,
4340 MemOpChains.push_back(LoadVal.getValue(1));
4341 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
4342 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
4345 // Return if the struct has been fully copied.
4346 if (ByValSize == Offset)
4349 // Copy the remainder of the byval argument with sub-word loads and shifts.
4350 if (LeftoverBytes) {
4351 assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) &&
4352 "Size of the remainder should be smaller than RegSize.");
4355 for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0;
4356 Offset < ByValSize; LoadSize /= 2) {
4357 unsigned RemSize = ByValSize - Offset;
4359 if (RemSize < LoadSize)
4363 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4364 DAG.getConstant(Offset, PtrTy));
4366 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr,
4367 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
4368 false, false, Alignment);
4369 MemOpChains.push_back(LoadVal.getValue(1));
4371 // Shift the loaded value.
4375 Shamt = TotalSizeLoaded;
4377 Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8;
4379 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
4380 DAG.getConstant(Shamt, MVT::i32));
4383 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
4388 TotalSizeLoaded += LoadSize;
4389 Alignment = std::min(Alignment, LoadSize);
4392 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
4393 RegsToPass.push_back(std::make_pair(ArgReg, Val));
4398 // Copy remainder of byval arg to it with memcpy.
4399 unsigned MemCpySize = ByValSize - Offset;
4400 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4401 DAG.getConstant(Offset, PtrTy));
4402 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
4403 DAG.getIntPtrConstant(ByVal.Address));
4404 Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
4405 DAG.getConstant(MemCpySize, PtrTy), Alignment,
4406 /*isVolatile=*/false, /*AlwaysInline=*/false,
4407 MachinePointerInfo(0), MachinePointerInfo(0));
4408 MemOpChains.push_back(Chain);
4412 MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4413 const MipsCC &CC, SDValue Chain,
4414 DebugLoc DL, SelectionDAG &DAG) const {
4415 unsigned NumRegs = CC.numIntArgRegs();
4416 const uint16_t *ArgRegs = CC.intArgRegs();
4417 const CCState &CCInfo = CC.getCCInfo();
4418 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs);
4419 unsigned RegSize = CC.regSize();
4420 MVT RegTy = MVT::getIntegerVT(RegSize * 8);
4421 const TargetRegisterClass *RC = getRegClassFor(RegTy);
4422 MachineFunction &MF = DAG.getMachineFunction();
4423 MachineFrameInfo *MFI = MF.getFrameInfo();
4424 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
4426 // Offset of the first variable argument from stack pointer.
4430 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize);
4433 (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx));
4435 // Record the frame index of the first variable argument
4436 // which is a value necessary to VASTART.
4437 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
4438 MipsFI->setVarArgsFrameIndex(FI);
4440 // Copy the integer registers that have not been used for argument passing
4441 // to the argument register save area. For O32, the save area is allocated
4442 // in the caller's stack frame, while for N32/64, it is allocated in the
4443 // callee's stack frame.
4444 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) {
4445 unsigned Reg = AddLiveIn(MF, ArgRegs[I], RC);
4446 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
4447 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
4448 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
4449 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
4450 MachinePointerInfo(), false, false, 0);
4451 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0);
4452 OutChains.push_back(Store);