1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
39 const char *MipsTargetLowering::
40 getTargetNodeName(unsigned Opcode) const
44 case MipsISD::JmpLink : return "MipsISD::JmpLink";
45 case MipsISD::Hi : return "MipsISD::Hi";
46 case MipsISD::Lo : return "MipsISD::Lo";
47 case MipsISD::GPRel : return "MipsISD::GPRel";
48 case MipsISD::Ret : return "MipsISD::Ret";
49 case MipsISD::CMov : return "MipsISD::CMov";
50 case MipsISD::SelectCC : return "MipsISD::SelectCC";
51 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
52 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
53 case MipsISD::FPCmp : return "MipsISD::FPCmp";
54 default : return NULL;
59 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
61 Subtarget = &TM.getSubtarget<MipsSubtarget>();
63 // Mips does not have i1 type, so use i32 for
64 // setcc operations results (slt, sgt, ...).
65 setSetCCResultContents(ZeroOrOneSetCCResult);
67 // JumpTable targets must use GOT when using PIC_
68 setUsesGlobalOffsetTable(true);
70 // Set up the register classes
71 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
73 // When dealing with single precision only, use libcalls
74 if (!Subtarget->isSingleFloat()) {
75 addRegisterClass(MVT::f32, Mips::AFGR32RegisterClass);
76 if (!Subtarget->isFP64bit())
77 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
79 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
82 addLegalFPImmediate(APFloat(+0.0f));
84 // Load extented operations for i1 types must be promoted
85 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
86 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
87 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
89 // Used by legalize types to correctly generate the setcc result.
90 // Without this, every float setcc comes with a AND/OR with the result,
91 // we don't want this, since the fpcmp result goes to a flag register,
92 // which is used implicitly by brcond and select operations.
93 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
95 // Mips Custom Operations
96 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
97 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
98 setOperationAction(ISD::RET, MVT::Other, Custom);
99 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
100 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
101 setOperationAction(ISD::SELECT, MVT::f32, Custom);
102 setOperationAction(ISD::SELECT, MVT::i32, Custom);
103 setOperationAction(ISD::SETCC, MVT::f32, Custom);
104 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
105 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
107 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
108 // with operands comming from setcc fp comparions. This is necessary since
109 // the result from these setcc are in a flag registers (FCR31).
110 setOperationAction(ISD::AND, MVT::i32, Custom);
111 setOperationAction(ISD::OR, MVT::i32, Custom);
113 // Operations not directly supported by Mips.
114 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
115 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
116 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
117 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
118 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
120 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
121 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
122 setOperationAction(ISD::ROTL, MVT::i32, Expand);
123 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
124 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
125 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
126 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
128 // We don't have line number support yet.
129 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
130 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
131 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
132 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
134 // Use the default for now
135 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
136 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
137 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
139 if (Subtarget->isSingleFloat())
140 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
142 if (!Subtarget->hasSEInReg()) {
143 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
144 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
147 if (!Subtarget->hasBitCount())
148 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
150 if (!Subtarget->hasSwap())
151 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
153 setStackPointerRegisterToSaveRestore(Mips::SP);
154 computeRegisterProperties();
158 MVT MipsTargetLowering::getSetCCResultType(const SDValue &) const {
163 SDValue MipsTargetLowering::
164 LowerOperation(SDValue Op, SelectionDAG &DAG)
166 switch (Op.getOpcode())
168 case ISD::AND: return LowerANDOR(Op, DAG);
169 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
170 case ISD::CALL: return LowerCALL(Op, DAG);
171 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
172 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
173 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
174 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
175 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
176 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
177 case ISD::OR: return LowerANDOR(Op, DAG);
178 case ISD::RET: return LowerRET(Op, DAG);
179 case ISD::SELECT: return LowerSELECT(Op, DAG);
180 case ISD::SETCC: return LowerSETCC(Op, DAG);
185 //===----------------------------------------------------------------------===//
186 // Lower helper functions
187 //===----------------------------------------------------------------------===//
189 // AddLiveIn - This helper function adds the specified physical register to the
190 // MachineFunction as a live in value. It also creates a corresponding
191 // virtual register for it.
193 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
195 assert(RC->contains(PReg) && "Not the correct regclass!");
196 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
197 MF.getRegInfo().addLiveIn(PReg, VReg);
201 // A address must be loaded from a small section if its size is less than the
202 // small section size threshold. Data in this section must be addressed using
204 bool MipsTargetLowering::IsInSmallSection(unsigned Size) {
205 return (Size > 0 && (Size <= Subtarget->getSSectionThreshold()));
208 // Discover if this global address can be placed into small data/bss section.
209 bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV)
211 const TargetData *TD = getTargetData();
212 const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV);
217 const Type *Ty = GV->getType()->getElementType();
218 unsigned Size = TD->getABITypeSize(Ty);
220 // if this is a internal constant string, there is a special
221 // section for it, but not in small data/bss.
222 if (GVA->hasInitializer() && GV->hasInternalLinkage()) {
223 Constant *C = GVA->getInitializer();
224 const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
225 if (CVA && CVA->isCString())
229 return IsInSmallSection(Size);
232 // Get fp branch code (not opcode) from condition code.
233 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
234 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
235 return Mips::BRANCH_T;
237 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
238 return Mips::BRANCH_F;
240 return Mips::BRANCH_INVALID;
243 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
246 assert(0 && "Unknown branch code");
247 case Mips::BRANCH_T : return Mips::BC1T;
248 case Mips::BRANCH_F : return Mips::BC1F;
249 case Mips::BRANCH_TL : return Mips::BC1TL;
250 case Mips::BRANCH_FL : return Mips::BC1FL;
254 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
256 default: assert(0 && "Unknown fp condition code!");
258 case ISD::SETOEQ: return Mips::FCOND_EQ;
259 case ISD::SETUNE: return Mips::FCOND_OGL;
261 case ISD::SETOLT: return Mips::FCOND_OLT;
263 case ISD::SETOGT: return Mips::FCOND_OGT;
265 case ISD::SETOLE: return Mips::FCOND_OLE;
267 case ISD::SETOGE: return Mips::FCOND_OGE;
268 case ISD::SETULT: return Mips::FCOND_ULT;
269 case ISD::SETULE: return Mips::FCOND_ULE;
270 case ISD::SETUGT: return Mips::FCOND_UGT;
271 case ISD::SETUGE: return Mips::FCOND_UGE;
272 case ISD::SETUO: return Mips::FCOND_UN;
273 case ISD::SETO: return Mips::FCOND_OR;
275 case ISD::SETONE: return Mips::FCOND_NEQ;
276 case ISD::SETUEQ: return Mips::FCOND_UEQ;
281 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
282 MachineBasicBlock *BB)
284 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
285 bool isFPCmp = false;
287 switch (MI->getOpcode()) {
288 default: assert(false && "Unexpected instr type to insert");
289 case Mips::Select_FCC:
290 case Mips::Select_FCC_SO32:
291 case Mips::Select_FCC_AS32:
292 case Mips::Select_FCC_D32:
293 isFPCmp = true; // FALL THROUGH
294 case Mips::Select_CC:
295 case Mips::Select_CC_SO32:
296 case Mips::Select_CC_AS32:
297 case Mips::Select_CC_D32: {
298 // To "insert" a SELECT_CC instruction, we actually have to insert the
299 // diamond control-flow pattern. The incoming instruction knows the
300 // destination vreg to set, the condition code register to branch on, the
301 // true/false values to select between, and a branch opcode to use.
302 const BasicBlock *LLVM_BB = BB->getBasicBlock();
303 MachineFunction::iterator It = BB;
310 // bNE r1, r0, copy1MBB
311 // fallthrough --> copy0MBB
312 MachineBasicBlock *thisMBB = BB;
313 MachineFunction *F = BB->getParent();
314 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
315 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
317 // Emit the right instruction according to the type of the operands compared
319 // Find the condiction code present in the setcc operation.
320 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
321 // Get the branch opcode from the branch code.
322 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
323 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
325 BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
326 .addReg(Mips::ZERO).addMBB(sinkMBB);
328 F->insert(It, copy0MBB);
329 F->insert(It, sinkMBB);
330 // Update machine-CFG edges by first adding all successors of the current
331 // block to the new block which will contain the Phi node for the select.
332 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
333 e = BB->succ_end(); i != e; ++i)
334 sinkMBB->addSuccessor(*i);
335 // Next, remove all successors of the current block, and add the true
336 // and fallthrough blocks as its successors.
337 while(!BB->succ_empty())
338 BB->removeSuccessor(BB->succ_begin());
339 BB->addSuccessor(copy0MBB);
340 BB->addSuccessor(sinkMBB);
344 // # fallthrough to sinkMBB
347 // Update machine-CFG edges
348 BB->addSuccessor(sinkMBB);
351 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
354 BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg())
355 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
356 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
358 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
364 //===----------------------------------------------------------------------===//
365 // Misc Lower Operation implementation
366 //===----------------------------------------------------------------------===//
368 SDValue MipsTargetLowering::
369 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
371 SDValue Chain = Op.getOperand(0);
372 SDValue Size = Op.getOperand(1);
374 // Get a reference from Mips stack pointer
375 SDValue StackPointer = DAG.getCopyFromReg(Chain, Mips::SP, MVT::i32);
377 // Subtract the dynamic size from the actual stack size to
378 // obtain the new stack size.
379 SDValue Sub = DAG.getNode(ISD::SUB, MVT::i32, StackPointer, Size);
381 // The Sub result contains the new stack start address, so it
382 // must be placed in the stack pointer register.
383 Chain = DAG.getCopyToReg(StackPointer.getValue(1), Mips::SP, Sub);
385 // This node always has two return values: a new stack pointer
387 SDValue Ops[2] = { Sub, Chain };
388 return DAG.getMergeValues(Ops, 2);
391 SDValue MipsTargetLowering::
392 LowerANDOR(SDValue Op, SelectionDAG &DAG)
394 SDValue LHS = Op.getOperand(0);
395 SDValue RHS = Op.getOperand(1);
397 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
400 SDValue True = DAG.getConstant(1, MVT::i32);
401 SDValue False = DAG.getConstant(0, MVT::i32);
403 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
404 LHS, True, False, LHS.getOperand(2));
405 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
406 RHS, True, False, RHS.getOperand(2));
408 return DAG.getNode(Op.getOpcode(), MVT::i32, LSEL, RSEL);
411 SDValue MipsTargetLowering::
412 LowerBRCOND(SDValue Op, SelectionDAG &DAG)
414 // The first operand is the chain, the second is the condition, the third is
415 // the block to branch to if the condition is true.
416 SDValue Chain = Op.getOperand(0);
417 SDValue Dest = Op.getOperand(2);
419 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
422 SDValue CondRes = Op.getOperand(1);
423 SDValue CCNode = CondRes.getOperand(2);
425 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
426 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
428 return DAG.getNode(MipsISD::FPBrcond, Op.getValueType(), Chain, BrCode,
432 SDValue MipsTargetLowering::
433 LowerSETCC(SDValue Op, SelectionDAG &DAG)
435 // The operands to this are the left and right operands to compare (ops #0,
436 // and #1) and the condition code to compare them with (op #2) as a
438 SDValue LHS = Op.getOperand(0);
439 SDValue RHS = Op.getOperand(1);
441 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
443 return DAG.getNode(MipsISD::FPCmp, Op.getValueType(), LHS, RHS,
444 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
447 SDValue MipsTargetLowering::
448 LowerSELECT(SDValue Op, SelectionDAG &DAG)
450 SDValue Cond = Op.getOperand(0);
451 SDValue True = Op.getOperand(1);
452 SDValue False = Op.getOperand(2);
454 // if the incomming condition comes from a integer compare, the select
455 // operation must be SelectCC or a conditional move if the subtarget
457 if (Cond.getOpcode() != MipsISD::FPCmp) {
458 if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
460 return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
464 // if the incomming condition comes from fpcmp, the select
465 // operation must use FPSelectCC.
466 SDValue CCNode = Cond.getOperand(2);
467 return DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
468 Cond, True, False, CCNode);
471 SDValue MipsTargetLowering::
472 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
474 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
475 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
477 if (!Subtarget->hasABICall()) {
478 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
479 SDValue Ops[] = { GA };
480 // %gp_rel relocation
481 if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) {
482 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1);
483 SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
484 return DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
486 // %hi/%lo relocation
487 SDValue HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
488 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
489 return DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
491 } else { // Abicall relocations, TODO: make this cleaner.
492 SDValue ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
493 // On functions and global targets not internal linked only
494 // a load from got/GP is necessary for PIC to work.
495 if (!GV->hasInternalLinkage() || isa<Function>(GV))
497 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
498 return DAG.getNode(ISD::ADD, MVT::i32, ResNode, Lo);
501 assert(0 && "Dont know how to handle GlobalAddress");
505 SDValue MipsTargetLowering::
506 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
508 assert(0 && "TLS not implemented for MIPS.");
509 return SDValue(); // Not reached
512 SDValue MipsTargetLowering::
513 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
518 MVT PtrVT = Op.getValueType();
519 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
520 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
522 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
523 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
524 SDValue Ops[] = { JTI };
525 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
526 } else // Emit Load from Global Pointer
527 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
529 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
530 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
535 SDValue MipsTargetLowering::
536 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
539 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
540 Constant *C = N->getConstVal();
541 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
544 // FIXME: we should reference the constant pool using small data sections,
545 // but the asm printer currently doens't support this feature without
546 // hacking it. This feature should come soon so we can uncomment the
548 //if (!Subtarget->hasABICall() &&
549 // IsInSmallSection(getTargetData()->getABITypeSize(C->getType()))) {
550 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
551 // SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
552 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
553 //} else { // %hi/%lo relocation
554 SDValue HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP);
555 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP);
556 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
562 //===----------------------------------------------------------------------===//
563 // Calling Convention Implementation
565 // The lower operations present on calling convention works on this order:
566 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
567 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
568 // LowerRET (virt regs --> phys regs)
569 // LowerCALL (phys regs --> virt regs)
571 //===----------------------------------------------------------------------===//
573 #include "MipsGenCallingConv.inc"
575 //===----------------------------------------------------------------------===//
576 // CALL Calling Convention Implementation
577 //===----------------------------------------------------------------------===//
579 /// LowerCCCCallTo - functions arguments are copied from virtual
580 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
581 /// CALLSEQ_END are emitted.
582 /// TODO: isVarArg, isTailCall.
583 SDValue MipsTargetLowering::
584 LowerCALL(SDValue Op, SelectionDAG &DAG)
586 MachineFunction &MF = DAG.getMachineFunction();
588 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
589 SDValue Chain = TheCall->getChain();
590 SDValue Callee = TheCall->getCallee();
591 bool isVarArg = TheCall->isVarArg();
592 unsigned CC = TheCall->getCallingConv();
594 MachineFrameInfo *MFI = MF.getFrameInfo();
596 // Analyze operands of the call, assigning locations to each operand.
597 SmallVector<CCValAssign, 16> ArgLocs;
598 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
600 // To meet O32 ABI, Mips must always allocate 16 bytes on
601 // the stack (even if less than 4 are used as arguments)
602 if (Subtarget->isABI_O32()) {
603 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
604 MFI->CreateFixedObject(VTsize, (VTsize*3));
607 CCInfo.AnalyzeCallOperands(TheCall, CC_Mips);
609 // Get a count of how many bytes are to be pushed on the stack.
610 unsigned NumBytes = CCInfo.getNextStackOffset();
611 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
613 // With EABI is it possible to have 16 args on registers.
614 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
615 SmallVector<SDValue, 8> MemOpChains;
617 // First/LastArgStackLoc contains the first/last
618 // "at stack" argument location.
619 int LastArgStackLoc = 0;
620 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
622 // Walk the register/memloc assignments, inserting copies/loads.
623 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
624 CCValAssign &VA = ArgLocs[i];
626 // Arguments start after the 5 first operands of ISD::CALL
627 SDValue Arg = TheCall->getArg(i);
629 // Promote the value if needed.
630 switch (VA.getLocInfo()) {
631 default: assert(0 && "Unknown loc info!");
632 case CCValAssign::Full: break;
633 case CCValAssign::SExt:
634 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
636 case CCValAssign::ZExt:
637 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
639 case CCValAssign::AExt:
640 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
644 // Arguments that can be passed on register must be kept at
647 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
651 // Register cant get to this point...
652 assert(VA.isMemLoc());
654 // Create the frame index object for this incoming parameter
655 // This guarantees that when allocating Local Area the firsts
656 // 16 bytes which are alwayes reserved won't be overwritten
657 // if O32 ABI is used. For EABI the first address is zero.
658 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
659 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
662 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
664 // emit ISD::STORE whichs stores the
665 // parameter value to a stack Location
666 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
669 // Transform all store nodes into one single node because all store
670 // nodes are independent of each other.
671 if (!MemOpChains.empty())
672 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
673 &MemOpChains[0], MemOpChains.size());
675 // Build a sequence of copy-to-reg nodes chained together with token
676 // chain and flag operands which copy the outgoing args into registers.
677 // The InFlag in necessary since all emited instructions must be
680 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
681 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
682 RegsToPass[i].second, InFlag);
683 InFlag = Chain.getValue(1);
686 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
687 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
688 // node so that legalize doesn't hack it.
689 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
690 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
691 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
692 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
695 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
696 // = Chain, Callee, Reg#1, Reg#2, ...
698 // Returns a chain & a flag for retval copy to use.
699 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
700 SmallVector<SDValue, 8> Ops;
701 Ops.push_back(Chain);
702 Ops.push_back(Callee);
704 // Add argument registers to the end of the list so that they are
705 // known live into the call.
706 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
707 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
708 RegsToPass[i].second.getValueType()));
710 if (InFlag.getNode())
711 Ops.push_back(InFlag);
713 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
714 InFlag = Chain.getValue(1);
716 // Create the CALLSEQ_END node.
717 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
718 DAG.getIntPtrConstant(0, true), InFlag);
719 InFlag = Chain.getValue(1);
721 // Create a stack location to hold GP when PIC is used. This stack
722 // location is used on function prologue to save GP and also after all
723 // emited CALL's to restore GP.
724 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
725 // Function can have an arbitrary number of calls, so
726 // hold the LastArgStackLoc with the biggest offset.
728 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
729 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
730 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
731 // Create the frame index only once. SPOffset here can be anything
732 // (this will be fixed on processFunctionBeforeFrameFinalized)
733 if (MipsFI->getGPStackOffset() == -1) {
734 FI = MFI->CreateFixedObject(4, 0);
737 MipsFI->setGPStackOffset(LastArgStackLoc);
741 FI = MipsFI->getGPFI();
742 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
743 SDValue GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
744 Chain = GPLoad.getValue(1);
745 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
746 GPLoad, SDValue(0,0));
747 InFlag = Chain.getValue(1);
750 // Handle result values, copying them out of physregs into vregs that we
752 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG), Op.getResNo());
755 /// LowerCallResult - Lower the result values of an ISD::CALL into the
756 /// appropriate copies out of appropriate physical registers. This assumes that
757 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
758 /// being lowered. Returns a SDNode with the same number of values as the
760 SDNode *MipsTargetLowering::
761 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
762 unsigned CallingConv, SelectionDAG &DAG) {
764 bool isVarArg = TheCall->isVarArg();
766 // Assign locations to each value returned by this call.
767 SmallVector<CCValAssign, 16> RVLocs;
768 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
770 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
771 SmallVector<SDValue, 8> ResultVals;
773 // Copy all of the result registers out of their specified physreg.
774 for (unsigned i = 0; i != RVLocs.size(); ++i) {
775 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
776 RVLocs[i].getValVT(), InFlag).getValue(1);
777 InFlag = Chain.getValue(2);
778 ResultVals.push_back(Chain.getValue(0));
781 ResultVals.push_back(Chain);
783 // Merge everything together with a MERGE_VALUES node.
784 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
785 ResultVals.size()).getNode();
788 //===----------------------------------------------------------------------===//
789 // FORMAL_ARGUMENTS Calling Convention Implementation
790 //===----------------------------------------------------------------------===//
792 /// LowerFORMAL_ARGUMENTS - transform physical registers into
793 /// virtual registers and generate load operations for
794 /// arguments places on the stack.
796 SDValue MipsTargetLowering::
797 LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
799 SDValue Root = Op.getOperand(0);
800 MachineFunction &MF = DAG.getMachineFunction();
801 MachineFrameInfo *MFI = MF.getFrameInfo();
802 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
804 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
805 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
807 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
809 // GP must be live into PIC and non-PIC call target.
810 AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
812 // Assign locations to all of the incoming arguments.
813 SmallVector<CCValAssign, 16> ArgLocs;
814 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
816 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_Mips);
817 SmallVector<SDValue, 16> ArgValues;
820 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
822 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
824 CCValAssign &VA = ArgLocs[i];
826 // Arguments stored on registers
828 MVT RegVT = VA.getLocVT();
829 TargetRegisterClass *RC = 0;
831 if (RegVT == MVT::i32)
832 RC = Mips::CPURegsRegisterClass;
833 else if (RegVT == MVT::f32) {
834 if (Subtarget->isSingleFloat())
835 RC = Mips::FGR32RegisterClass;
837 RC = Mips::AFGR32RegisterClass;
838 } else if (RegVT == MVT::f64) {
839 if (!Subtarget->isSingleFloat())
840 RC = Mips::AFGR64RegisterClass;
842 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
844 // Transform the arguments stored on
845 // physical registers into virtual ones
846 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
847 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
849 // If this is an 8 or 16-bit value, it is really passed promoted
850 // to 32 bits. Insert an assert[sz]ext to capture this, then
851 // truncate to the right size.
852 if (VA.getLocInfo() == CCValAssign::SExt)
853 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
854 DAG.getValueType(VA.getValVT()));
855 else if (VA.getLocInfo() == CCValAssign::ZExt)
856 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
857 DAG.getValueType(VA.getValVT()));
859 if (VA.getLocInfo() != CCValAssign::Full)
860 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
862 ArgValues.push_back(ArgValue);
864 // To meet ABI, when VARARGS are passed on registers, the registers
865 // must have their values written to the caller stack frame.
866 if ((isVarArg) && (Subtarget->isABI_O32())) {
867 if (StackPtr.getNode() == 0)
868 StackPtr = DAG.getRegister(StackReg, getPointerTy());
870 // The stack pointer offset is relative to the caller stack frame.
871 // Since the real stack size is unknown here, a negative SPOffset
872 // is used so there's a way to adjust these offsets when the stack
873 // size get known (on EliminateFrameIndex). A dummy SPOffset is
874 // used instead of a direct negative address (which is recorded to
875 // be used on emitPrologue) to avoid mis-calc of the first stack
876 // offset on PEI::calculateFrameObjectOffsets.
877 // Arguments are always 32-bit.
878 int FI = MFI->CreateFixedObject(4, 0);
879 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
880 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
882 // emit ISD::STORE whichs stores the
883 // parameter value to a stack Location
884 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
887 } else { // VA.isRegLoc()
890 assert(VA.isMemLoc());
892 // The stack pointer offset is relative to the caller stack frame.
893 // Since the real stack size is unknown here, a negative SPOffset
894 // is used so there's a way to adjust these offsets when the stack
895 // size get known (on EliminateFrameIndex). A dummy SPOffset is
896 // used instead of a direct negative address (which is recorded to
897 // be used on emitPrologue) to avoid mis-calc of the first stack
898 // offset on PEI::calculateFrameObjectOffsets.
899 // Arguments are always 32-bit.
900 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
901 int FI = MFI->CreateFixedObject(ArgSize, 0);
902 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
903 (FirstStackArgLoc + VA.getLocMemOffset())));
905 // Create load nodes to retrieve arguments from the stack
906 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
907 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
911 // The mips ABIs for returning structs by value requires that we copy
912 // the sret argument into $v0 for the return. Save the argument into
913 // a virtual register so that we can access it from the return points.
914 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
915 unsigned Reg = MipsFI->getSRetReturnReg();
917 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
918 MipsFI->setSRetReturnReg(Reg);
920 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
921 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
924 ArgValues.push_back(Root);
926 // Return the new list of results.
927 return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
928 ArgValues.size()).getValue(Op.getResNo());
931 //===----------------------------------------------------------------------===//
932 // Return Value Calling Convention Implementation
933 //===----------------------------------------------------------------------===//
935 SDValue MipsTargetLowering::
936 LowerRET(SDValue Op, SelectionDAG &DAG)
938 // CCValAssign - represent the assignment of
939 // the return value to a location
940 SmallVector<CCValAssign, 16> RVLocs;
941 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
942 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
944 // CCState - Info about the registers and stack slot.
945 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
947 // Analize return values of ISD::RET
948 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Mips);
950 // If this is the first return lowered for this function, add
951 // the regs to the liveout set for the function.
952 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
953 for (unsigned i = 0; i != RVLocs.size(); ++i)
954 if (RVLocs[i].isRegLoc())
955 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
958 // The chain is always operand #0
959 SDValue Chain = Op.getOperand(0);
962 // Copy the result values into the output registers.
963 for (unsigned i = 0; i != RVLocs.size(); ++i) {
964 CCValAssign &VA = RVLocs[i];
965 assert(VA.isRegLoc() && "Can only return in registers!");
967 // ISD::RET => ret chain, (regnum1,val1), ...
968 // So i*2+1 index only the regnums
969 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
971 // guarantee that all emitted copies are
972 // stuck together, avoiding something bad
973 Flag = Chain.getValue(1);
976 // The mips ABIs for returning structs by value requires that we copy
977 // the sret argument into $v0 for the return. We saved the argument into
978 // a virtual register in the entry block, so now we copy the value out
980 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
981 MachineFunction &MF = DAG.getMachineFunction();
982 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
983 unsigned Reg = MipsFI->getSRetReturnReg();
986 assert(0 && "sret virtual register not created in the entry block");
987 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
989 Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag);
990 Flag = Chain.getValue(1);
993 // Return on Mips is always a "jr $ra"
995 return DAG.getNode(MipsISD::Ret, MVT::Other,
996 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
998 return DAG.getNode(MipsISD::Ret, MVT::Other,
999 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1002 //===----------------------------------------------------------------------===//
1003 // Mips Inline Assembly Support
1004 //===----------------------------------------------------------------------===//
1006 /// getConstraintType - Given a constraint letter, return the type of
1007 /// constraint it is for this target.
1008 MipsTargetLowering::ConstraintType MipsTargetLowering::
1009 getConstraintType(const std::string &Constraint) const
1011 // Mips specific constrainy
1012 // GCC config/mips/constraints.md
1014 // 'd' : An address register. Equivalent to r
1015 // unless generating MIPS16 code.
1016 // 'y' : Equivalent to r; retained for
1017 // backwards compatibility.
1018 // 'f' : Floating Point registers.
1019 if (Constraint.size() == 1) {
1020 switch (Constraint[0]) {
1025 return C_RegisterClass;
1029 return TargetLowering::getConstraintType(Constraint);
1032 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1033 /// return a list of registers that can be used to satisfy the constraint.
1034 /// This should only be used for C_RegisterClass constraints.
1035 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1036 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
1038 if (Constraint.size() == 1) {
1039 switch (Constraint[0]) {
1041 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1043 if (VT == MVT::f32) {
1044 if (Subtarget->isSingleFloat())
1045 return std::make_pair(0U, Mips::FGR32RegisterClass);
1047 return std::make_pair(0U, Mips::AFGR32RegisterClass);
1050 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1051 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1054 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1057 /// Given a register class constraint, like 'r', if this corresponds directly
1058 /// to an LLVM register class, return a register of 0 and the register class
1060 std::vector<unsigned> MipsTargetLowering::
1061 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1064 if (Constraint.size() != 1)
1065 return std::vector<unsigned>();
1067 switch (Constraint[0]) {
1070 // GCC Mips Constraint Letters
1073 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1074 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1075 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1079 if (VT == MVT::f32) {
1080 if (Subtarget->isSingleFloat())
1081 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1082 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1083 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1084 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1085 Mips::F30, Mips::F31, 0);
1087 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1088 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1089 Mips::F28, Mips::F30, 0);
1093 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1094 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1095 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1096 Mips::D14, Mips::D15, 0);
1098 return std::vector<unsigned>();