1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
37 const char *MipsTargetLowering::
38 getTargetNodeName(unsigned Opcode) const
42 case MipsISD::JmpLink : return "MipsISD::JmpLink";
43 case MipsISD::Hi : return "MipsISD::Hi";
44 case MipsISD::Lo : return "MipsISD::Lo";
45 case MipsISD::GPRel : return "MipsISD::GPRel";
46 case MipsISD::Ret : return "MipsISD::Ret";
47 case MipsISD::CMov : return "MipsISD::CMov";
48 case MipsISD::SelectCC : return "MipsISD::SelectCC";
49 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
50 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
51 case MipsISD::FPCmp : return "MipsISD::FPCmp";
52 case MipsISD::FPRound : return "MipsISD::FPRound";
53 default : return NULL;
58 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
60 Subtarget = &TM.getSubtarget<MipsSubtarget>();
62 // Mips does not have i1 type, so use i32 for
63 // setcc operations results (slt, sgt, ...).
64 setBooleanContents(ZeroOrOneBooleanContent);
66 // JumpTable targets must use GOT when using PIC_
67 setUsesGlobalOffsetTable(true);
69 // Set up the register classes
70 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
71 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
73 // When dealing with single precision only, use libcalls
74 if (!Subtarget->isSingleFloat())
75 if (!Subtarget->isFP64bit())
76 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
79 addLegalFPImmediate(APFloat(+0.0f));
81 // Load extented operations for i1 types must be promoted
82 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
83 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
86 // MIPS doesn't have extending float->double load/store
87 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
88 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
90 // Used by legalize types to correctly generate the setcc result.
91 // Without this, every float setcc comes with a AND/OR with the result,
92 // we don't want this, since the fpcmp result goes to a flag register,
93 // which is used implicitly by brcond and select operations.
94 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
96 // Mips Custom Operations
97 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
98 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
99 setOperationAction(ISD::RET, MVT::Other, Custom);
100 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
101 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
102 setOperationAction(ISD::SELECT, MVT::f32, Custom);
103 setOperationAction(ISD::SELECT, MVT::f64, Custom);
104 setOperationAction(ISD::SELECT, MVT::i32, Custom);
105 setOperationAction(ISD::SETCC, MVT::f32, Custom);
106 setOperationAction(ISD::SETCC, MVT::f64, Custom);
107 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
108 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
109 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
111 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
112 // with operands comming from setcc fp comparions. This is necessary since
113 // the result from these setcc are in a flag registers (FCR31).
114 setOperationAction(ISD::AND, MVT::i32, Custom);
115 setOperationAction(ISD::OR, MVT::i32, Custom);
117 // Operations not directly supported by Mips.
118 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
119 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
120 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
121 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
122 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
124 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
125 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
126 setOperationAction(ISD::ROTL, MVT::i32, Expand);
127 setOperationAction(ISD::ROTR, MVT::i32, Expand);
128 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
129 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
130 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
131 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
132 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
133 setOperationAction(ISD::FSIN, MVT::f32, Expand);
134 setOperationAction(ISD::FCOS, MVT::f32, Expand);
135 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
136 setOperationAction(ISD::FPOW, MVT::f32, Expand);
137 setOperationAction(ISD::FLOG, MVT::f32, Expand);
138 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
139 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
140 setOperationAction(ISD::FEXP, MVT::f32, Expand);
142 // We don't have line number support yet.
143 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
144 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
145 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
146 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
148 // Use the default for now
149 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
150 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
151 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
153 if (Subtarget->isSingleFloat())
154 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
156 if (!Subtarget->hasSEInReg()) {
157 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
161 if (!Subtarget->hasBitCount())
162 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
164 if (!Subtarget->hasSwap())
165 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
167 setStackPointerRegisterToSaveRestore(Mips::SP);
168 computeRegisterProperties();
171 MVT MipsTargetLowering::getSetCCResultType(MVT VT) const {
175 /// getFunctionAlignment - Return the Log2 alignment of this function.
176 unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const {
180 SDValue MipsTargetLowering::
181 LowerOperation(SDValue Op, SelectionDAG &DAG)
183 switch (Op.getOpcode())
185 case ISD::AND: return LowerANDOR(Op, DAG);
186 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
187 case ISD::CALL: return LowerCALL(Op, DAG);
188 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
189 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
190 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
191 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
192 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
193 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
194 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
195 case ISD::OR: return LowerANDOR(Op, DAG);
196 case ISD::RET: return LowerRET(Op, DAG);
197 case ISD::SELECT: return LowerSELECT(Op, DAG);
198 case ISD::SETCC: return LowerSETCC(Op, DAG);
203 //===----------------------------------------------------------------------===//
204 // Lower helper functions
205 //===----------------------------------------------------------------------===//
207 // AddLiveIn - This helper function adds the specified physical register to the
208 // MachineFunction as a live in value. It also creates a corresponding
209 // virtual register for it.
211 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
213 assert(RC->contains(PReg) && "Not the correct regclass!");
214 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
215 MF.getRegInfo().addLiveIn(PReg, VReg);
219 // A address must be loaded from a small section if its size is less than the
220 // small section size threshold. Data in this section must be addressed using
222 bool MipsTargetLowering::IsInSmallSection(unsigned Size) {
223 return (Size > 0 && (Size <= Subtarget->getSSectionThreshold()));
226 // Discover if this global address can be placed into small data/bss section.
227 bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV)
229 const TargetData *TD = getTargetData();
230 const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV);
235 const Type *Ty = GV->getType()->getElementType();
236 unsigned Size = TD->getTypeAllocSize(Ty);
238 // if this is a internal constant string, there is a special
239 // section for it, but not in small data/bss.
240 if (GVA->hasInitializer() && GV->hasLocalLinkage()) {
241 Constant *C = GVA->getInitializer();
242 const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
243 if (CVA && CVA->isCString())
247 return IsInSmallSection(Size);
250 // Get fp branch code (not opcode) from condition code.
251 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
252 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
253 return Mips::BRANCH_T;
255 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
256 return Mips::BRANCH_F;
258 return Mips::BRANCH_INVALID;
261 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
264 llvm_unreachable("Unknown branch code");
265 case Mips::BRANCH_T : return Mips::BC1T;
266 case Mips::BRANCH_F : return Mips::BC1F;
267 case Mips::BRANCH_TL : return Mips::BC1TL;
268 case Mips::BRANCH_FL : return Mips::BC1FL;
272 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
274 default: llvm_unreachable("Unknown fp condition code!");
276 case ISD::SETOEQ: return Mips::FCOND_EQ;
277 case ISD::SETUNE: return Mips::FCOND_OGL;
279 case ISD::SETOLT: return Mips::FCOND_OLT;
281 case ISD::SETOGT: return Mips::FCOND_OGT;
283 case ISD::SETOLE: return Mips::FCOND_OLE;
285 case ISD::SETOGE: return Mips::FCOND_OGE;
286 case ISD::SETULT: return Mips::FCOND_ULT;
287 case ISD::SETULE: return Mips::FCOND_ULE;
288 case ISD::SETUGT: return Mips::FCOND_UGT;
289 case ISD::SETUGE: return Mips::FCOND_UGE;
290 case ISD::SETUO: return Mips::FCOND_UN;
291 case ISD::SETO: return Mips::FCOND_OR;
293 case ISD::SETONE: return Mips::FCOND_NEQ;
294 case ISD::SETUEQ: return Mips::FCOND_UEQ;
299 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
300 MachineBasicBlock *BB) const {
301 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
302 bool isFPCmp = false;
303 DebugLoc dl = MI->getDebugLoc();
305 switch (MI->getOpcode()) {
306 default: assert(false && "Unexpected instr type to insert");
307 case Mips::Select_FCC:
308 case Mips::Select_FCC_S32:
309 case Mips::Select_FCC_D32:
310 isFPCmp = true; // FALL THROUGH
311 case Mips::Select_CC:
312 case Mips::Select_CC_S32:
313 case Mips::Select_CC_D32: {
314 // To "insert" a SELECT_CC instruction, we actually have to insert the
315 // diamond control-flow pattern. The incoming instruction knows the
316 // destination vreg to set, the condition code register to branch on, the
317 // true/false values to select between, and a branch opcode to use.
318 const BasicBlock *LLVM_BB = BB->getBasicBlock();
319 MachineFunction::iterator It = BB;
326 // bNE r1, r0, copy1MBB
327 // fallthrough --> copy0MBB
328 MachineBasicBlock *thisMBB = BB;
329 MachineFunction *F = BB->getParent();
330 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
331 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
333 // Emit the right instruction according to the type of the operands compared
335 // Find the condiction code present in the setcc operation.
336 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
337 // Get the branch opcode from the branch code.
338 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
339 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
341 BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
342 .addReg(Mips::ZERO).addMBB(sinkMBB);
344 F->insert(It, copy0MBB);
345 F->insert(It, sinkMBB);
346 // Update machine-CFG edges by first adding all successors of the current
347 // block to the new block which will contain the Phi node for the select.
348 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
349 e = BB->succ_end(); i != e; ++i)
350 sinkMBB->addSuccessor(*i);
351 // Next, remove all successors of the current block, and add the true
352 // and fallthrough blocks as its successors.
353 while(!BB->succ_empty())
354 BB->removeSuccessor(BB->succ_begin());
355 BB->addSuccessor(copy0MBB);
356 BB->addSuccessor(sinkMBB);
360 // # fallthrough to sinkMBB
363 // Update machine-CFG edges
364 BB->addSuccessor(sinkMBB);
367 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
370 BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg())
371 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
372 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
374 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
380 //===----------------------------------------------------------------------===//
381 // Misc Lower Operation implementation
382 //===----------------------------------------------------------------------===//
384 SDValue MipsTargetLowering::
385 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG)
387 if (!Subtarget->isMips1())
390 MachineFunction &MF = DAG.getMachineFunction();
391 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
393 SDValue Chain = DAG.getEntryNode();
394 DebugLoc dl = Op.getDebugLoc();
395 SDValue Src = Op.getOperand(0);
397 // Set the condition register
398 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
399 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
400 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
402 SDValue Cst = DAG.getConstant(3, MVT::i32);
403 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
404 Cst = DAG.getConstant(2, MVT::i32);
405 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
407 SDValue InFlag(0, 0);
408 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
410 // Emit the round instruction and bit convert to integer
411 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
412 Src, CondReg.getValue(1));
413 SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Trunc);
417 SDValue MipsTargetLowering::
418 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
420 SDValue Chain = Op.getOperand(0);
421 SDValue Size = Op.getOperand(1);
422 DebugLoc dl = Op.getDebugLoc();
424 // Get a reference from Mips stack pointer
425 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
427 // Subtract the dynamic size from the actual stack size to
428 // obtain the new stack size.
429 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
431 // The Sub result contains the new stack start address, so it
432 // must be placed in the stack pointer register.
433 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
435 // This node always has two return values: a new stack pointer
437 SDValue Ops[2] = { Sub, Chain };
438 return DAG.getMergeValues(Ops, 2, dl);
441 SDValue MipsTargetLowering::
442 LowerANDOR(SDValue Op, SelectionDAG &DAG)
444 SDValue LHS = Op.getOperand(0);
445 SDValue RHS = Op.getOperand(1);
446 DebugLoc dl = Op.getDebugLoc();
448 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
451 SDValue True = DAG.getConstant(1, MVT::i32);
452 SDValue False = DAG.getConstant(0, MVT::i32);
454 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
455 LHS, True, False, LHS.getOperand(2));
456 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
457 RHS, True, False, RHS.getOperand(2));
459 return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
462 SDValue MipsTargetLowering::
463 LowerBRCOND(SDValue Op, SelectionDAG &DAG)
465 // The first operand is the chain, the second is the condition, the third is
466 // the block to branch to if the condition is true.
467 SDValue Chain = Op.getOperand(0);
468 SDValue Dest = Op.getOperand(2);
469 DebugLoc dl = Op.getDebugLoc();
471 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
474 SDValue CondRes = Op.getOperand(1);
475 SDValue CCNode = CondRes.getOperand(2);
477 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
478 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
480 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
484 SDValue MipsTargetLowering::
485 LowerSETCC(SDValue Op, SelectionDAG &DAG)
487 // The operands to this are the left and right operands to compare (ops #0,
488 // and #1) and the condition code to compare them with (op #2) as a
490 SDValue LHS = Op.getOperand(0);
491 SDValue RHS = Op.getOperand(1);
492 DebugLoc dl = Op.getDebugLoc();
494 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
496 return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
497 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
500 SDValue MipsTargetLowering::
501 LowerSELECT(SDValue Op, SelectionDAG &DAG)
503 SDValue Cond = Op.getOperand(0);
504 SDValue True = Op.getOperand(1);
505 SDValue False = Op.getOperand(2);
506 DebugLoc dl = Op.getDebugLoc();
508 // if the incomming condition comes from a integer compare, the select
509 // operation must be SelectCC or a conditional move if the subtarget
511 if (Cond.getOpcode() != MipsISD::FPCmp) {
512 if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
514 return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(),
518 // if the incomming condition comes from fpcmp, the select
519 // operation must use FPSelectCC.
520 SDValue CCNode = Cond.getOperand(2);
521 return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
522 Cond, True, False, CCNode);
525 SDValue MipsTargetLowering::
526 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
528 // FIXME there isn't actually debug info here
529 DebugLoc dl = Op.getDebugLoc();
530 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
531 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
533 if (!Subtarget->hasABICall()) {
534 SDVTList VTs = DAG.getVTList(MVT::i32);
535 SDValue Ops[] = { GA };
536 // %gp_rel relocation
537 if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) {
538 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, Ops, 1);
539 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
540 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
542 // %hi/%lo relocation
543 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1);
544 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
545 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
547 } else { // Abicall relocations, TODO: make this cleaner.
548 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
549 DAG.getEntryNode(), GA, NULL, 0);
550 // On functions and global targets not internal linked only
551 // a load from got/GP is necessary for PIC to work.
552 if (!GV->hasLocalLinkage() || isa<Function>(GV))
554 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
555 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
558 llvm_unreachable("Dont know how to handle GlobalAddress");
562 SDValue MipsTargetLowering::
563 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
565 llvm_unreachable("TLS not implemented for MIPS.");
566 return SDValue(); // Not reached
569 SDValue MipsTargetLowering::
570 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
574 // FIXME there isn't actually debug info here
575 DebugLoc dl = Op.getDebugLoc();
577 MVT PtrVT = Op.getValueType();
578 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
579 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
581 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
582 SDVTList VTs = DAG.getVTList(MVT::i32);
583 SDValue Ops[] = { JTI };
584 HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1);
585 } else // Emit Load from Global Pointer
586 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
588 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
589 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
594 SDValue MipsTargetLowering::
595 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
598 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
599 Constant *C = N->getConstVal();
600 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
601 // FIXME there isn't actually debug info here
602 DebugLoc dl = Op.getDebugLoc();
605 // FIXME: we should reference the constant pool using small data sections,
606 // but the asm printer currently doens't support this feature without
607 // hacking it. This feature should come soon so we can uncomment the
609 //if (!Subtarget->hasABICall() &&
610 // IsInSmallSection(getTargetData()->getTypeAllocSize(C->getType()))) {
611 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
612 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
613 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
614 //} else { // %hi/%lo relocation
615 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
616 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
617 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
623 //===----------------------------------------------------------------------===//
624 // Calling Convention Implementation
626 // The lower operations present on calling convention works on this order:
627 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
628 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
629 // LowerRET (virt regs --> phys regs)
630 // LowerCALL (phys regs --> virt regs)
632 //===----------------------------------------------------------------------===//
634 #include "MipsGenCallingConv.inc"
636 //===----------------------------------------------------------------------===//
637 // TODO: Implement a generic logic using tblgen that can support this.
638 // Mips O32 ABI rules:
640 // i32 - Passed in A0, A1, A2, A3 and stack
641 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
642 // an argument. Otherwise, passed in A1, A2, A3 and stack.
643 // f64 - Only passed in two aliased f32 registers if no int reg has been used
644 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
645 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
647 //===----------------------------------------------------------------------===//
649 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
650 MVT LocVT, CCValAssign::LocInfo LocInfo,
651 ISD::ArgFlagsTy ArgFlags, CCState &State) {
653 static const unsigned IntRegsSize=4, FloatRegsSize=2;
655 static const unsigned IntRegs[] = {
656 Mips::A0, Mips::A1, Mips::A2, Mips::A3
658 static const unsigned F32Regs[] = {
661 static const unsigned F64Regs[] = {
666 unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
667 bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0)));
669 // Promote i8 and i16
670 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
672 if (ArgFlags.isSExt())
673 LocInfo = CCValAssign::SExt;
674 else if (ArgFlags.isZExt())
675 LocInfo = CCValAssign::ZExt;
677 LocInfo = CCValAssign::AExt;
680 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) {
681 Reg = State.AllocateReg(IntRegs, IntRegsSize);
686 if (ValVT.isFloatingPoint() && !IntRegUsed) {
687 if (ValVT == MVT::f32)
688 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
690 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
693 if (ValVT == MVT::f64 && IntRegUsed) {
694 if (UnallocIntReg != IntRegsSize) {
695 // If we hit register A3 as the first not allocated, we must
696 // mark it as allocated (shadow) and use the stack instead.
697 if (IntRegs[UnallocIntReg] != (unsigned (Mips::A3)))
699 for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg)
700 State.AllocateReg(UnallocIntReg);
706 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
707 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
708 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
710 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
712 return false; // CC must always match
715 //===----------------------------------------------------------------------===//
716 // CALL Calling Convention Implementation
717 //===----------------------------------------------------------------------===//
719 /// LowerCALL - functions arguments are copied from virtual regs to
720 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
721 /// TODO: isVarArg, isTailCall.
722 SDValue MipsTargetLowering::
723 LowerCALL(SDValue Op, SelectionDAG &DAG)
725 MachineFunction &MF = DAG.getMachineFunction();
727 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
728 SDValue Chain = TheCall->getChain();
729 SDValue Callee = TheCall->getCallee();
730 bool isVarArg = TheCall->isVarArg();
731 unsigned CC = TheCall->getCallingConv();
732 DebugLoc dl = TheCall->getDebugLoc();
734 MachineFrameInfo *MFI = MF.getFrameInfo();
736 // Analyze operands of the call, assigning locations to each operand.
737 SmallVector<CCValAssign, 16> ArgLocs;
738 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext());
740 // To meet O32 ABI, Mips must always allocate 16 bytes on
741 // the stack (even if less than 4 are used as arguments)
742 if (Subtarget->isABI_O32()) {
743 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
744 MFI->CreateFixedObject(VTsize, (VTsize*3));
745 CCInfo.AnalyzeCallOperands(TheCall, CC_MipsO32);
747 CCInfo.AnalyzeCallOperands(TheCall, CC_Mips);
749 // Get a count of how many bytes are to be pushed on the stack.
750 unsigned NumBytes = CCInfo.getNextStackOffset();
751 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
753 // With EABI is it possible to have 16 args on registers.
754 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
755 SmallVector<SDValue, 8> MemOpChains;
757 // First/LastArgStackLoc contains the first/last
758 // "at stack" argument location.
759 int LastArgStackLoc = 0;
760 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
762 // Walk the register/memloc assignments, inserting copies/loads.
763 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
764 SDValue Arg = TheCall->getArg(i);
765 CCValAssign &VA = ArgLocs[i];
767 // Promote the value if needed.
768 switch (VA.getLocInfo()) {
769 default: llvm_unreachable("Unknown loc info!");
770 case CCValAssign::Full:
771 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
772 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
773 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg);
774 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
775 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
776 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
777 DAG.getConstant(0, getPointerTy()));
778 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
779 DAG.getConstant(1, getPointerTy()));
780 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
781 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
786 case CCValAssign::SExt:
787 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
789 case CCValAssign::ZExt:
790 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
792 case CCValAssign::AExt:
793 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
797 // Arguments that can be passed on register must be kept at
800 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
804 // Register can't get to this point...
805 assert(VA.isMemLoc());
807 // Create the frame index object for this incoming parameter
808 // This guarantees that when allocating Local Area the firsts
809 // 16 bytes which are alwayes reserved won't be overwritten
810 // if O32 ABI is used. For EABI the first address is zero.
811 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
812 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
815 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
817 // emit ISD::STORE whichs stores the
818 // parameter value to a stack Location
819 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
822 // Transform all store nodes into one single node because all store
823 // nodes are independent of each other.
824 if (!MemOpChains.empty())
825 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
826 &MemOpChains[0], MemOpChains.size());
828 // Build a sequence of copy-to-reg nodes chained together with token
829 // chain and flag operands which copy the outgoing args into registers.
830 // The InFlag in necessary since all emited instructions must be
833 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
834 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
835 RegsToPass[i].second, InFlag);
836 InFlag = Chain.getValue(1);
839 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
840 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
841 // node so that legalize doesn't hack it.
842 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
843 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
844 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
845 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
847 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
848 // = Chain, Callee, Reg#1, Reg#2, ...
850 // Returns a chain & a flag for retval copy to use.
851 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
852 SmallVector<SDValue, 8> Ops;
853 Ops.push_back(Chain);
854 Ops.push_back(Callee);
856 // Add argument registers to the end of the list so that they are
857 // known live into the call.
858 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
859 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
860 RegsToPass[i].second.getValueType()));
862 if (InFlag.getNode())
863 Ops.push_back(InFlag);
865 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
866 InFlag = Chain.getValue(1);
868 // Create the CALLSEQ_END node.
869 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
870 DAG.getIntPtrConstant(0, true), InFlag);
871 InFlag = Chain.getValue(1);
873 // Create a stack location to hold GP when PIC is used. This stack
874 // location is used on function prologue to save GP and also after all
875 // emited CALL's to restore GP.
876 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
877 // Function can have an arbitrary number of calls, so
878 // hold the LastArgStackLoc with the biggest offset.
880 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
881 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
882 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
883 // Create the frame index only once. SPOffset here can be anything
884 // (this will be fixed on processFunctionBeforeFrameFinalized)
885 if (MipsFI->getGPStackOffset() == -1) {
886 FI = MFI->CreateFixedObject(4, 0);
889 MipsFI->setGPStackOffset(LastArgStackLoc);
893 FI = MipsFI->getGPFI();
894 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
895 SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0);
896 Chain = GPLoad.getValue(1);
897 Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
898 GPLoad, SDValue(0,0));
899 InFlag = Chain.getValue(1);
902 // Handle result values, copying them out of physregs into vregs that we
904 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG), Op.getResNo());
907 /// LowerCallResult - Lower the result values of an ISD::CALL into the
908 /// appropriate copies out of appropriate physical registers. This assumes that
909 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
910 /// being lowered. Returns a SDNode with the same number of values as the
912 SDNode *MipsTargetLowering::
913 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
914 unsigned CallingConv, SelectionDAG &DAG) {
916 bool isVarArg = TheCall->isVarArg();
917 DebugLoc dl = TheCall->getDebugLoc();
919 // Assign locations to each value returned by this call.
920 SmallVector<CCValAssign, 16> RVLocs;
921 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(),
922 RVLocs, *DAG.getContext());
924 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
925 SmallVector<SDValue, 8> ResultVals;
927 // Copy all of the result registers out of their specified physreg.
928 for (unsigned i = 0; i != RVLocs.size(); ++i) {
929 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
930 RVLocs[i].getValVT(), InFlag).getValue(1);
931 InFlag = Chain.getValue(2);
932 ResultVals.push_back(Chain.getValue(0));
935 ResultVals.push_back(Chain);
937 // Merge everything together with a MERGE_VALUES node.
938 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
939 &ResultVals[0], ResultVals.size()).getNode();
942 //===----------------------------------------------------------------------===//
943 // FORMAL_ARGUMENTS Calling Convention Implementation
944 //===----------------------------------------------------------------------===//
946 /// LowerFORMAL_ARGUMENTS - transform physical registers into
947 /// virtual registers and generate load operations for
948 /// arguments places on the stack.
950 SDValue MipsTargetLowering::
951 LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
953 SDValue Root = Op.getOperand(0);
954 MachineFunction &MF = DAG.getMachineFunction();
955 MachineFrameInfo *MFI = MF.getFrameInfo();
956 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
957 DebugLoc dl = Op.getDebugLoc();
959 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
960 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
962 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
964 // Assign locations to all of the incoming arguments.
965 SmallVector<CCValAssign, 16> ArgLocs;
966 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext());
968 if (Subtarget->isABI_O32())
969 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MipsO32);
971 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_Mips);
973 SmallVector<SDValue, 16> ArgValues;
976 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
978 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
979 CCValAssign &VA = ArgLocs[i];
981 // Arguments stored on registers
983 MVT RegVT = VA.getLocVT();
984 TargetRegisterClass *RC = 0;
986 if (RegVT == MVT::i32)
987 RC = Mips::CPURegsRegisterClass;
988 else if (RegVT == MVT::f32)
989 RC = Mips::FGR32RegisterClass;
990 else if (RegVT == MVT::f64) {
991 if (!Subtarget->isSingleFloat())
992 RC = Mips::AFGR64RegisterClass;
994 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
996 // Transform the arguments stored on
997 // physical registers into virtual ones
998 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
999 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
1001 // If this is an 8 or 16-bit value, it has been passed promoted
1002 // to 32 bits. Insert an assert[sz]ext to capture this, then
1003 // truncate to the right size.
1004 if (VA.getLocInfo() != CCValAssign::Full) {
1005 unsigned Opcode = 0;
1006 if (VA.getLocInfo() == CCValAssign::SExt)
1007 Opcode = ISD::AssertSext;
1008 else if (VA.getLocInfo() == CCValAssign::ZExt)
1009 Opcode = ISD::AssertZext;
1011 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
1012 DAG.getValueType(VA.getValVT()));
1013 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1016 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
1017 if (Subtarget->isABI_O32()) {
1018 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
1019 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
1020 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
1021 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
1022 VA.getLocReg()+1, RC);
1023 SDValue ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg2, RegVT);
1024 SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
1025 SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2);
1026 ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi);
1030 ArgValues.push_back(ArgValue);
1032 // To meet ABI, when VARARGS are passed on registers, the registers
1033 // must have their values written to the caller stack frame.
1034 if ((isVarArg) && (Subtarget->isABI_O32())) {
1035 if (StackPtr.getNode() == 0)
1036 StackPtr = DAG.getRegister(StackReg, getPointerTy());
1038 // The stack pointer offset is relative to the caller stack frame.
1039 // Since the real stack size is unknown here, a negative SPOffset
1040 // is used so there's a way to adjust these offsets when the stack
1041 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1042 // used instead of a direct negative address (which is recorded to
1043 // be used on emitPrologue) to avoid mis-calc of the first stack
1044 // offset on PEI::calculateFrameObjectOffsets.
1045 // Arguments are always 32-bit.
1046 int FI = MFI->CreateFixedObject(4, 0);
1047 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
1048 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
1050 // emit ISD::STORE whichs stores the
1051 // parameter value to a stack Location
1052 ArgValues.push_back(DAG.getStore(Root, dl, ArgValue, PtrOff, NULL, 0));
1055 } else { // VA.isRegLoc()
1058 assert(VA.isMemLoc());
1060 // The stack pointer offset is relative to the caller stack frame.
1061 // Since the real stack size is unknown here, a negative SPOffset
1062 // is used so there's a way to adjust these offsets when the stack
1063 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1064 // used instead of a direct negative address (which is recorded to
1065 // be used on emitPrologue) to avoid mis-calc of the first stack
1066 // offset on PEI::calculateFrameObjectOffsets.
1067 // Arguments are always 32-bit.
1068 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1069 int FI = MFI->CreateFixedObject(ArgSize, 0);
1070 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
1071 (FirstStackArgLoc + VA.getLocMemOffset())));
1073 // Create load nodes to retrieve arguments from the stack
1074 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1075 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0));
1079 // The mips ABIs for returning structs by value requires that we copy
1080 // the sret argument into $v0 for the return. Save the argument into
1081 // a virtual register so that we can access it from the return points.
1082 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1083 unsigned Reg = MipsFI->getSRetReturnReg();
1085 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1086 MipsFI->setSRetReturnReg(Reg);
1088 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]);
1089 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root);
1092 ArgValues.push_back(Root);
1094 // Return the new list of results.
1095 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1096 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1099 //===----------------------------------------------------------------------===//
1100 // Return Value Calling Convention Implementation
1101 //===----------------------------------------------------------------------===//
1103 SDValue MipsTargetLowering::
1104 LowerRET(SDValue Op, SelectionDAG &DAG)
1106 // CCValAssign - represent the assignment of
1107 // the return value to a location
1108 SmallVector<CCValAssign, 16> RVLocs;
1109 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1110 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1111 DebugLoc dl = Op.getDebugLoc();
1113 // CCState - Info about the registers and stack slot.
1114 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs, *DAG.getContext());
1116 // Analize return values of ISD::RET
1117 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Mips);
1119 // If this is the first return lowered for this function, add
1120 // the regs to the liveout set for the function.
1121 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1122 for (unsigned i = 0; i != RVLocs.size(); ++i)
1123 if (RVLocs[i].isRegLoc())
1124 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1127 // The chain is always operand #0
1128 SDValue Chain = Op.getOperand(0);
1131 // Copy the result values into the output registers.
1132 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1133 CCValAssign &VA = RVLocs[i];
1134 assert(VA.isRegLoc() && "Can only return in registers!");
1136 // ISD::RET => ret chain, (regnum1,val1), ...
1137 // So i*2+1 index only the regnums
1138 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1139 Op.getOperand(i*2+1), Flag);
1141 // guarantee that all emitted copies are
1142 // stuck together, avoiding something bad
1143 Flag = Chain.getValue(1);
1146 // The mips ABIs for returning structs by value requires that we copy
1147 // the sret argument into $v0 for the return. We saved the argument into
1148 // a virtual register in the entry block, so now we copy the value out
1150 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1151 MachineFunction &MF = DAG.getMachineFunction();
1152 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1153 unsigned Reg = MipsFI->getSRetReturnReg();
1156 llvm_unreachable("sret virtual register not created in the entry block");
1157 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1159 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1160 Flag = Chain.getValue(1);
1163 // Return on Mips is always a "jr $ra"
1165 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1166 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1168 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1169 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1172 //===----------------------------------------------------------------------===//
1173 // Mips Inline Assembly Support
1174 //===----------------------------------------------------------------------===//
1176 /// getConstraintType - Given a constraint letter, return the type of
1177 /// constraint it is for this target.
1178 MipsTargetLowering::ConstraintType MipsTargetLowering::
1179 getConstraintType(const std::string &Constraint) const
1181 // Mips specific constrainy
1182 // GCC config/mips/constraints.md
1184 // 'd' : An address register. Equivalent to r
1185 // unless generating MIPS16 code.
1186 // 'y' : Equivalent to r; retained for
1187 // backwards compatibility.
1188 // 'f' : Floating Point registers.
1189 if (Constraint.size() == 1) {
1190 switch (Constraint[0]) {
1195 return C_RegisterClass;
1199 return TargetLowering::getConstraintType(Constraint);
1202 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1203 /// return a list of registers that can be used to satisfy the constraint.
1204 /// This should only be used for C_RegisterClass constraints.
1205 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1206 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
1208 if (Constraint.size() == 1) {
1209 switch (Constraint[0]) {
1211 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1214 return std::make_pair(0U, Mips::FGR32RegisterClass);
1216 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1217 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1220 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1223 /// Given a register class constraint, like 'r', if this corresponds directly
1224 /// to an LLVM register class, return a register of 0 and the register class
1226 std::vector<unsigned> MipsTargetLowering::
1227 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1230 if (Constraint.size() != 1)
1231 return std::vector<unsigned>();
1233 switch (Constraint[0]) {
1236 // GCC Mips Constraint Letters
1239 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1240 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1241 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1245 if (VT == MVT::f32) {
1246 if (Subtarget->isSingleFloat())
1247 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1248 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1249 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1250 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1251 Mips::F30, Mips::F31, 0);
1253 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1254 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1255 Mips::F28, Mips::F30, 0);
1259 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1260 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1261 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1262 Mips::D14, Mips::D15, 0);
1264 return std::vector<unsigned>();
1268 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1269 // The Mips target isn't yet aware of offsets.