1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "MipsTargetObjectFile.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
37 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
39 case MipsISD::JmpLink : return "MipsISD::JmpLink";
40 case MipsISD::Hi : return "MipsISD::Hi";
41 case MipsISD::Lo : return "MipsISD::Lo";
42 case MipsISD::GPRel : return "MipsISD::GPRel";
43 case MipsISD::Ret : return "MipsISD::Ret";
44 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
45 case MipsISD::FPCmp : return "MipsISD::FPCmp";
46 case MipsISD::CMovFP_T : return "MipsISD::CMovFP_T";
47 case MipsISD::CMovFP_F : return "MipsISD::CMovFP_F";
48 case MipsISD::FPRound : return "MipsISD::FPRound";
49 case MipsISD::MAdd : return "MipsISD::MAdd";
50 case MipsISD::MAddu : return "MipsISD::MAddu";
51 case MipsISD::MSub : return "MipsISD::MSub";
52 case MipsISD::MSubu : return "MipsISD::MSubu";
53 case MipsISD::DivRem : return "MipsISD::DivRem";
54 case MipsISD::DivRemU : return "MipsISD::DivRemU";
55 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
56 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
57 default : return NULL;
62 MipsTargetLowering(MipsTargetMachine &TM)
63 : TargetLowering(TM, new MipsTargetObjectFile()) {
64 Subtarget = &TM.getSubtarget<MipsSubtarget>();
66 // Mips does not have i1 type, so use i32 for
67 // setcc operations results (slt, sgt, ...).
68 setBooleanContents(ZeroOrOneBooleanContent);
70 // Set up the register classes
71 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
72 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
74 // When dealing with single precision only, use libcalls
75 if (!Subtarget->isSingleFloat())
76 if (!Subtarget->isFP64bit())
77 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
79 // Load extented operations for i1 types must be promoted
80 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
81 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
82 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 // MIPS doesn't have extending float->double load/store
85 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // Used by legalize types to correctly generate the setcc result.
89 // Without this, every float setcc comes with a AND/OR with the result,
90 // we don't want this, since the fpcmp result goes to a flag register,
91 // which is used implicitly by brcond and select operations.
92 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
94 // Mips Custom Operations
95 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
96 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
97 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
98 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
99 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
100 setOperationAction(ISD::SELECT, MVT::f32, Custom);
101 setOperationAction(ISD::SELECT, MVT::f64, Custom);
102 setOperationAction(ISD::SELECT, MVT::i32, Custom);
103 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
104 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
105 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
106 setOperationAction(ISD::VASTART, MVT::Other, Custom);
108 setOperationAction(ISD::SDIV, MVT::i32, Expand);
109 setOperationAction(ISD::SREM, MVT::i32, Expand);
110 setOperationAction(ISD::UDIV, MVT::i32, Expand);
111 setOperationAction(ISD::UREM, MVT::i32, Expand);
113 // Operations not directly supported by Mips.
114 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
115 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
116 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
117 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
118 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
120 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
121 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
122 setOperationAction(ISD::ROTL, MVT::i32, Expand);
124 if (!Subtarget->isMips32r2())
125 setOperationAction(ISD::ROTR, MVT::i32, Expand);
127 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
128 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
129 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
130 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
131 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
132 setOperationAction(ISD::FSIN, MVT::f32, Expand);
133 setOperationAction(ISD::FSIN, MVT::f64, Expand);
134 setOperationAction(ISD::FCOS, MVT::f32, Expand);
135 setOperationAction(ISD::FCOS, MVT::f64, Expand);
136 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
137 setOperationAction(ISD::FPOW, MVT::f32, Expand);
138 setOperationAction(ISD::FLOG, MVT::f32, Expand);
139 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
140 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
141 setOperationAction(ISD::FEXP, MVT::f32, Expand);
143 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
145 setOperationAction(ISD::VAARG, MVT::Other, Expand);
146 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
147 setOperationAction(ISD::VAEND, MVT::Other, Expand);
149 // Use the default for now
150 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
151 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
152 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
154 if (Subtarget->isSingleFloat())
155 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
157 if (!Subtarget->hasSEInReg()) {
158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
159 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
162 if (!Subtarget->hasBitCount())
163 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
165 if (!Subtarget->hasSwap())
166 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
168 setTargetDAGCombine(ISD::ADDE);
169 setTargetDAGCombine(ISD::SUBE);
170 setTargetDAGCombine(ISD::SDIVREM);
171 setTargetDAGCombine(ISD::UDIVREM);
172 setTargetDAGCombine(ISD::SETCC);
174 setStackPointerRegisterToSaveRestore(Mips::SP);
175 computeRegisterProperties();
178 MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
182 /// getFunctionAlignment - Return the Log2 alignment of this function.
183 unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const {
188 // Transforms a subgraph in CurDAG if the following pattern is found:
189 // (addc multLo, Lo0), (adde multHi, Hi0),
191 // multHi/Lo: product of multiplication
192 // Lo0: initial value of Lo register
193 // Hi0: initial value of Hi register
194 // Return true if pattern matching was successful.
195 static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
196 // ADDENode's second operand must be a flag output of an ADDC node in order
197 // for the matching to be successful.
198 SDNode* ADDCNode = ADDENode->getOperand(2).getNode();
200 if (ADDCNode->getOpcode() != ISD::ADDC)
203 SDValue MultHi = ADDENode->getOperand(0);
204 SDValue MultLo = ADDCNode->getOperand(0);
205 SDNode* MultNode = MultHi.getNode();
206 unsigned MultOpc = MultHi.getOpcode();
208 // MultHi and MultLo must be generated by the same node,
209 if (MultLo.getNode() != MultNode)
212 // and it must be a multiplication.
213 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
216 // MultLo amd MultHi must be the first and second output of MultNode
218 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
221 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
222 // of the values of MultNode, in which case MultNode will be removed in later
224 // If there exist users other than ADDENode or ADDCNode, this function returns
225 // here, which will result in MultNode being mapped to a single MULT
226 // instruction node rather than a pair of MULT and MADD instructions being
228 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
231 SDValue Chain = CurDAG->getEntryNode();
232 DebugLoc dl = ADDENode->getDebugLoc();
234 // create MipsMAdd(u) node
235 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
237 SDValue MAdd = CurDAG->getNode(MultOpc, dl,
239 MultNode->getOperand(0),// Factor 0
240 MultNode->getOperand(1),// Factor 1
241 ADDCNode->getOperand(1),// Lo0
242 ADDENode->getOperand(1));// Hi0
244 // create CopyFromReg nodes
245 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
247 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
249 CopyFromLo.getValue(2));
251 // replace uses of adde and addc here
252 if (!SDValue(ADDCNode, 0).use_empty())
253 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
255 if (!SDValue(ADDENode, 0).use_empty())
256 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
262 // Transforms a subgraph in CurDAG if the following pattern is found:
263 // (addc Lo0, multLo), (sube Hi0, multHi),
265 // multHi/Lo: product of multiplication
266 // Lo0: initial value of Lo register
267 // Hi0: initial value of Hi register
268 // Return true if pattern matching was successful.
269 static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
270 // SUBENode's second operand must be a flag output of an SUBC node in order
271 // for the matching to be successful.
272 SDNode* SUBCNode = SUBENode->getOperand(2).getNode();
274 if (SUBCNode->getOpcode() != ISD::SUBC)
277 SDValue MultHi = SUBENode->getOperand(1);
278 SDValue MultLo = SUBCNode->getOperand(1);
279 SDNode* MultNode = MultHi.getNode();
280 unsigned MultOpc = MultHi.getOpcode();
282 // MultHi and MultLo must be generated by the same node,
283 if (MultLo.getNode() != MultNode)
286 // and it must be a multiplication.
287 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
290 // MultLo amd MultHi must be the first and second output of MultNode
292 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
295 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
296 // of the values of MultNode, in which case MultNode will be removed in later
298 // If there exist users other than SUBENode or SUBCNode, this function returns
299 // here, which will result in MultNode being mapped to a single MULT
300 // instruction node rather than a pair of MULT and MSUB instructions being
302 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
305 SDValue Chain = CurDAG->getEntryNode();
306 DebugLoc dl = SUBENode->getDebugLoc();
308 // create MipsSub(u) node
309 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
311 SDValue MSub = CurDAG->getNode(MultOpc, dl,
313 MultNode->getOperand(0),// Factor 0
314 MultNode->getOperand(1),// Factor 1
315 SUBCNode->getOperand(0),// Lo0
316 SUBENode->getOperand(0));// Hi0
318 // create CopyFromReg nodes
319 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
321 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
323 CopyFromLo.getValue(2));
325 // replace uses of sube and subc here
326 if (!SDValue(SUBCNode, 0).use_empty())
327 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
329 if (!SDValue(SUBENode, 0).use_empty())
330 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
335 static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
336 TargetLowering::DAGCombinerInfo &DCI,
337 const MipsSubtarget* Subtarget) {
338 if (DCI.isBeforeLegalize())
341 if (Subtarget->isMips32() && SelectMadd(N, &DAG))
342 return SDValue(N, 0);
347 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
348 TargetLowering::DAGCombinerInfo &DCI,
349 const MipsSubtarget* Subtarget) {
350 if (DCI.isBeforeLegalize())
353 if (Subtarget->isMips32() && SelectMsub(N, &DAG))
354 return SDValue(N, 0);
359 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG,
360 TargetLowering::DAGCombinerInfo &DCI,
361 const MipsSubtarget* Subtarget) {
362 if (DCI.isBeforeLegalizeOps())
365 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
367 DebugLoc dl = N->getDebugLoc();
369 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
370 N->getOperand(0), N->getOperand(1));
371 SDValue InChain = DAG.getEntryNode();
372 SDValue InGlue = DivRem;
375 if (N->hasAnyUseOfValue(0)) {
376 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, Mips::LO, MVT::i32,
378 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
379 InChain = CopyFromLo.getValue(1);
380 InGlue = CopyFromLo.getValue(2);
384 if (N->hasAnyUseOfValue(1)) {
385 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
386 Mips::HI, MVT::i32, InGlue);
387 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
393 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
395 default: llvm_unreachable("Unknown fp condition code!");
397 case ISD::SETOEQ: return Mips::FCOND_OEQ;
398 case ISD::SETUNE: return Mips::FCOND_UNE;
400 case ISD::SETOLT: return Mips::FCOND_OLT;
402 case ISD::SETOGT: return Mips::FCOND_OGT;
404 case ISD::SETOLE: return Mips::FCOND_OLE;
406 case ISD::SETOGE: return Mips::FCOND_OGE;
407 case ISD::SETULT: return Mips::FCOND_ULT;
408 case ISD::SETULE: return Mips::FCOND_ULE;
409 case ISD::SETUGT: return Mips::FCOND_UGT;
410 case ISD::SETUGE: return Mips::FCOND_UGE;
411 case ISD::SETUO: return Mips::FCOND_UN;
412 case ISD::SETO: return Mips::FCOND_OR;
414 case ISD::SETONE: return Mips::FCOND_ONE;
415 case ISD::SETUEQ: return Mips::FCOND_UEQ;
420 // Returns true if condition code has to be inverted.
421 static bool InvertFPCondCode(Mips::CondCode CC) {
422 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
425 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
428 assert(false && "Illegal Condition Code");
432 // Creates and returns an FPCmp node from a setcc node.
433 // Returns Op if setcc is not a floating point comparison.
434 static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) {
435 // must be a SETCC node
436 if (Op.getOpcode() != ISD::SETCC)
439 SDValue LHS = Op.getOperand(0);
441 if (!LHS.getValueType().isFloatingPoint())
444 SDValue RHS = Op.getOperand(1);
445 DebugLoc dl = Op.getDebugLoc();
447 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
448 // node if necessary.
449 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
451 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
452 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
455 // Creates and returns a CMovFPT/F node.
456 static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True,
457 SDValue False, DebugLoc DL) {
458 bool invert = InvertFPCondCode((Mips::CondCode)
459 cast<ConstantSDNode>(Cond.getOperand(2))
462 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
463 True.getValueType(), True, False, Cond);
466 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG,
467 TargetLowering::DAGCombinerInfo &DCI,
468 const MipsSubtarget* Subtarget) {
469 if (DCI.isBeforeLegalizeOps())
472 SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0));
474 if (Cond.getOpcode() != MipsISD::FPCmp)
477 SDValue True = DAG.getConstant(1, MVT::i32);
478 SDValue False = DAG.getConstant(0, MVT::i32);
480 return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc());
483 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
485 SelectionDAG &DAG = DCI.DAG;
486 unsigned opc = N->getOpcode();
491 return PerformADDECombine(N, DAG, DCI, Subtarget);
493 return PerformSUBECombine(N, DAG, DCI, Subtarget);
496 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
498 return PerformSETCCCombine(N, DAG, DCI, Subtarget);
504 SDValue MipsTargetLowering::
505 LowerOperation(SDValue Op, SelectionDAG &DAG) const
507 switch (Op.getOpcode())
509 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
510 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
511 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
512 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
513 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
514 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
515 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
516 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
517 case ISD::SELECT: return LowerSELECT(Op, DAG);
518 case ISD::VASTART: return LowerVASTART(Op, DAG);
523 //===----------------------------------------------------------------------===//
524 // Lower helper functions
525 //===----------------------------------------------------------------------===//
527 // AddLiveIn - This helper function adds the specified physical register to the
528 // MachineFunction as a live in value. It also creates a corresponding
529 // virtual register for it.
531 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
533 assert(RC->contains(PReg) && "Not the correct regclass!");
534 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
535 MF.getRegInfo().addLiveIn(PReg, VReg);
539 // Get fp branch code (not opcode) from condition code.
540 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
541 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
542 return Mips::BRANCH_T;
544 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
545 return Mips::BRANCH_F;
547 return Mips::BRANCH_INVALID;
551 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
552 MachineBasicBlock *BB) const {
553 // There is no need to expand CMov instructions if target has
554 // conditional moves.
555 if (Subtarget->hasCondMov())
558 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
559 bool isFPCmp = false;
560 DebugLoc dl = MI->getDebugLoc();
563 switch (MI->getOpcode()) {
564 default: assert(false && "Unexpected instr type to insert");
589 // To "insert" a SELECT_CC instruction, we actually have to insert the
590 // diamond control-flow pattern. The incoming instruction knows the
591 // destination vreg to set, the condition code register to branch on, the
592 // true/false values to select between, and a branch opcode to use.
593 const BasicBlock *LLVM_BB = BB->getBasicBlock();
594 MachineFunction::iterator It = BB;
601 // bNE r1, r0, copy1MBB
602 // fallthrough --> copy0MBB
603 MachineBasicBlock *thisMBB = BB;
604 MachineFunction *F = BB->getParent();
605 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
606 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
607 F->insert(It, copy0MBB);
608 F->insert(It, sinkMBB);
610 // Transfer the remainder of BB and its successor edges to sinkMBB.
611 sinkMBB->splice(sinkMBB->begin(), BB,
612 llvm::next(MachineBasicBlock::iterator(MI)),
614 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
616 // Next, add the true and fallthrough blocks as its successors.
617 BB->addSuccessor(copy0MBB);
618 BB->addSuccessor(sinkMBB);
620 // Emit the right instruction according to the type of the operands compared
622 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
624 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
625 .addReg(Mips::ZERO).addMBB(sinkMBB);
630 // # fallthrough to sinkMBB
633 // Update machine-CFG edges
634 BB->addSuccessor(sinkMBB);
637 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
642 BuildMI(*BB, BB->begin(), dl,
643 TII->get(Mips::PHI), MI->getOperand(0).getReg())
644 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
645 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
647 BuildMI(*BB, BB->begin(), dl,
648 TII->get(Mips::PHI), MI->getOperand(0).getReg())
649 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
650 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
652 MI->eraseFromParent(); // The pseudo instruction is gone now.
656 //===----------------------------------------------------------------------===//
657 // Misc Lower Operation implementation
658 //===----------------------------------------------------------------------===//
660 SDValue MipsTargetLowering::
661 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
663 if (!Subtarget->isMips1())
666 MachineFunction &MF = DAG.getMachineFunction();
667 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
669 SDValue Chain = DAG.getEntryNode();
670 DebugLoc dl = Op.getDebugLoc();
671 SDValue Src = Op.getOperand(0);
673 // Set the condition register
674 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
675 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
676 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
678 SDValue Cst = DAG.getConstant(3, MVT::i32);
679 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
680 Cst = DAG.getConstant(2, MVT::i32);
681 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
683 SDValue InFlag(0, 0);
684 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
686 // Emit the round instruction and bit convert to integer
687 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
688 Src, CondReg.getValue(1));
689 SDValue BitCvt = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Trunc);
693 SDValue MipsTargetLowering::
694 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
696 SDValue Chain = Op.getOperand(0);
697 SDValue Size = Op.getOperand(1);
698 DebugLoc dl = Op.getDebugLoc();
700 // Get a reference from Mips stack pointer
701 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
703 // Subtract the dynamic size from the actual stack size to
704 // obtain the new stack size.
705 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
707 // The Sub result contains the new stack start address, so it
708 // must be placed in the stack pointer register.
709 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
711 // This node always has two return values: a new stack pointer
713 SDValue Ops[2] = { Sub, Chain };
714 return DAG.getMergeValues(Ops, 2, dl);
717 SDValue MipsTargetLowering::
718 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
720 // The first operand is the chain, the second is the condition, the third is
721 // the block to branch to if the condition is true.
722 SDValue Chain = Op.getOperand(0);
723 SDValue Dest = Op.getOperand(2);
724 DebugLoc dl = Op.getDebugLoc();
726 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
728 // Return if flag is not set by a floating point comparison.
729 if (CondRes.getOpcode() != MipsISD::FPCmp)
732 SDValue CCNode = CondRes.getOperand(2);
734 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
735 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
737 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
741 SDValue MipsTargetLowering::
742 LowerSELECT(SDValue Op, SelectionDAG &DAG) const
744 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
746 // Return if flag is not set by a floating point comparison.
747 if (Cond.getOpcode() != MipsISD::FPCmp)
750 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
754 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
755 SelectionDAG &DAG) const {
756 // FIXME there isn't actually debug info here
757 DebugLoc dl = Op.getDebugLoc();
758 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
760 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
761 SDVTList VTs = DAG.getVTList(MVT::i32);
763 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
765 // %gp_rel relocation
766 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
767 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
769 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
770 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
771 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
773 // %hi/%lo relocation
774 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
776 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
778 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
779 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
780 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
782 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
784 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
785 DAG.getEntryNode(), GA, MachinePointerInfo(),
787 // On functions and global targets not internal linked only
788 // a load from got/GP is necessary for PIC to work.
789 if (!GV->hasInternalLinkage() &&
790 (!GV->hasLocalLinkage() || isa<Function>(GV)))
792 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
794 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
795 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
798 llvm_unreachable("Dont know how to handle GlobalAddress");
802 SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
803 SelectionDAG &DAG) const {
804 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
805 // FIXME there isn't actually debug info here
806 DebugLoc dl = Op.getDebugLoc();
808 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
809 // %hi/%lo relocation
810 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true,
812 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true,
814 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
815 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
816 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
819 SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true,
821 SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true,
823 SDValue Load = DAG.getLoad(MVT::i32, dl,
824 DAG.getEntryNode(), BAGOTOffset,
825 MachinePointerInfo(), false, false, 0);
826 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset);
827 return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
830 SDValue MipsTargetLowering::
831 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
833 llvm_unreachable("TLS not implemented for MIPS.");
834 return SDValue(); // Not reached
837 SDValue MipsTargetLowering::
838 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
842 // FIXME there isn't actually debug info here
843 DebugLoc dl = Op.getDebugLoc();
844 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
845 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI;
847 EVT PtrVT = Op.getValueType();
848 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
850 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
853 SDValue Ops[] = { JTI };
854 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
855 } else // Emit Load from Global Pointer
856 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI,
857 MachinePointerInfo(),
860 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
862 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo);
863 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
868 SDValue MipsTargetLowering::
869 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
872 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
873 const Constant *C = N->getConstVal();
874 // FIXME there isn't actually debug info here
875 DebugLoc dl = Op.getDebugLoc();
878 // FIXME: we should reference the constant pool using small data sections,
879 // but the asm printer currently doesn't support this feature without
880 // hacking it. This feature should come soon so we can uncomment the
882 //if (IsInSmallSection(C->getType())) {
883 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
884 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
885 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
887 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
888 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
889 N->getOffset(), MipsII::MO_ABS_HI);
890 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
891 N->getOffset(), MipsII::MO_ABS_LO);
892 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
893 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
894 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
896 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
897 N->getOffset(), MipsII::MO_GOT);
898 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(),
899 CP, MachinePointerInfo::getConstantPool(),
901 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
902 N->getOffset(), MipsII::MO_ABS_LO);
903 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
904 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
910 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
911 MachineFunction &MF = DAG.getMachineFunction();
912 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
914 DebugLoc dl = Op.getDebugLoc();
915 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
918 // vastart just stores the address of the VarArgsFrameIndex slot into the
919 // memory location argument.
920 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
921 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
922 MachinePointerInfo(SV),
926 //===----------------------------------------------------------------------===//
927 // Calling Convention Implementation
928 //===----------------------------------------------------------------------===//
930 #include "MipsGenCallingConv.inc"
932 //===----------------------------------------------------------------------===//
933 // TODO: Implement a generic logic using tblgen that can support this.
934 // Mips O32 ABI rules:
936 // i32 - Passed in A0, A1, A2, A3 and stack
937 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
938 // an argument. Otherwise, passed in A1, A2, A3 and stack.
939 // f64 - Only passed in two aliased f32 registers if no int reg has been used
940 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
941 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
943 //===----------------------------------------------------------------------===//
945 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
946 MVT LocVT, CCValAssign::LocInfo LocInfo,
947 ISD::ArgFlagsTy ArgFlags, CCState &State) {
949 static const unsigned IntRegsSize=4, FloatRegsSize=2;
951 static const unsigned IntRegs[] = {
952 Mips::A0, Mips::A1, Mips::A2, Mips::A3
954 static const unsigned F32Regs[] = {
957 static const unsigned F64Regs[] = {
962 static bool IntRegUsed = false;
964 // This must be the first arg of the call if no regs have been allocated.
965 // Initialize IntRegUsed in that case.
966 if (IntRegs[State.getFirstUnallocated(IntRegs, IntRegsSize)] == Mips::A0 &&
967 F32Regs[State.getFirstUnallocated(F32Regs, FloatRegsSize)] == Mips::F12 &&
968 F64Regs[State.getFirstUnallocated(F64Regs, FloatRegsSize)] == Mips::D6)
971 // Promote i8 and i16
972 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
974 if (ArgFlags.isSExt())
975 LocInfo = CCValAssign::SExt;
976 else if (ArgFlags.isZExt())
977 LocInfo = CCValAssign::ZExt;
979 LocInfo = CCValAssign::AExt;
982 if (ValVT == MVT::i32) {
983 Reg = State.AllocateReg(IntRegs, IntRegsSize);
985 } else if (ValVT == MVT::f32) {
986 // An int reg has to be marked allocated regardless of whether or not
987 // IntRegUsed is true.
988 Reg = State.AllocateReg(IntRegs, IntRegsSize);
991 if (Reg) // Int reg is available
994 unsigned FReg = State.AllocateReg(F32Regs, FloatRegsSize);
995 if (FReg) // F32 reg is available
997 else if (Reg) // No F32 regs are available, but an int reg is available.
1000 } else if (ValVT == MVT::f64) {
1001 // Int regs have to be marked allocated regardless of whether or not
1002 // IntRegUsed is true.
1003 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1004 if (Reg == Mips::A1)
1005 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1006 else if (Reg == Mips::A3)
1008 State.AllocateReg(IntRegs, IntRegsSize);
1010 // At this point, Reg is A0, A2 or 0, and all the unavailable integer regs
1011 // are marked as allocated.
1013 if (Reg)// if int reg is available
1016 unsigned FReg = State.AllocateReg(F64Regs, FloatRegsSize);
1017 if (FReg) // F64 reg is available.
1019 else if (Reg) // No F64 regs are available, but an int reg is available.
1023 assert(false && "cannot handle this ValVT");
1026 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
1027 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
1028 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
1030 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1032 return false; // CC must always match
1035 static bool CC_MipsO32_VarArgs(unsigned ValNo, MVT ValVT,
1036 MVT LocVT, CCValAssign::LocInfo LocInfo,
1037 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1039 static const unsigned IntRegsSize=4;
1041 static const unsigned IntRegs[] = {
1042 Mips::A0, Mips::A1, Mips::A2, Mips::A3
1045 // Promote i8 and i16
1046 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
1048 if (ArgFlags.isSExt())
1049 LocInfo = CCValAssign::SExt;
1050 else if (ArgFlags.isZExt())
1051 LocInfo = CCValAssign::ZExt;
1053 LocInfo = CCValAssign::AExt;
1058 if (ValVT == MVT::i32 || ValVT == MVT::f32) {
1059 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1061 } else if (ValVT == MVT::f64) {
1062 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1063 if (Reg == Mips::A1 || Reg == Mips::A3)
1064 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1065 State.AllocateReg(IntRegs, IntRegsSize);
1068 llvm_unreachable("Cannot handle this ValVT.");
1071 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
1072 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
1073 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
1075 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1077 return false; // CC must always match
1080 //===----------------------------------------------------------------------===//
1081 // Call Calling Convention Implementation
1082 //===----------------------------------------------------------------------===//
1084 /// LowerCall - functions arguments are copied from virtual regs to
1085 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
1086 /// TODO: isTailCall.
1088 MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1089 CallingConv::ID CallConv, bool isVarArg,
1091 const SmallVectorImpl<ISD::OutputArg> &Outs,
1092 const SmallVectorImpl<SDValue> &OutVals,
1093 const SmallVectorImpl<ISD::InputArg> &Ins,
1094 DebugLoc dl, SelectionDAG &DAG,
1095 SmallVectorImpl<SDValue> &InVals) const {
1096 // MIPs target does not yet support tail call optimization.
1099 MachineFunction &MF = DAG.getMachineFunction();
1100 MachineFrameInfo *MFI = MF.getFrameInfo();
1101 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1103 // Analyze operands of the call, assigning locations to each operand.
1104 SmallVector<CCValAssign, 16> ArgLocs;
1105 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1108 // To meet O32 ABI, Mips must always allocate 16 bytes on
1109 // the stack (even if less than 4 are used as arguments)
1110 if (Subtarget->isABI_O32()) {
1111 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
1112 MFI->CreateFixedObject(VTsize, (VTsize*3), true);
1113 CCInfo.AnalyzeCallOperands(Outs,
1114 isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32);
1116 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
1118 // Get a count of how many bytes are to be pushed on the stack.
1119 unsigned NumBytes = CCInfo.getNextStackOffset();
1120 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1122 // With EABI is it possible to have 16 args on registers.
1123 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
1124 SmallVector<SDValue, 8> MemOpChains;
1126 // First/LastArgStackLoc contains the first/last
1127 // "at stack" argument location.
1128 int LastArgStackLoc = 0;
1129 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
1131 // Walk the register/memloc assignments, inserting copies/loads.
1132 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1133 SDValue Arg = OutVals[i];
1134 CCValAssign &VA = ArgLocs[i];
1136 // Promote the value if needed.
1137 switch (VA.getLocInfo()) {
1138 default: llvm_unreachable("Unknown loc info!");
1139 case CCValAssign::Full:
1140 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
1141 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
1142 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
1143 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
1144 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1145 Arg, DAG.getConstant(0, MVT::i32));
1146 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1147 Arg, DAG.getConstant(1, MVT::i32));
1148 if (!Subtarget->isLittle())
1150 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
1151 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
1156 case CCValAssign::SExt:
1157 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1159 case CCValAssign::ZExt:
1160 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1162 case CCValAssign::AExt:
1163 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1167 // Arguments that can be passed on register must be kept at
1168 // RegsToPass vector
1169 if (VA.isRegLoc()) {
1170 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1174 // Register can't get to this point...
1175 assert(VA.isMemLoc());
1177 // Create the frame index object for this incoming parameter
1178 // This guarantees that when allocating Local Area the firsts
1179 // 16 bytes which are alwayes reserved won't be overwritten
1180 // if O32 ABI is used. For EABI the first address is zero.
1181 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
1182 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1183 LastArgStackLoc, true);
1185 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
1187 // emit ISD::STORE whichs stores the
1188 // parameter value to a stack Location
1189 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
1190 MachinePointerInfo(),
1194 // Transform all store nodes into one single node because all store
1195 // nodes are independent of each other.
1196 if (!MemOpChains.empty())
1197 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1198 &MemOpChains[0], MemOpChains.size());
1200 // Build a sequence of copy-to-reg nodes chained together with token
1201 // chain and flag operands which copy the outgoing args into registers.
1202 // The InFlag in necessary since all emitted instructions must be
1205 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1206 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1207 RegsToPass[i].second, InFlag);
1208 InFlag = Chain.getValue(1);
1211 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1212 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1213 // node so that legalize doesn't hack it.
1214 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
1215 bool LoadSymAddr = false;
1218 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1219 if (IsPIC && G->getGlobal()->hasInternalLinkage()) {
1220 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
1221 getPointerTy(), 0,MipsII:: MO_GOT);
1222 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
1223 0, MipsII::MO_ABS_LO);
1225 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
1226 getPointerTy(), 0, OpFlag);
1231 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1232 Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
1233 getPointerTy(), OpFlag);
1237 // Create nodes that load address of callee and copy it to T9
1240 // Load callee address
1241 SDValue LoadValue = DAG.getLoad(MVT::i32, dl, Chain, Callee,
1242 MachinePointerInfo::getGOT(),
1245 // Use GOT+LO if callee has internal linkage.
1246 if (CalleeLo.getNode()) {
1247 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CalleeLo);
1248 Callee = DAG.getNode(ISD::ADD, dl, MVT::i32, LoadValue, Lo);
1252 // Use chain output from LoadValue
1253 Chain = LoadValue.getValue(1);
1257 Chain = DAG.getCopyToReg(Chain, dl, Mips::T9, Callee, SDValue(0, 0));
1258 InFlag = Chain.getValue(1);
1259 Callee = DAG.getRegister(Mips::T9, MVT::i32);
1262 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
1263 // = Chain, Callee, Reg#1, Reg#2, ...
1265 // Returns a chain & a flag for retval copy to use.
1266 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1267 SmallVector<SDValue, 8> Ops;
1268 Ops.push_back(Chain);
1269 Ops.push_back(Callee);
1271 // Add argument registers to the end of the list so that they are
1272 // known live into the call.
1273 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1274 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1275 RegsToPass[i].second.getValueType()));
1277 if (InFlag.getNode())
1278 Ops.push_back(InFlag);
1280 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
1281 InFlag = Chain.getValue(1);
1283 // Create a stack location to hold GP when PIC is used. This stack
1284 // location is used on function prologue to save GP and also after all
1285 // emitted CALL's to restore GP.
1287 // Function can have an arbitrary number of calls, so
1288 // hold the LastArgStackLoc with the biggest offset.
1290 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1291 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
1292 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
1293 // Create the frame index only once. SPOffset here can be anything
1294 // (this will be fixed on processFunctionBeforeFrameFinalized)
1295 if (MipsFI->getGPStackOffset() == -1) {
1296 FI = MFI->CreateFixedObject(4, 0, true);
1297 MipsFI->setGPFI(FI);
1299 MipsFI->setGPStackOffset(LastArgStackLoc);
1303 FI = MipsFI->getGPFI();
1304 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1305 SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN,
1306 MachinePointerInfo::getFixedStack(FI),
1308 Chain = GPLoad.getValue(1);
1309 Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
1310 GPLoad, SDValue(0,0));
1311 InFlag = Chain.getValue(1);
1314 // Create the CALLSEQ_END node.
1315 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1316 DAG.getIntPtrConstant(0, true), InFlag);
1317 InFlag = Chain.getValue(1);
1319 // Handle result values, copying them out of physregs into vregs that we
1321 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
1322 Ins, dl, DAG, InVals);
1325 /// LowerCallResult - Lower the result values of a call into the
1326 /// appropriate copies out of appropriate physical registers.
1328 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1329 CallingConv::ID CallConv, bool isVarArg,
1330 const SmallVectorImpl<ISD::InputArg> &Ins,
1331 DebugLoc dl, SelectionDAG &DAG,
1332 SmallVectorImpl<SDValue> &InVals) const {
1334 // Assign locations to each value returned by this call.
1335 SmallVector<CCValAssign, 16> RVLocs;
1336 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1337 RVLocs, *DAG.getContext());
1339 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
1341 // Copy all of the result registers out of their specified physreg.
1342 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1343 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
1344 RVLocs[i].getValVT(), InFlag).getValue(1);
1345 InFlag = Chain.getValue(2);
1346 InVals.push_back(Chain.getValue(0));
1352 //===----------------------------------------------------------------------===//
1353 // Formal Arguments Calling Convention Implementation
1354 //===----------------------------------------------------------------------===//
1356 /// LowerFormalArguments - transform physical registers into virtual registers
1357 /// and generate load operations for arguments places on the stack.
1359 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
1360 CallingConv::ID CallConv,
1362 const SmallVectorImpl<ISD::InputArg>
1364 DebugLoc dl, SelectionDAG &DAG,
1365 SmallVectorImpl<SDValue> &InVals)
1368 MachineFunction &MF = DAG.getMachineFunction();
1369 MachineFrameInfo *MFI = MF.getFrameInfo();
1370 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1372 MipsFI->setVarArgsFrameIndex(0);
1374 // Used with vargs to acumulate store chains.
1375 std::vector<SDValue> OutChains;
1377 // Keep track of the last register used for arguments
1378 unsigned ArgRegEnd = 0;
1380 // Assign locations to all of the incoming arguments.
1381 SmallVector<CCValAssign, 16> ArgLocs;
1382 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1383 ArgLocs, *DAG.getContext());
1385 if (Subtarget->isABI_O32())
1386 CCInfo.AnalyzeFormalArguments(Ins,
1387 isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32);
1389 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
1391 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
1392 unsigned LastStackArgEndOffset = 0;
1393 EVT LastRegArgValVT;
1395 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1396 CCValAssign &VA = ArgLocs[i];
1398 // Arguments stored on registers
1399 if (VA.isRegLoc()) {
1400 EVT RegVT = VA.getLocVT();
1401 ArgRegEnd = VA.getLocReg();
1402 LastRegArgValVT = VA.getValVT();
1403 TargetRegisterClass *RC = 0;
1405 if (RegVT == MVT::i32)
1406 RC = Mips::CPURegsRegisterClass;
1407 else if (RegVT == MVT::f32)
1408 RC = Mips::FGR32RegisterClass;
1409 else if (RegVT == MVT::f64) {
1410 if (!Subtarget->isSingleFloat())
1411 RC = Mips::AFGR64RegisterClass;
1413 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
1415 // Transform the arguments stored on
1416 // physical registers into virtual ones
1417 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
1418 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1420 // If this is an 8 or 16-bit value, it has been passed promoted
1421 // to 32 bits. Insert an assert[sz]ext to capture this, then
1422 // truncate to the right size.
1423 if (VA.getLocInfo() != CCValAssign::Full) {
1424 unsigned Opcode = 0;
1425 if (VA.getLocInfo() == CCValAssign::SExt)
1426 Opcode = ISD::AssertSext;
1427 else if (VA.getLocInfo() == CCValAssign::ZExt)
1428 Opcode = ISD::AssertZext;
1430 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
1431 DAG.getValueType(VA.getValVT()));
1432 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1435 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
1436 if (Subtarget->isABI_O32()) {
1437 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
1438 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue);
1439 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
1440 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
1441 VA.getLocReg()+1, RC);
1442 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
1443 if (!Subtarget->isLittle())
1444 std::swap(ArgValue, ArgValue2);
1445 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
1446 ArgValue, ArgValue2);
1450 InVals.push_back(ArgValue);
1451 } else { // VA.isRegLoc()
1454 assert(VA.isMemLoc());
1456 // The last argument is not a register anymore
1459 // The stack pointer offset is relative to the caller stack frame.
1460 // Since the real stack size is unknown here, a negative SPOffset
1461 // is used so there's a way to adjust these offsets when the stack
1462 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1463 // used instead of a direct negative address (which is recorded to
1464 // be used on emitPrologue) to avoid mis-calc of the first stack
1465 // offset on PEI::calculateFrameObjectOffsets.
1466 unsigned ArgSize = VA.getValVT().getSizeInBits()/8;
1467 LastStackArgEndOffset = FirstStackArgLoc + VA.getLocMemOffset() + ArgSize;
1468 int FI = MFI->CreateFixedObject(ArgSize, 0, true);
1469 MipsFI->recordLoadArgsFI(FI, -(4 +
1470 (FirstStackArgLoc + VA.getLocMemOffset())));
1472 // Create load nodes to retrieve arguments from the stack
1473 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1474 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1475 MachinePointerInfo::getFixedStack(FI),
1480 // The mips ABIs for returning structs by value requires that we copy
1481 // the sret argument into $v0 for the return. Save the argument into
1482 // a virtual register so that we can access it from the return points.
1483 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1484 unsigned Reg = MipsFI->getSRetReturnReg();
1486 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1487 MipsFI->setSRetReturnReg(Reg);
1489 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1490 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1493 // To meet ABI, when VARARGS are passed on registers, the registers
1494 // must have their values written to the caller stack frame. If the last
1495 // argument was placed in the stack, there's no need to save any register.
1496 if (isVarArg && Subtarget->isABI_O32()) {
1498 // Last named formal argument is passed in register.
1500 // The last register argument that must be saved is Mips::A3
1501 TargetRegisterClass *RC = Mips::CPURegsRegisterClass;
1502 if (LastRegArgValVT == MVT::f64)
1505 if (ArgRegEnd < Mips::A3) {
1506 // Both the last named formal argument and the first variable
1507 // argument are passed in registers.
1508 for (++ArgRegEnd; ArgRegEnd <= Mips::A3; ++ArgRegEnd) {
1509 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
1510 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
1512 int FI = MFI->CreateFixedObject(4, 0, true);
1513 MipsFI->recordStoreVarArgsFI(FI, -(4+(ArgRegEnd-Mips::A0)*4));
1514 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
1515 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
1516 MachinePointerInfo(),
1519 // Record the frame index of the first variable argument
1520 // which is a value necessary to VASTART.
1521 if (!MipsFI->getVarArgsFrameIndex()) {
1522 MFI->setObjectAlignment(FI, 4);
1523 MipsFI->setVarArgsFrameIndex(FI);
1527 // Last named formal argument is in register Mips::A3, and the first
1528 // variable argument is on stack. Record the frame index of the first
1529 // variable argument.
1530 int FI = MFI->CreateFixedObject(4, 0, true);
1531 MFI->setObjectAlignment(FI, 4);
1532 MipsFI->recordStoreVarArgsFI(FI, -20);
1533 MipsFI->setVarArgsFrameIndex(FI);
1536 // Last named formal argument and all the variable arguments are passed
1537 // on stack. Record the frame index of the first variable argument.
1538 int FI = MFI->CreateFixedObject(4, 0, true);
1539 MFI->setObjectAlignment(FI, 4);
1540 MipsFI->recordStoreVarArgsFI(FI, -(4+LastStackArgEndOffset));
1541 MipsFI->setVarArgsFrameIndex(FI);
1545 // All stores are grouped in one node to allow the matching between
1546 // the size of Ins and InVals. This only happens when on varg functions
1547 if (!OutChains.empty()) {
1548 OutChains.push_back(Chain);
1549 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1550 &OutChains[0], OutChains.size());
1556 //===----------------------------------------------------------------------===//
1557 // Return Value Calling Convention Implementation
1558 //===----------------------------------------------------------------------===//
1561 MipsTargetLowering::LowerReturn(SDValue Chain,
1562 CallingConv::ID CallConv, bool isVarArg,
1563 const SmallVectorImpl<ISD::OutputArg> &Outs,
1564 const SmallVectorImpl<SDValue> &OutVals,
1565 DebugLoc dl, SelectionDAG &DAG) const {
1567 // CCValAssign - represent the assignment of
1568 // the return value to a location
1569 SmallVector<CCValAssign, 16> RVLocs;
1571 // CCState - Info about the registers and stack slot.
1572 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1573 RVLocs, *DAG.getContext());
1575 // Analize return values.
1576 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
1578 // If this is the first return lowered for this function, add
1579 // the regs to the liveout set for the function.
1580 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1581 for (unsigned i = 0; i != RVLocs.size(); ++i)
1582 if (RVLocs[i].isRegLoc())
1583 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1588 // Copy the result values into the output registers.
1589 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1590 CCValAssign &VA = RVLocs[i];
1591 assert(VA.isRegLoc() && "Can only return in registers!");
1593 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1596 // guarantee that all emitted copies are
1597 // stuck together, avoiding something bad
1598 Flag = Chain.getValue(1);
1601 // The mips ABIs for returning structs by value requires that we copy
1602 // the sret argument into $v0 for the return. We saved the argument into
1603 // a virtual register in the entry block, so now we copy the value out
1605 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1606 MachineFunction &MF = DAG.getMachineFunction();
1607 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1608 unsigned Reg = MipsFI->getSRetReturnReg();
1611 llvm_unreachable("sret virtual register not created in the entry block");
1612 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1614 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1615 Flag = Chain.getValue(1);
1618 // Return on Mips is always a "jr $ra"
1620 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1621 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1623 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1624 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1627 //===----------------------------------------------------------------------===//
1628 // Mips Inline Assembly Support
1629 //===----------------------------------------------------------------------===//
1631 /// getConstraintType - Given a constraint letter, return the type of
1632 /// constraint it is for this target.
1633 MipsTargetLowering::ConstraintType MipsTargetLowering::
1634 getConstraintType(const std::string &Constraint) const
1636 // Mips specific constrainy
1637 // GCC config/mips/constraints.md
1639 // 'd' : An address register. Equivalent to r
1640 // unless generating MIPS16 code.
1641 // 'y' : Equivalent to r; retained for
1642 // backwards compatibility.
1643 // 'f' : Floating Point registers.
1644 if (Constraint.size() == 1) {
1645 switch (Constraint[0]) {
1650 return C_RegisterClass;
1654 return TargetLowering::getConstraintType(Constraint);
1657 /// Examine constraint type and operand type and determine a weight value.
1658 /// This object must already have been set up with the operand type
1659 /// and the current alternative constraint selected.
1660 TargetLowering::ConstraintWeight
1661 MipsTargetLowering::getSingleConstraintMatchWeight(
1662 AsmOperandInfo &info, const char *constraint) const {
1663 ConstraintWeight weight = CW_Invalid;
1664 Value *CallOperandVal = info.CallOperandVal;
1665 // If we don't have a value, we can't do a match,
1666 // but allow it at the lowest weight.
1667 if (CallOperandVal == NULL)
1669 const Type *type = CallOperandVal->getType();
1670 // Look at the constraint type.
1671 switch (*constraint) {
1673 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1677 if (type->isIntegerTy())
1678 weight = CW_Register;
1681 if (type->isFloatTy())
1682 weight = CW_Register;
1688 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1689 /// return a list of registers that can be used to satisfy the constraint.
1690 /// This should only be used for C_RegisterClass constraints.
1691 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1692 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
1694 if (Constraint.size() == 1) {
1695 switch (Constraint[0]) {
1697 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1700 return std::make_pair(0U, Mips::FGR32RegisterClass);
1702 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1703 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1706 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1709 /// Given a register class constraint, like 'r', if this corresponds directly
1710 /// to an LLVM register class, return a register of 0 and the register class
1712 std::vector<unsigned> MipsTargetLowering::
1713 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1716 if (Constraint.size() != 1)
1717 return std::vector<unsigned>();
1719 switch (Constraint[0]) {
1722 // GCC Mips Constraint Letters
1725 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1726 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1727 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1731 if (VT == MVT::f32) {
1732 if (Subtarget->isSingleFloat())
1733 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1734 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1735 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1736 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1737 Mips::F30, Mips::F31, 0);
1739 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1740 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1741 Mips::F28, Mips::F30, 0);
1745 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1746 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1747 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1748 Mips::D14, Mips::D15, 0);
1750 return std::vector<unsigned>();
1754 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1755 // The Mips target isn't yet aware of offsets.
1759 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
1760 if (VT != MVT::f32 && VT != MVT::f64)
1762 if (Imm.isNegZero())
1764 return Imm.isZero();