1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "MCTargetDesc/MipsBaseInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Target/TargetLowering.h"
31 // Start the numbering from where ISD NodeType finishes.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 // Jump and link (call)
40 // Get the Higher 16 bits from a 32-bit immediate
41 // No relation with Mips Hi register
44 // Get the Lower 16 bits from a 32-bit immediate
45 // No relation with Mips Lo register
48 // Handle gp_rel (small data/bss sections) relocation.
54 // Floating Point Branch Conditional
57 // Floating Point Compare
60 // Floating Point Conditional Moves
64 // FP-to-int truncation node.
72 // Node used to extract integer from accumulator.
76 // Node used to insert integers to accumulator.
107 // EXTR.W instrinsic nodes.
117 // DPA.W intrinsic nodes.
153 // DSP setcc and select_cc nodes.
157 // Vector comparisons.
158 // These take a vector and return a boolean.
164 // These take a vector and return a vector bitmask.
171 // Element-wise vector max/min.
177 // Vector Shuffle with mask as an operand
178 VSHF, // Generic shuffle
179 SHF, // 4-element set shuffle.
180 ILVEV, // Interleave even elements
181 ILVOD, // Interleave odd elements
182 ILVL, // Interleave left elements
183 ILVR, // Interleave right elements
184 PCKEV, // Pack even elements
185 PCKOD, // Pack odd elements
187 // Combined (XOR (OR $a, $b), -1)
190 // Extended vector element extraction
194 // Load/Store Left/Right nodes.
195 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
206 //===--------------------------------------------------------------------===//
207 // TargetLowering Implementation
208 //===--------------------------------------------------------------------===//
209 class MipsFunctionInfo;
211 class MipsTargetLowering : public TargetLowering {
213 explicit MipsTargetLowering(MipsTargetMachine &TM);
215 static const MipsTargetLowering *create(MipsTargetMachine &TM);
217 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
219 virtual void LowerOperationWrapper(SDNode *N,
220 SmallVectorImpl<SDValue> &Results,
221 SelectionDAG &DAG) const;
223 /// LowerOperation - Provide custom lowering hooks for some operations.
224 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
226 /// ReplaceNodeResults - Replace the results of node with an illegal result
227 /// type with new values built out of custom code.
229 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
230 SelectionDAG &DAG) const;
232 /// getTargetNodeName - This method returns the name of a target specific
234 virtual const char *getTargetNodeName(unsigned Opcode) const;
236 /// getSetCCResultType - get the ISD::SETCC result ValueType
237 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
239 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
241 virtual MachineBasicBlock *
242 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
245 bool operator()(const char *S1, const char *S2) const {
246 return strcmp(S1, S2) < 0;
251 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
253 // This method creates the following nodes, which are necessary for
254 // computing a local symbol's address:
256 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
257 template<class NodeTy>
258 SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
259 bool HasMips64) const {
261 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
262 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
263 getTargetNode(N, Ty, DAG, GOTFlag));
264 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
265 MachinePointerInfo::getGOT(), false, false,
267 unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
268 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
269 getTargetNode(N, Ty, DAG, LoFlag));
270 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
273 // This method creates the following nodes, which are necessary for
274 // computing a global symbol's address:
276 // (load (wrapper $gp, %got(sym)))
277 template<class NodeTy>
278 SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
279 unsigned Flag, SDValue Chain,
280 const MachinePointerInfo &PtrInfo) const {
282 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
283 getTargetNode(N, Ty, DAG, Flag));
284 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
287 // This method creates the following nodes, which are necessary for
288 // computing a global symbol's address in large-GOT mode:
290 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
291 template<class NodeTy>
292 SDValue getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG,
293 unsigned HiFlag, unsigned LoFlag,
295 const MachinePointerInfo &PtrInfo) const {
297 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty,
298 getTargetNode(N, Ty, DAG, HiFlag));
299 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
300 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
301 getTargetNode(N, Ty, DAG, LoFlag));
302 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
306 // This method creates the following nodes, which are necessary for
307 // computing a symbol's address in non-PIC mode:
309 // (add %hi(sym), %lo(sym))
310 template<class NodeTy>
311 SDValue getAddrNonPIC(NodeTy *N, EVT Ty, SelectionDAG &DAG) const {
313 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
314 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
315 return DAG.getNode(ISD::ADD, DL, Ty,
316 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
317 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
320 /// This function fills Ops, which is the list of operands that will later
321 /// be used when a function call node is created. It also generates
322 /// copyToReg nodes to set up argument registers.
324 getOpndList(SmallVectorImpl<SDValue> &Ops,
325 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
326 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
327 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
329 /// ByValArgInfo - Byval argument information.
330 struct ByValArgInfo {
331 unsigned FirstIdx; // Index of the first register used.
332 unsigned NumRegs; // Number of registers used for this argument.
333 unsigned Address; // Offset of the stack area used to pass this argument.
335 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
338 /// MipsCC - This class provides methods used to analyze formal and call
339 /// arguments and inquire about calling convention information.
342 enum SpecialCallingConvType {
343 Mips16RetHelperConv, NoSpecialCallingConv
346 MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
347 SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
350 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
351 bool IsVarArg, bool IsSoftFloat,
352 const SDNode *CallNode,
353 std::vector<ArgListEntry> &FuncArgs);
354 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
356 Function::const_arg_iterator FuncArg);
358 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
359 bool IsSoftFloat, const SDNode *CallNode,
360 const Type *RetTy) const;
362 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
363 bool IsSoftFloat, const Type *RetTy) const;
365 const CCState &getCCInfo() const { return CCInfo; }
367 /// hasByValArg - Returns true if function has byval arguments.
368 bool hasByValArg() const { return !ByValArgs.empty(); }
370 /// regSize - Size (in number of bits) of integer registers.
371 unsigned regSize() const { return IsO32 ? 4 : 8; }
373 /// numIntArgRegs - Number of integer registers available for calls.
374 unsigned numIntArgRegs() const;
376 /// reservedArgArea - The size of the area the caller reserves for
377 /// register arguments. This is 16-byte if ABI is O32.
378 unsigned reservedArgArea() const;
380 /// Return pointer to array of integer argument registers.
381 const uint16_t *intArgRegs() const;
383 typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
384 byval_iterator byval_begin() const { return ByValArgs.begin(); }
385 byval_iterator byval_end() const { return ByValArgs.end(); }
388 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
389 CCValAssign::LocInfo LocInfo,
390 ISD::ArgFlagsTy ArgFlags);
392 /// useRegsForByval - Returns true if the calling convention allows the
393 /// use of registers to pass byval arguments.
394 bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
396 /// Return the function that analyzes fixed argument list functions.
397 llvm::CCAssignFn *fixedArgFn() const;
399 /// Return the function that analyzes variable argument list functions.
400 llvm::CCAssignFn *varArgFn() const;
402 const uint16_t *shadowRegs() const;
404 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
407 /// Return the type of the register which is used to pass an argument or
408 /// return a value. This function returns f64 if the argument is an i64
409 /// value which has been generated as a result of softening an f128 value.
410 /// Otherwise, it just returns VT.
411 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
412 bool IsSoftFloat) const;
414 template<typename Ty>
415 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
416 const SDNode *CallNode, const Type *RetTy) const;
419 CallingConv::ID CallConv;
421 SpecialCallingConvType SpecialCallingConv;
422 SmallVector<ByValArgInfo, 2> ByValArgs;
425 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
426 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
429 const MipsSubtarget *Subtarget;
431 bool HasMips64, IsN64, IsO32;
434 // Create a TargetGlobalAddress node.
435 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
436 unsigned Flag) const;
438 // Create a TargetExternalSymbol node.
439 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
440 unsigned Flag) const;
442 // Create a TargetBlockAddress node.
443 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
444 unsigned Flag) const;
446 // Create a TargetJumpTable node.
447 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
448 unsigned Flag) const;
450 // Create a TargetConstantPool node.
451 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
452 unsigned Flag) const;
454 MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
455 // Lower Operand helpers
456 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
457 CallingConv::ID CallConv, bool isVarArg,
458 const SmallVectorImpl<ISD::InputArg> &Ins,
459 SDLoc dl, SelectionDAG &DAG,
460 SmallVectorImpl<SDValue> &InVals,
461 const SDNode *CallNode, const Type *RetTy) const;
463 // Lower Operand specifics
464 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
465 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
466 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
467 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
468 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
469 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
470 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
471 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
472 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
473 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
474 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
475 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
476 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
477 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
478 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
479 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
480 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
481 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
482 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
484 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
485 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
487 /// isEligibleForTailCallOptimization - Check whether the call is eligible
488 /// for tail call optimization.
490 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
491 unsigned NextStackOffset,
492 const MipsFunctionInfo& FI) const = 0;
494 /// copyByValArg - Copy argument registers which were used to pass a byval
495 /// argument to the stack. Create a stack frame object for the byval
497 void copyByValRegs(SDValue Chain, SDLoc DL,
498 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
499 const ISD::ArgFlagsTy &Flags,
500 SmallVectorImpl<SDValue> &InVals,
501 const Argument *FuncArg,
502 const MipsCC &CC, const ByValArgInfo &ByVal) const;
504 /// passByValArg - Pass a byval argument in registers or on stack.
505 void passByValArg(SDValue Chain, SDLoc DL,
506 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
507 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
508 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
509 const MipsCC &CC, const ByValArgInfo &ByVal,
510 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
512 /// writeVarArgRegs - Write variable function arguments passed in registers
513 /// to the stack. Also create a stack frame object for the first variable
515 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
516 SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
519 LowerFormalArguments(SDValue Chain,
520 CallingConv::ID CallConv, bool isVarArg,
521 const SmallVectorImpl<ISD::InputArg> &Ins,
522 SDLoc dl, SelectionDAG &DAG,
523 SmallVectorImpl<SDValue> &InVals) const;
525 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
526 SDValue Arg, SDLoc DL, bool IsTailCall,
527 SelectionDAG &DAG) const;
530 LowerCall(TargetLowering::CallLoweringInfo &CLI,
531 SmallVectorImpl<SDValue> &InVals) const;
534 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
536 const SmallVectorImpl<ISD::OutputArg> &Outs,
537 LLVMContext &Context) const;
540 LowerReturn(SDValue Chain,
541 CallingConv::ID CallConv, bool isVarArg,
542 const SmallVectorImpl<ISD::OutputArg> &Outs,
543 const SmallVectorImpl<SDValue> &OutVals,
544 SDLoc dl, SelectionDAG &DAG) const;
546 // Inline asm support
547 ConstraintType getConstraintType(const std::string &Constraint) const;
549 /// Examine constraint string and operand type and determine a weight value.
550 /// The operand object must already have been set up with the operand type.
551 ConstraintWeight getSingleConstraintMatchWeight(
552 AsmOperandInfo &info, const char *constraint) const;
554 /// This function parses registers that appear in inline-asm constraints.
555 /// It returns pair (0, 0) on failure.
556 std::pair<unsigned, const TargetRegisterClass *>
557 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
559 std::pair<unsigned, const TargetRegisterClass*>
560 getRegForInlineAsmConstraint(const std::string &Constraint,
563 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
564 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
565 /// true it means one of the asm constraint of the inline asm instruction
566 /// being processed is 'm'.
567 virtual void LowerAsmOperandForConstraint(SDValue Op,
568 std::string &Constraint,
569 std::vector<SDValue> &Ops,
570 SelectionDAG &DAG) const;
572 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
574 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
576 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
578 bool IsMemset, bool ZeroMemset,
580 MachineFunction &MF) const;
582 /// isFPImmLegal - Returns true if the target can instruction select the
583 /// specified FP immediate natively. If false, the legalizer will
584 /// materialize the FP immediate as a load from a constant pool.
585 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
587 virtual unsigned getJumpTableEncoding() const;
589 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
590 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
591 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
592 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
593 bool Nand = false) const;
594 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
595 MachineBasicBlock *BB, unsigned Size) const;
596 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
597 MachineBasicBlock *BB, unsigned Size) const;
600 /// Create MipsTargetLowering objects.
601 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
602 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
605 #endif // MipsISELLOWERING_H