1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/Target/TargetLowering.h"
30 // Start the numbering from where ISD NodeType finishes.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Jump and link (call)
39 // Get the Higher 16 bits from a 32-bit immediate
40 // No relation with Mips Hi register
43 // Get the Lower 16 bits from a 32-bit immediate
44 // No relation with Mips Lo register
47 // Handle gp_rel (small data/bss sections) relocation.
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // FP-to-int truncation node.
71 // Node used to extract integer from accumulator.
74 // Node used to insert integers to accumulator.
105 // EXTR.W instrinsic nodes.
115 // DPA.W intrinsic nodes.
151 // DSP setcc and select_cc nodes.
155 // Load/Store Left/Right nodes.
156 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
167 //===--------------------------------------------------------------------===//
168 // TargetLowering Implementation
169 //===--------------------------------------------------------------------===//
170 class MipsFunctionInfo;
172 class MipsTargetLowering : public TargetLowering {
174 explicit MipsTargetLowering(MipsTargetMachine &TM);
176 static const MipsTargetLowering *create(MipsTargetMachine &TM);
178 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
180 virtual void LowerOperationWrapper(SDNode *N,
181 SmallVectorImpl<SDValue> &Results,
182 SelectionDAG &DAG) const;
184 /// LowerOperation - Provide custom lowering hooks for some operations.
185 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
187 /// ReplaceNodeResults - Replace the results of node with an illegal result
188 /// type with new values built out of custom code.
190 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
191 SelectionDAG &DAG) const;
193 /// getTargetNodeName - This method returns the name of a target specific
195 virtual const char *getTargetNodeName(unsigned Opcode) const;
197 /// getSetCCResultType - get the ISD::SETCC result ValueType
198 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
200 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
202 virtual MachineBasicBlock *
203 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
206 bool operator()(const char *S1, const char *S2) const {
207 return strcmp(S1, S2) < 0;
212 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
214 SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
216 SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
218 SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
219 unsigned HiFlag, unsigned LoFlag) const;
221 /// This function fills Ops, which is the list of operands that will later
222 /// be used when a function call node is created. It also generates
223 /// copyToReg nodes to set up argument registers.
225 getOpndList(SmallVectorImpl<SDValue> &Ops,
226 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
227 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
228 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
230 /// ByValArgInfo - Byval argument information.
231 struct ByValArgInfo {
232 unsigned FirstIdx; // Index of the first register used.
233 unsigned NumRegs; // Number of registers used for this argument.
234 unsigned Address; // Offset of the stack area used to pass this argument.
236 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
239 /// MipsCC - This class provides methods used to analyze formal and call
240 /// arguments and inquire about calling convention information.
243 enum SpecialCallingConvType {
244 Mips16RetHelperConv, NoSpecialCallingConv
247 MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
248 SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
251 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
252 bool IsVarArg, bool IsSoftFloat,
253 const SDNode *CallNode,
254 std::vector<ArgListEntry> &FuncArgs);
255 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
257 Function::const_arg_iterator FuncArg);
259 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
260 bool IsSoftFloat, const SDNode *CallNode,
261 const Type *RetTy) const;
263 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
264 bool IsSoftFloat, const Type *RetTy) const;
266 const CCState &getCCInfo() const { return CCInfo; }
268 /// hasByValArg - Returns true if function has byval arguments.
269 bool hasByValArg() const { return !ByValArgs.empty(); }
271 /// regSize - Size (in number of bits) of integer registers.
272 unsigned regSize() const { return IsO32 ? 4 : 8; }
274 /// numIntArgRegs - Number of integer registers available for calls.
275 unsigned numIntArgRegs() const;
277 /// reservedArgArea - The size of the area the caller reserves for
278 /// register arguments. This is 16-byte if ABI is O32.
279 unsigned reservedArgArea() const;
281 /// Return pointer to array of integer argument registers.
282 const uint16_t *intArgRegs() const;
284 typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
285 byval_iterator byval_begin() const { return ByValArgs.begin(); }
286 byval_iterator byval_end() const { return ByValArgs.end(); }
289 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
290 CCValAssign::LocInfo LocInfo,
291 ISD::ArgFlagsTy ArgFlags);
293 /// useRegsForByval - Returns true if the calling convention allows the
294 /// use of registers to pass byval arguments.
295 bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
297 /// Return the function that analyzes fixed argument list functions.
298 llvm::CCAssignFn *fixedArgFn() const;
300 /// Return the function that analyzes variable argument list functions.
301 llvm::CCAssignFn *varArgFn() const;
303 const uint16_t *shadowRegs() const;
305 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
308 /// Return the type of the register which is used to pass an argument or
309 /// return a value. This function returns f64 if the argument is an i64
310 /// value which has been generated as a result of softening an f128 value.
311 /// Otherwise, it just returns VT.
312 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
313 bool IsSoftFloat) const;
315 template<typename Ty>
316 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
317 const SDNode *CallNode, const Type *RetTy) const;
320 CallingConv::ID CallConv;
322 SpecialCallingConvType SpecialCallingConv;
323 SmallVector<ByValArgInfo, 2> ByValArgs;
327 const MipsSubtarget *Subtarget;
329 bool HasMips64, IsN64, IsO32;
333 MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
334 // Lower Operand helpers
335 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
336 CallingConv::ID CallConv, bool isVarArg,
337 const SmallVectorImpl<ISD::InputArg> &Ins,
338 SDLoc dl, SelectionDAG &DAG,
339 SmallVectorImpl<SDValue> &InVals,
340 const SDNode *CallNode, const Type *RetTy) const;
342 // Lower Operand specifics
343 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
344 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
345 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
346 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
347 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
348 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
349 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
350 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
351 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
352 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
353 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
354 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
355 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
356 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
357 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
358 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
359 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
360 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
361 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
363 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
364 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
365 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
366 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
368 /// isEligibleForTailCallOptimization - Check whether the call is eligible
369 /// for tail call optimization.
371 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
372 unsigned NextStackOffset,
373 const MipsFunctionInfo& FI) const = 0;
375 /// copyByValArg - Copy argument registers which were used to pass a byval
376 /// argument to the stack. Create a stack frame object for the byval
378 void copyByValRegs(SDValue Chain, SDLoc DL,
379 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
380 const ISD::ArgFlagsTy &Flags,
381 SmallVectorImpl<SDValue> &InVals,
382 const Argument *FuncArg,
383 const MipsCC &CC, const ByValArgInfo &ByVal) const;
385 /// passByValArg - Pass a byval argument in registers or on stack.
386 void passByValArg(SDValue Chain, SDLoc DL,
387 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
388 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
389 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
390 const MipsCC &CC, const ByValArgInfo &ByVal,
391 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
393 /// writeVarArgRegs - Write variable function arguments passed in registers
394 /// to the stack. Also create a stack frame object for the first variable
396 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
397 SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
400 LowerFormalArguments(SDValue Chain,
401 CallingConv::ID CallConv, bool isVarArg,
402 const SmallVectorImpl<ISD::InputArg> &Ins,
403 SDLoc dl, SelectionDAG &DAG,
404 SmallVectorImpl<SDValue> &InVals) const;
406 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
407 SDValue Arg, SDLoc DL, bool IsTailCall,
408 SelectionDAG &DAG) const;
411 LowerCall(TargetLowering::CallLoweringInfo &CLI,
412 SmallVectorImpl<SDValue> &InVals) const;
415 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
417 const SmallVectorImpl<ISD::OutputArg> &Outs,
418 LLVMContext &Context) const;
421 LowerReturn(SDValue Chain,
422 CallingConv::ID CallConv, bool isVarArg,
423 const SmallVectorImpl<ISD::OutputArg> &Outs,
424 const SmallVectorImpl<SDValue> &OutVals,
425 SDLoc dl, SelectionDAG &DAG) const;
427 // Inline asm support
428 ConstraintType getConstraintType(const std::string &Constraint) const;
430 /// Examine constraint string and operand type and determine a weight value.
431 /// The operand object must already have been set up with the operand type.
432 ConstraintWeight getSingleConstraintMatchWeight(
433 AsmOperandInfo &info, const char *constraint) const;
435 /// This function parses registers that appear in inline-asm constraints.
436 /// It returns pair (0, 0) on failure.
437 std::pair<unsigned, const TargetRegisterClass *>
438 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
440 std::pair<unsigned, const TargetRegisterClass*>
441 getRegForInlineAsmConstraint(const std::string &Constraint,
444 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
445 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
446 /// true it means one of the asm constraint of the inline asm instruction
447 /// being processed is 'm'.
448 virtual void LowerAsmOperandForConstraint(SDValue Op,
449 std::string &Constraint,
450 std::vector<SDValue> &Ops,
451 SelectionDAG &DAG) const;
453 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
455 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
457 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
459 bool IsMemset, bool ZeroMemset,
461 MachineFunction &MF) const;
463 /// isFPImmLegal - Returns true if the target can instruction select the
464 /// specified FP immediate natively. If false, the legalizer will
465 /// materialize the FP immediate as a load from a constant pool.
466 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
468 virtual unsigned getJumpTableEncoding() const;
470 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
471 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
472 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
473 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
474 bool Nand = false) const;
475 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
476 MachineBasicBlock *BB, unsigned Size) const;
477 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
478 MachineBasicBlock *BB, unsigned Size) const;
481 /// Create MipsTargetLowering objects.
482 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
483 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
486 #endif // MipsISELLOWERING_H