1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetLowering.h"
21 #include "MipsSubtarget.h"
26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 // Jump and link (call)
32 // Get the Higher 16 bits from a 32-bit immediate
33 // No relation with Mips Hi register
36 // Get the Lower 16 bits from a 32-bit immediate
37 // No relation with Mips Lo register
40 // Handle gp_rel (small data/bss sections) relocation.
43 // Floating Point Branch Conditional
46 // Floating Point Compare
49 // Floating Point Conditional Moves
53 // Floating Point Rounding
74 //===--------------------------------------------------------------------===//
75 // TargetLowering Implementation
76 //===--------------------------------------------------------------------===//
78 class MipsTargetLowering : public TargetLowering {
80 explicit MipsTargetLowering(MipsTargetMachine &TM);
82 /// LowerOperation - Provide custom lowering hooks for some operations.
83 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
85 /// getTargetNodeName - This method returns the name of a target specific
87 virtual const char *getTargetNodeName(unsigned Opcode) const;
89 /// getSetCCResultType - get the ISD::SETCC result ValueType
90 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
92 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
95 const MipsSubtarget *Subtarget;
98 // Lower Operand helpers
99 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
100 CallingConv::ID CallConv, bool isVarArg,
101 const SmallVectorImpl<ISD::InputArg> &Ins,
102 DebugLoc dl, SelectionDAG &DAG,
103 SmallVectorImpl<SDValue> &InVals) const;
105 // Lower Operand specifics
106 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
107 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
108 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
109 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
110 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
111 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
112 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
113 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
114 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
115 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
118 LowerFormalArguments(SDValue Chain,
119 CallingConv::ID CallConv, bool isVarArg,
120 const SmallVectorImpl<ISD::InputArg> &Ins,
121 DebugLoc dl, SelectionDAG &DAG,
122 SmallVectorImpl<SDValue> &InVals) const;
125 LowerCall(SDValue Chain, SDValue Callee,
126 CallingConv::ID CallConv, bool isVarArg,
128 const SmallVectorImpl<ISD::OutputArg> &Outs,
129 const SmallVectorImpl<SDValue> &OutVals,
130 const SmallVectorImpl<ISD::InputArg> &Ins,
131 DebugLoc dl, SelectionDAG &DAG,
132 SmallVectorImpl<SDValue> &InVals) const;
135 LowerReturn(SDValue Chain,
136 CallingConv::ID CallConv, bool isVarArg,
137 const SmallVectorImpl<ISD::OutputArg> &Outs,
138 const SmallVectorImpl<SDValue> &OutVals,
139 DebugLoc dl, SelectionDAG &DAG) const;
141 virtual MachineBasicBlock *
142 EmitInstrWithCustomInserter(MachineInstr *MI,
143 MachineBasicBlock *MBB) const;
145 // Inline asm support
146 ConstraintType getConstraintType(const std::string &Constraint) const;
148 /// Examine constraint string and operand type and determine a weight value.
149 /// The operand object must already have been set up with the operand type.
150 ConstraintWeight getSingleConstraintMatchWeight(
151 AsmOperandInfo &info, const char *constraint) const;
153 std::pair<unsigned, const TargetRegisterClass*>
154 getRegForInlineAsmConstraint(const std::string &Constraint,
157 std::vector<unsigned>
158 getRegClassForInlineAsmConstraint(const std::string &Constraint,
161 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
163 /// isFPImmLegal - Returns true if the target can instruction select the
164 /// specified FP immediate natively. If false, the legalizer will
165 /// materialize the FP immediate as a load from a constant pool.
166 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
170 #endif // MipsISELLOWERING_H