1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
18 #include "MCTargetDesc/MipsABIInfo.h"
19 #include "MCTargetDesc/MipsBaseInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Target/TargetLowering.h"
31 // Start the numbering from where ISD NodeType finishes.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 // Jump and link (call)
40 // Get the Higher 16 bits from a 32-bit immediate
41 // No relation with Mips Hi register
44 // Get the Lower 16 bits from a 32-bit immediate
45 // No relation with Mips Lo register
48 // Handle gp_rel (small data/bss sections) relocation.
54 // Floating Point Branch Conditional
57 // Floating Point Compare
60 // Floating Point Conditional Moves
64 // FP-to-int truncation node.
72 // Node used to extract integer from accumulator.
76 // Node used to insert integers to accumulator.
107 // EXTR.W instrinsic nodes.
117 // DPA.W intrinsic nodes.
153 // DSP setcc and select_cc nodes.
157 // Vector comparisons.
158 // These take a vector and return a boolean.
164 // These take a vector and return a vector bitmask.
171 // Element-wise vector max/min.
177 // Vector Shuffle with mask as an operand
178 VSHF, // Generic shuffle
179 SHF, // 4-element set shuffle.
180 ILVEV, // Interleave even elements
181 ILVOD, // Interleave odd elements
182 ILVL, // Interleave left elements
183 ILVR, // Interleave right elements
184 PCKEV, // Pack even elements
185 PCKOD, // Pack odd elements
188 INSVE, // Copy element from one vector to another
190 // Combined (XOR (OR $a, $b), -1)
193 // Extended vector element extraction
197 // Load/Store Left/Right nodes.
198 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
209 //===--------------------------------------------------------------------===//
210 // TargetLowering Implementation
211 //===--------------------------------------------------------------------===//
212 class MipsFunctionInfo;
216 class MipsTargetLowering : public TargetLowering {
219 explicit MipsTargetLowering(const MipsTargetMachine &TM,
220 const MipsSubtarget &STI);
222 static const MipsTargetLowering *create(const MipsTargetMachine &TM,
223 const MipsSubtarget &STI);
225 /// createFastISel - This method returns a target specific FastISel object,
226 /// or null if the target does not support "fast" ISel.
227 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
228 const TargetLibraryInfo *libInfo) const override;
230 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
232 void LowerOperationWrapper(SDNode *N,
233 SmallVectorImpl<SDValue> &Results,
234 SelectionDAG &DAG) const override;
236 /// LowerOperation - Provide custom lowering hooks for some operations.
237 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
239 /// ReplaceNodeResults - Replace the results of node with an illegal result
240 /// type with new values built out of custom code.
242 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
243 SelectionDAG &DAG) const override;
245 /// getTargetNodeName - This method returns the name of a target specific
247 const char *getTargetNodeName(unsigned Opcode) const override;
249 /// getSetCCResultType - get the ISD::SETCC result ValueType
250 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
252 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
255 EmitInstrWithCustomInserter(MachineInstr *MI,
256 MachineBasicBlock *MBB) const override;
259 bool operator()(const char *S1, const char *S2) const {
260 return strcmp(S1, S2) < 0;
264 void HandleByVal(CCState *, unsigned &, unsigned) const override;
266 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
269 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
271 // This method creates the following nodes, which are necessary for
272 // computing a local symbol's address:
274 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
275 template <class NodeTy>
276 SDValue getAddrLocal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG,
277 bool IsN32OrN64) const {
278 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
279 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
280 getTargetNode(N, Ty, DAG, GOTFlag));
281 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
282 MachinePointerInfo::getGOT(), false, false,
284 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
285 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
286 getTargetNode(N, Ty, DAG, LoFlag));
287 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
290 // This method creates the following nodes, which are necessary for
291 // computing a global symbol's address:
293 // (load (wrapper $gp, %got(sym)))
294 template <class NodeTy>
295 SDValue getAddrGlobal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG,
296 unsigned Flag, SDValue Chain,
297 const MachinePointerInfo &PtrInfo) const {
298 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
299 getTargetNode(N, Ty, DAG, Flag));
300 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
303 // This method creates the following nodes, which are necessary for
304 // computing a global symbol's address in large-GOT mode:
306 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
307 template <class NodeTy>
308 SDValue getAddrGlobalLargeGOT(NodeTy *N, SDLoc DL, EVT Ty,
309 SelectionDAG &DAG, unsigned HiFlag,
310 unsigned LoFlag, SDValue Chain,
311 const MachinePointerInfo &PtrInfo) const {
313 DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(N, Ty, DAG, HiFlag));
314 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
315 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
316 getTargetNode(N, Ty, DAG, LoFlag));
317 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
321 // This method creates the following nodes, which are necessary for
322 // computing a symbol's address in non-PIC mode:
324 // (add %hi(sym), %lo(sym))
325 template <class NodeTy>
326 SDValue getAddrNonPIC(NodeTy *N, SDLoc DL, EVT Ty,
327 SelectionDAG &DAG) const {
328 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
329 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
330 return DAG.getNode(ISD::ADD, DL, Ty,
331 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
332 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
335 // This method creates the following nodes, which are necessary for
336 // computing a symbol's address using gp-relative addressing:
338 // (add $gp, %gp_rel(sym))
339 template <class NodeTy>
340 SDValue getAddrGPRel(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) const {
341 assert(Ty == MVT::i32);
342 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
343 return DAG.getNode(ISD::ADD, DL, Ty,
344 DAG.getRegister(Mips::GP, Ty),
345 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty),
349 /// This function fills Ops, which is the list of operands that will later
350 /// be used when a function call node is created. It also generates
351 /// copyToReg nodes to set up argument registers.
353 getOpndList(SmallVectorImpl<SDValue> &Ops,
354 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
355 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
356 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
357 SDValue Chain) const;
360 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
361 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
364 const MipsSubtarget &Subtarget;
365 // Cache the ABI from the TargetMachine, we use it everywhere.
366 const MipsABIInfo &ABI;
369 // Create a TargetGlobalAddress node.
370 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
371 unsigned Flag) const;
373 // Create a TargetExternalSymbol node.
374 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
375 unsigned Flag) const;
377 // Create a TargetBlockAddress node.
378 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
379 unsigned Flag) const;
381 // Create a TargetJumpTable node.
382 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
383 unsigned Flag) const;
385 // Create a TargetConstantPool node.
386 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
387 unsigned Flag) const;
389 // Lower Operand helpers
390 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
391 CallingConv::ID CallConv, bool isVarArg,
392 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
393 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
394 TargetLowering::CallLoweringInfo &CLI) const;
396 // Lower Operand specifics
397 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
398 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
399 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
400 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
401 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
402 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
403 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
404 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
405 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
406 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
407 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
408 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
409 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
410 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
411 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
412 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
413 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
414 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
415 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
416 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
418 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
419 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
421 /// isEligibleForTailCallOptimization - Check whether the call is eligible
422 /// for tail call optimization.
424 isEligibleForTailCallOptimization(const CCState &CCInfo,
425 unsigned NextStackOffset,
426 const MipsFunctionInfo &FI) const = 0;
428 /// copyByValArg - Copy argument registers which were used to pass a byval
429 /// argument to the stack. Create a stack frame object for the byval
431 void copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
432 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
433 SmallVectorImpl<SDValue> &InVals,
434 const Argument *FuncArg, unsigned FirstReg,
435 unsigned LastReg, const CCValAssign &VA,
436 MipsCCState &State) const;
438 /// passByValArg - Pass a byval argument in registers or on stack.
439 void passByValArg(SDValue Chain, SDLoc DL,
440 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
441 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
442 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
443 unsigned FirstReg, unsigned LastReg,
444 const ISD::ArgFlagsTy &Flags, bool isLittle,
445 const CCValAssign &VA) const;
447 /// writeVarArgRegs - Write variable function arguments passed in registers
448 /// to the stack. Also create a stack frame object for the first variable
450 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
451 SDLoc DL, SelectionDAG &DAG, CCState &State) const;
454 LowerFormalArguments(SDValue Chain,
455 CallingConv::ID CallConv, bool isVarArg,
456 const SmallVectorImpl<ISD::InputArg> &Ins,
457 SDLoc dl, SelectionDAG &DAG,
458 SmallVectorImpl<SDValue> &InVals) const override;
460 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
461 SDValue Arg, SDLoc DL, bool IsTailCall,
462 SelectionDAG &DAG) const;
464 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
465 SmallVectorImpl<SDValue> &InVals) const override;
467 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
469 const SmallVectorImpl<ISD::OutputArg> &Outs,
470 LLVMContext &Context) const override;
472 SDValue LowerReturn(SDValue Chain,
473 CallingConv::ID CallConv, bool isVarArg,
474 const SmallVectorImpl<ISD::OutputArg> &Outs,
475 const SmallVectorImpl<SDValue> &OutVals,
476 SDLoc dl, SelectionDAG &DAG) const override;
478 // Inline asm support
480 getConstraintType(const std::string &Constraint) const override;
482 /// Examine constraint string and operand type and determine a weight value.
483 /// The operand object must already have been set up with the operand type.
484 ConstraintWeight getSingleConstraintMatchWeight(
485 AsmOperandInfo &info, const char *constraint) const override;
487 /// This function parses registers that appear in inline-asm constraints.
488 /// It returns pair (0, 0) on failure.
489 std::pair<unsigned, const TargetRegisterClass *>
490 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
492 std::pair<unsigned, const TargetRegisterClass*>
493 getRegForInlineAsmConstraint(const std::string &Constraint,
494 MVT VT) const override;
496 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
497 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
498 /// true it means one of the asm constraint of the inline asm instruction
499 /// being processed is 'm'.
500 void LowerAsmOperandForConstraint(SDValue Op,
501 std::string &Constraint,
502 std::vector<SDValue> &Ops,
503 SelectionDAG &DAG) const override;
505 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
507 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
509 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
511 bool IsMemset, bool ZeroMemset,
513 MachineFunction &MF) const override;
515 /// isFPImmLegal - Returns true if the target can instruction select the
516 /// specified FP immediate natively. If false, the legalizer will
517 /// materialize the FP immediate as a load from a constant pool.
518 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
520 unsigned getJumpTableEncoding() const override;
522 /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
523 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI,
524 MachineBasicBlock *BB,
525 unsigned Size, unsigned DstReg,
526 unsigned SrcRec) const;
528 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
529 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
530 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
531 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
532 bool Nand = false) const;
533 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
534 MachineBasicBlock *BB, unsigned Size) const;
535 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
536 MachineBasicBlock *BB, unsigned Size) const;
537 MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const;
538 MachineBasicBlock *emitPseudoSELECT(MachineInstr *MI,
539 MachineBasicBlock *BB, bool isFPCmp,
543 /// Create MipsTargetLowering objects.
544 const MipsTargetLowering *
545 createMips16TargetLowering(const MipsTargetMachine &TM,
546 const MipsSubtarget &STI);
547 const MipsTargetLowering *
548 createMipsSETargetLowering(const MipsTargetMachine &TM,
549 const MipsSubtarget &STI);
552 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
553 const TargetLibraryInfo *libInfo);