1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/Target/TargetLowering.h"
29 // Start the numbering from where ISD NodeType finishes.
30 FIRST_NUMBER = ISD::BUILTIN_OP_END,
32 // Jump and link (call)
38 // Get the Higher 16 bits from a 32-bit immediate
39 // No relation with Mips Hi register
42 // Get the Lower 16 bits from a 32-bit immediate
43 // No relation with Mips Lo register
46 // Handle gp_rel (small data/bss sections) relocation.
52 // Floating Point Branch Conditional
55 // Floating Point Compare
58 // Floating Point Conditional Moves
62 // Floating Point Rounding
92 // EXTR.W instrinsic nodes.
102 // DPA.W intrinsic nodes.
133 // Load/Store Left/Right nodes.
134 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
145 //===--------------------------------------------------------------------===//
146 // TargetLowering Implementation
147 //===--------------------------------------------------------------------===//
148 class MipsFunctionInfo;
150 class MipsTargetLowering : public TargetLowering {
152 explicit MipsTargetLowering(MipsTargetMachine &TM);
154 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
156 virtual bool allowsUnalignedMemoryAccesses (EVT VT, bool *Fast) const;
158 virtual void LowerOperationWrapper(SDNode *N,
159 SmallVectorImpl<SDValue> &Results,
160 SelectionDAG &DAG) const;
162 /// LowerOperation - Provide custom lowering hooks for some operations.
163 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
165 /// ReplaceNodeResults - Replace the results of node with an illegal result
166 /// type with new values built out of custom code.
168 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
169 SelectionDAG &DAG) const;
171 /// getTargetNodeName - This method returns the name of a target specific
173 virtual const char *getTargetNodeName(unsigned Opcode) const;
175 /// getSetCCResultType - get the ISD::SETCC result ValueType
176 EVT getSetCCResultType(EVT VT) const;
178 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
181 void SetMips16LibcallName(RTLIB::Libcall, const char *Name);
183 void setMips16HardFloatLibCalls();
186 getMips16HelperFunctionStubNumber(ArgListTy &Args) const;
188 const char *getMips16HelperFunction
189 (Type* RetTy, ArgListTy &Args, bool &needHelper) const;
191 /// ByValArgInfo - Byval argument information.
192 struct ByValArgInfo {
193 unsigned FirstIdx; // Index of the first register used.
194 unsigned NumRegs; // Number of registers used for this argument.
195 unsigned Address; // Offset of the stack area used to pass this argument.
197 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
200 /// MipsCC - This class provides methods used to analyze formal and call
201 /// arguments and inquire about calling convention information.
204 MipsCC(CallingConv::ID CallConv, bool IsO32, CCState &Info);
206 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
208 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins);
209 const CCState &getCCInfo() const { return CCInfo; }
211 /// hasByValArg - Returns true if function has byval arguments.
212 bool hasByValArg() const { return !ByValArgs.empty(); }
214 /// regSize - Size (in number of bits) of integer registers.
215 unsigned regSize() const { return IsO32 ? 4 : 8; }
217 /// numIntArgRegs - Number of integer registers available for calls.
218 unsigned numIntArgRegs() const;
220 /// reservedArgArea - The size of the area the caller reserves for
221 /// register arguments. This is 16-byte if ABI is O32.
222 unsigned reservedArgArea() const;
224 /// Return pointer to array of integer argument registers.
225 const uint16_t *intArgRegs() const;
227 typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator;
228 byval_iterator byval_begin() const { return ByValArgs.begin(); }
229 byval_iterator byval_end() const { return ByValArgs.end(); }
232 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
233 CCValAssign::LocInfo LocInfo,
234 ISD::ArgFlagsTy ArgFlags);
236 /// useRegsForByval - Returns true if the calling convention allows the
237 /// use of registers to pass byval arguments.
238 bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
240 /// Return the function that analyzes fixed argument list functions.
241 llvm::CCAssignFn *fixedArgFn() const;
243 /// Return the function that analyzes variable argument list functions.
244 llvm::CCAssignFn *varArgFn() const;
246 const uint16_t *shadowRegs() const;
248 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
252 CallingConv::ID CallConv;
254 SmallVector<ByValArgInfo, 2> ByValArgs;
258 const MipsSubtarget *Subtarget;
260 bool HasMips64, IsN64, IsO32;
262 // Lower Operand helpers
263 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
264 CallingConv::ID CallConv, bool isVarArg,
265 const SmallVectorImpl<ISD::InputArg> &Ins,
266 DebugLoc dl, SelectionDAG &DAG,
267 SmallVectorImpl<SDValue> &InVals) const;
269 // Lower Operand specifics
270 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
271 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
272 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
273 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
274 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
275 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
276 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
277 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
278 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
279 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
280 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
281 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
282 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
283 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
284 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
285 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
286 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
287 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
288 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
290 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
291 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
292 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
293 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
294 SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
296 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
297 /// for tail call optimization.
298 bool IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
299 unsigned NextStackOffset,
300 const MipsFunctionInfo& FI) const;
302 /// copyByValArg - Copy argument registers which were used to pass a byval
303 /// argument to the stack. Create a stack frame object for the byval
305 void copyByValRegs(SDValue Chain, DebugLoc DL,
306 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
307 const ISD::ArgFlagsTy &Flags,
308 SmallVectorImpl<SDValue> &InVals,
309 const Argument *FuncArg,
310 const MipsCC &CC, const ByValArgInfo &ByVal) const;
312 /// passByValArg - Pass a byval argument in registers or on stack.
313 void passByValArg(SDValue Chain, DebugLoc DL,
314 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
315 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
316 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
317 const MipsCC &CC, const ByValArgInfo &ByVal,
318 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
320 /// writeVarArgRegs - Write variable function arguments passed in registers
321 /// to the stack. Also create a stack frame object for the first variable
323 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
324 SDValue Chain, DebugLoc DL, SelectionDAG &DAG) const;
327 LowerFormalArguments(SDValue Chain,
328 CallingConv::ID CallConv, bool isVarArg,
329 const SmallVectorImpl<ISD::InputArg> &Ins,
330 DebugLoc dl, SelectionDAG &DAG,
331 SmallVectorImpl<SDValue> &InVals) const;
333 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
334 SDValue Arg, DebugLoc DL, bool IsTailCall,
335 SelectionDAG &DAG) const;
338 LowerCall(TargetLowering::CallLoweringInfo &CLI,
339 SmallVectorImpl<SDValue> &InVals) const;
342 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
344 const SmallVectorImpl<ISD::OutputArg> &Outs,
345 LLVMContext &Context) const;
348 LowerReturn(SDValue Chain,
349 CallingConv::ID CallConv, bool isVarArg,
350 const SmallVectorImpl<ISD::OutputArg> &Outs,
351 const SmallVectorImpl<SDValue> &OutVals,
352 DebugLoc dl, SelectionDAG &DAG) const;
354 virtual MachineBasicBlock *
355 EmitInstrWithCustomInserter(MachineInstr *MI,
356 MachineBasicBlock *MBB) const;
358 // Inline asm support
359 ConstraintType getConstraintType(const std::string &Constraint) const;
361 /// Examine constraint string and operand type and determine a weight value.
362 /// The operand object must already have been set up with the operand type.
363 ConstraintWeight getSingleConstraintMatchWeight(
364 AsmOperandInfo &info, const char *constraint) const;
366 std::pair<unsigned, const TargetRegisterClass*>
367 getRegForInlineAsmConstraint(const std::string &Constraint,
370 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
371 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
372 /// true it means one of the asm constraint of the inline asm instruction
373 /// being processed is 'm'.
374 virtual void LowerAsmOperandForConstraint(SDValue Op,
375 std::string &Constraint,
376 std::vector<SDValue> &Ops,
377 SelectionDAG &DAG) const;
379 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
381 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
383 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
385 bool IsMemset, bool ZeroMemset,
387 MachineFunction &MF) const;
389 /// isFPImmLegal - Returns true if the target can instruction select the
390 /// specified FP immediate natively. If false, the legalizer will
391 /// materialize the FP immediate as a load from a constant pool.
392 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
394 virtual unsigned getJumpTableEncoding() const;
396 MachineBasicBlock *EmitBPOSGE32(MachineInstr *MI,
397 MachineBasicBlock *BB) const;
398 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
399 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
400 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
401 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
402 bool Nand = false) const;
403 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
404 MachineBasicBlock *BB, unsigned Size) const;
405 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
406 MachineBasicBlock *BB, unsigned Size) const;
407 MachineBasicBlock *EmitSel16(unsigned Opc, MachineInstr *MI,
408 MachineBasicBlock *BB) const;
409 MachineBasicBlock *EmitSeliT16(unsigned Opc1, unsigned Opc2,
411 MachineBasicBlock *BB) const;
413 MachineBasicBlock *EmitSelT16(unsigned Opc1, unsigned Opc2,
415 MachineBasicBlock *BB) const;
416 MachineBasicBlock *EmitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
418 MachineBasicBlock *BB) const;
419 MachineBasicBlock *EmitFEXT_T8I8I16_ins(
420 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc,
421 MachineInstr *MI, MachineBasicBlock *BB) const;
422 MachineBasicBlock *EmitFEXT_CCRX16_ins(
424 MachineInstr *MI, MachineBasicBlock *BB) const;
425 MachineBasicBlock *EmitFEXT_CCRXI16_ins(
426 unsigned SltiOpc, unsigned SltiXOpc,
427 MachineInstr *MI, MachineBasicBlock *BB )const;
432 #endif // MipsISELLOWERING_H