1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
18 #include "MCTargetDesc/MipsABIInfo.h"
19 #include "MCTargetDesc/MipsBaseInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Target/TargetLowering.h"
30 enum NodeType : unsigned {
31 // Start the numbering from where ISD NodeType finishes.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 // Jump and link (call)
40 // Get the Higher 16 bits from a 32-bit immediate
41 // No relation with Mips Hi register
44 // Get the Lower 16 bits from a 32-bit immediate
45 // No relation with Mips Lo register
48 // Handle gp_rel (small data/bss sections) relocation.
54 // Floating Point Branch Conditional
57 // Floating Point Compare
60 // Floating Point Conditional Moves
64 // FP-to-int truncation node.
72 // Node used to extract integer from accumulator.
76 // Node used to insert integers to accumulator.
107 // EXTR.W instrinsic nodes.
117 // DPA.W intrinsic nodes.
153 // DSP setcc and select_cc nodes.
157 // Vector comparisons.
158 // These take a vector and return a boolean.
164 // These take a vector and return a vector bitmask.
171 // Element-wise vector max/min.
177 // Vector Shuffle with mask as an operand
178 VSHF, // Generic shuffle
179 SHF, // 4-element set shuffle.
180 ILVEV, // Interleave even elements
181 ILVOD, // Interleave odd elements
182 ILVL, // Interleave left elements
183 ILVR, // Interleave right elements
184 PCKEV, // Pack even elements
185 PCKOD, // Pack odd elements
188 INSVE, // Copy element from one vector to another
190 // Combined (XOR (OR $a, $b), -1)
193 // Extended vector element extraction
197 // Load/Store Left/Right nodes.
198 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
209 //===--------------------------------------------------------------------===//
210 // TargetLowering Implementation
211 //===--------------------------------------------------------------------===//
212 class MipsFunctionInfo;
216 class MipsTargetLowering : public TargetLowering {
219 explicit MipsTargetLowering(const MipsTargetMachine &TM,
220 const MipsSubtarget &STI);
222 static const MipsTargetLowering *create(const MipsTargetMachine &TM,
223 const MipsSubtarget &STI);
225 /// createFastISel - This method returns a target specific FastISel object,
226 /// or null if the target does not support "fast" ISel.
227 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
228 const TargetLibraryInfo *libInfo) const override;
230 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
234 void LowerOperationWrapper(SDNode *N,
235 SmallVectorImpl<SDValue> &Results,
236 SelectionDAG &DAG) const override;
238 /// LowerOperation - Provide custom lowering hooks for some operations.
239 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
241 /// ReplaceNodeResults - Replace the results of node with an illegal result
242 /// type with new values built out of custom code.
244 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
245 SelectionDAG &DAG) const override;
247 /// getTargetNodeName - This method returns the name of a target specific
249 const char *getTargetNodeName(unsigned Opcode) const override;
251 /// getSetCCResultType - get the ISD::SETCC result ValueType
252 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
253 EVT VT) const override;
255 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
258 EmitInstrWithCustomInserter(MachineInstr *MI,
259 MachineBasicBlock *MBB) const override;
261 void HandleByVal(CCState *, unsigned &, unsigned) const override;
263 unsigned getRegisterByName(const char* RegName, EVT VT,
264 SelectionDAG &DAG) const override;
266 /// Returns true if a cast between SrcAS and DestAS is a noop.
267 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
268 // Mips doesn't have any special address spaces so we just reserve
269 // the first 256 for software use (e.g. OpenCL) and treat casts
270 // between them as noops.
271 return SrcAS < 256 && DestAS < 256;
275 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
277 // This method creates the following nodes, which are necessary for
278 // computing a local symbol's address:
280 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
281 template <class NodeTy>
282 SDValue getAddrLocal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG,
283 bool IsN32OrN64) const {
284 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
285 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
286 getTargetNode(N, Ty, DAG, GOTFlag));
288 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
289 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
290 false, false, false, 0);
291 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
292 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
293 getTargetNode(N, Ty, DAG, LoFlag));
294 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
297 // This method creates the following nodes, which are necessary for
298 // computing a global symbol's address:
300 // (load (wrapper $gp, %got(sym)))
301 template <class NodeTy>
302 SDValue getAddrGlobal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG,
303 unsigned Flag, SDValue Chain,
304 const MachinePointerInfo &PtrInfo) const {
305 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
306 getTargetNode(N, Ty, DAG, Flag));
307 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
310 // This method creates the following nodes, which are necessary for
311 // computing a global symbol's address in large-GOT mode:
313 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
314 template <class NodeTy>
315 SDValue getAddrGlobalLargeGOT(NodeTy *N, SDLoc DL, EVT Ty,
316 SelectionDAG &DAG, unsigned HiFlag,
317 unsigned LoFlag, SDValue Chain,
318 const MachinePointerInfo &PtrInfo) const {
320 DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(N, Ty, DAG, HiFlag));
321 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
322 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
323 getTargetNode(N, Ty, DAG, LoFlag));
324 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
328 // This method creates the following nodes, which are necessary for
329 // computing a symbol's address in non-PIC mode:
331 // (add %hi(sym), %lo(sym))
332 template <class NodeTy>
333 SDValue getAddrNonPIC(NodeTy *N, SDLoc DL, EVT Ty,
334 SelectionDAG &DAG) const {
335 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
336 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
337 return DAG.getNode(ISD::ADD, DL, Ty,
338 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
339 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
342 // This method creates the following nodes, which are necessary for
343 // computing a symbol's address using gp-relative addressing:
345 // (add $gp, %gp_rel(sym))
346 template <class NodeTy>
347 SDValue getAddrGPRel(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) const {
348 assert(Ty == MVT::i32);
349 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
350 return DAG.getNode(ISD::ADD, DL, Ty,
351 DAG.getRegister(Mips::GP, Ty),
352 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty),
356 /// This function fills Ops, which is the list of operands that will later
357 /// be used when a function call node is created. It also generates
358 /// copyToReg nodes to set up argument registers.
360 getOpndList(SmallVectorImpl<SDValue> &Ops,
361 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
362 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
363 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
364 SDValue Chain) const;
367 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
368 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
371 const MipsSubtarget &Subtarget;
372 // Cache the ABI from the TargetMachine, we use it everywhere.
373 const MipsABIInfo &ABI;
376 // Create a TargetGlobalAddress node.
377 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
378 unsigned Flag) const;
380 // Create a TargetExternalSymbol node.
381 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
382 unsigned Flag) const;
384 // Create a TargetBlockAddress node.
385 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
386 unsigned Flag) const;
388 // Create a TargetJumpTable node.
389 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
390 unsigned Flag) const;
392 // Create a TargetConstantPool node.
393 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
394 unsigned Flag) const;
396 // Lower Operand helpers
397 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
398 CallingConv::ID CallConv, bool isVarArg,
399 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
400 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
401 TargetLowering::CallLoweringInfo &CLI) const;
403 // Lower Operand specifics
404 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
405 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
406 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
407 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
408 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
409 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
410 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
411 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
412 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
413 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
414 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
415 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
416 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
417 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
418 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
419 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
420 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
421 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
422 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
423 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
425 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
426 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
428 /// isEligibleForTailCallOptimization - Check whether the call is eligible
429 /// for tail call optimization.
431 isEligibleForTailCallOptimization(const CCState &CCInfo,
432 unsigned NextStackOffset,
433 const MipsFunctionInfo &FI) const = 0;
435 /// copyByValArg - Copy argument registers which were used to pass a byval
436 /// argument to the stack. Create a stack frame object for the byval
438 void copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
439 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
440 SmallVectorImpl<SDValue> &InVals,
441 const Argument *FuncArg, unsigned FirstReg,
442 unsigned LastReg, const CCValAssign &VA,
443 MipsCCState &State) const;
445 /// passByValArg - Pass a byval argument in registers or on stack.
446 void passByValArg(SDValue Chain, SDLoc DL,
447 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
448 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
449 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
450 unsigned FirstReg, unsigned LastReg,
451 const ISD::ArgFlagsTy &Flags, bool isLittle,
452 const CCValAssign &VA) const;
454 /// writeVarArgRegs - Write variable function arguments passed in registers
455 /// to the stack. Also create a stack frame object for the first variable
457 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
458 SDLoc DL, SelectionDAG &DAG, CCState &State) const;
461 LowerFormalArguments(SDValue Chain,
462 CallingConv::ID CallConv, bool isVarArg,
463 const SmallVectorImpl<ISD::InputArg> &Ins,
464 SDLoc dl, SelectionDAG &DAG,
465 SmallVectorImpl<SDValue> &InVals) const override;
467 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
468 SDValue Arg, SDLoc DL, bool IsTailCall,
469 SelectionDAG &DAG) const;
471 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
472 SmallVectorImpl<SDValue> &InVals) const override;
474 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
476 const SmallVectorImpl<ISD::OutputArg> &Outs,
477 LLVMContext &Context) const override;
479 SDValue LowerReturn(SDValue Chain,
480 CallingConv::ID CallConv, bool isVarArg,
481 const SmallVectorImpl<ISD::OutputArg> &Outs,
482 const SmallVectorImpl<SDValue> &OutVals,
483 SDLoc dl, SelectionDAG &DAG) const override;
485 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
487 // Inline asm support
488 ConstraintType getConstraintType(StringRef Constraint) const override;
490 /// Examine constraint string and operand type and determine a weight value.
491 /// The operand object must already have been set up with the operand type.
492 ConstraintWeight getSingleConstraintMatchWeight(
493 AsmOperandInfo &info, const char *constraint) const override;
495 /// This function parses registers that appear in inline-asm constraints.
496 /// It returns pair (0, 0) on failure.
497 std::pair<unsigned, const TargetRegisterClass *>
498 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
500 std::pair<unsigned, const TargetRegisterClass *>
501 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
502 StringRef Constraint, MVT VT) const override;
504 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
505 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
506 /// true it means one of the asm constraint of the inline asm instruction
507 /// being processed is 'm'.
508 void LowerAsmOperandForConstraint(SDValue Op,
509 std::string &Constraint,
510 std::vector<SDValue> &Ops,
511 SelectionDAG &DAG) const override;
514 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
515 if (ConstraintCode == "R")
516 return InlineAsm::Constraint_R;
517 else if (ConstraintCode == "ZC")
518 return InlineAsm::Constraint_ZC;
519 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
522 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
523 Type *Ty, unsigned AS) const override;
525 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
527 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
529 bool IsMemset, bool ZeroMemset,
531 MachineFunction &MF) const override;
533 /// isFPImmLegal - Returns true if the target can instruction select the
534 /// specified FP immediate natively. If false, the legalizer will
535 /// materialize the FP immediate as a load from a constant pool.
536 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
538 unsigned getJumpTableEncoding() const override;
539 bool useSoftFloat() const override;
541 /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
542 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI,
543 MachineBasicBlock *BB,
544 unsigned Size, unsigned DstReg,
545 unsigned SrcRec) const;
547 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
548 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
549 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
550 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
551 bool Nand = false) const;
552 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
553 MachineBasicBlock *BB, unsigned Size) const;
554 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
555 MachineBasicBlock *BB, unsigned Size) const;
556 MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const;
557 MachineBasicBlock *emitPseudoSELECT(MachineInstr *MI,
558 MachineBasicBlock *BB, bool isFPCmp,
562 /// Create MipsTargetLowering objects.
563 const MipsTargetLowering *
564 createMips16TargetLowering(const MipsTargetMachine &TM,
565 const MipsSubtarget &STI);
566 const MipsTargetLowering *
567 createMipsSETargetLowering(const MipsTargetMachine &TM,
568 const MipsSubtarget &STI);
571 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
572 const TargetLibraryInfo *libInfo);