1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
18 #include "MCTargetDesc/MipsBaseInfo.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/Target/TargetLowering.h"
30 // Start the numbering from where ISD NodeType finishes.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Jump and link (call)
39 // Get the Higher 16 bits from a 32-bit immediate
40 // No relation with Mips Hi register
43 // Get the Lower 16 bits from a 32-bit immediate
44 // No relation with Mips Lo register
47 // Handle gp_rel (small data/bss sections) relocation.
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // FP-to-int truncation node.
71 // Node used to extract integer from accumulator.
75 // Node used to insert integers to accumulator.
106 // EXTR.W instrinsic nodes.
116 // DPA.W intrinsic nodes.
152 // DSP setcc and select_cc nodes.
156 // Vector comparisons.
157 // These take a vector and return a boolean.
163 // These take a vector and return a vector bitmask.
170 // Element-wise vector max/min.
176 // Vector Shuffle with mask as an operand
177 VSHF, // Generic shuffle
178 SHF, // 4-element set shuffle.
179 ILVEV, // Interleave even elements
180 ILVOD, // Interleave odd elements
181 ILVL, // Interleave left elements
182 ILVR, // Interleave right elements
183 PCKEV, // Pack even elements
184 PCKOD, // Pack odd elements
187 INSVE, // Copy element from one vector to another
189 // Combined (XOR (OR $a, $b), -1)
192 // Extended vector element extraction
196 // Load/Store Left/Right nodes.
197 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
208 //===--------------------------------------------------------------------===//
209 // TargetLowering Implementation
210 //===--------------------------------------------------------------------===//
211 class MipsFunctionInfo;
215 class MipsTargetLowering : public TargetLowering {
218 explicit MipsTargetLowering(const MipsTargetMachine &TM,
219 const MipsSubtarget &STI);
221 static const MipsTargetLowering *create(const MipsTargetMachine &TM,
222 const MipsSubtarget &STI);
224 /// createFastISel - This method returns a target specific FastISel object,
225 /// or null if the target does not support "fast" ISel.
226 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
227 const TargetLibraryInfo *libInfo) const override;
229 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
231 void LowerOperationWrapper(SDNode *N,
232 SmallVectorImpl<SDValue> &Results,
233 SelectionDAG &DAG) const override;
235 /// LowerOperation - Provide custom lowering hooks for some operations.
236 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
238 /// ReplaceNodeResults - Replace the results of node with an illegal result
239 /// type with new values built out of custom code.
241 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
242 SelectionDAG &DAG) const override;
244 /// getTargetNodeName - This method returns the name of a target specific
246 const char *getTargetNodeName(unsigned Opcode) const override;
248 /// getSetCCResultType - get the ISD::SETCC result ValueType
249 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
251 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
254 EmitInstrWithCustomInserter(MachineInstr *MI,
255 MachineBasicBlock *MBB) const override;
258 bool operator()(const char *S1, const char *S2) const {
259 return strcmp(S1, S2) < 0;
263 void HandleByVal(CCState *, unsigned &, unsigned) const override;
265 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
268 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
270 // This method creates the following nodes, which are necessary for
271 // computing a local symbol's address:
273 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
274 template <class NodeTy>
275 SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
276 bool IsN32OrN64) const {
278 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
279 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
280 getTargetNode(N, Ty, DAG, GOTFlag));
281 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
282 MachinePointerInfo::getGOT(), false, false,
284 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
285 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
286 getTargetNode(N, Ty, DAG, LoFlag));
287 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
290 // This method creates the following nodes, which are necessary for
291 // computing a global symbol's address:
293 // (load (wrapper $gp, %got(sym)))
294 template<class NodeTy>
295 SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
296 unsigned Flag, SDValue Chain,
297 const MachinePointerInfo &PtrInfo) const {
299 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
300 getTargetNode(N, Ty, DAG, Flag));
301 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
304 // This method creates the following nodes, which are necessary for
305 // computing a global symbol's address in large-GOT mode:
307 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
308 template<class NodeTy>
309 SDValue getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG,
310 unsigned HiFlag, unsigned LoFlag,
312 const MachinePointerInfo &PtrInfo) const {
314 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty,
315 getTargetNode(N, Ty, DAG, HiFlag));
316 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
317 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
318 getTargetNode(N, Ty, DAG, LoFlag));
319 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
323 // This method creates the following nodes, which are necessary for
324 // computing a symbol's address in non-PIC mode:
326 // (add %hi(sym), %lo(sym))
327 template<class NodeTy>
328 SDValue getAddrNonPIC(NodeTy *N, EVT Ty, SelectionDAG &DAG) const {
330 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
331 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
332 return DAG.getNode(ISD::ADD, DL, Ty,
333 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
334 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
337 // This method creates the following nodes, which are necessary for
338 // computing a symbol's address using gp-relative addressing:
340 // (add $gp, %gp_rel(sym))
341 template<class NodeTy>
342 SDValue getAddrGPRel(NodeTy *N, EVT Ty, SelectionDAG &DAG) const {
344 assert(Ty == MVT::i32);
345 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
346 return DAG.getNode(ISD::ADD, DL, Ty,
347 DAG.getRegister(Mips::GP, Ty),
348 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty),
352 /// This function fills Ops, which is the list of operands that will later
353 /// be used when a function call node is created. It also generates
354 /// copyToReg nodes to set up argument registers.
356 getOpndList(SmallVectorImpl<SDValue> &Ops,
357 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
358 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
359 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
360 SDValue Chain) const;
363 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
364 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
367 const MipsSubtarget &Subtarget;
370 // Create a TargetGlobalAddress node.
371 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
372 unsigned Flag) const;
374 // Create a TargetExternalSymbol node.
375 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
376 unsigned Flag) const;
378 // Create a TargetBlockAddress node.
379 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
380 unsigned Flag) const;
382 // Create a TargetJumpTable node.
383 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
384 unsigned Flag) const;
386 // Create a TargetConstantPool node.
387 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
388 unsigned Flag) const;
390 // Lower Operand helpers
391 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
392 CallingConv::ID CallConv, bool isVarArg,
393 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
394 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
395 TargetLowering::CallLoweringInfo &CLI) const;
397 // Lower Operand specifics
398 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
399 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
400 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
401 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
402 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
403 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
404 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
405 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
406 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
407 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
408 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
409 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
410 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
411 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
412 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
413 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
414 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
415 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
416 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
417 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
419 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
420 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
422 /// isEligibleForTailCallOptimization - Check whether the call is eligible
423 /// for tail call optimization.
425 isEligibleForTailCallOptimization(const CCState &CCInfo,
426 unsigned NextStackOffset,
427 const MipsFunctionInfo &FI) const = 0;
429 /// copyByValArg - Copy argument registers which were used to pass a byval
430 /// argument to the stack. Create a stack frame object for the byval
432 void copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
433 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
434 SmallVectorImpl<SDValue> &InVals,
435 const Argument *FuncArg, unsigned FirstReg,
436 unsigned LastReg, const CCValAssign &VA,
437 MipsCCState &State) const;
439 /// passByValArg - Pass a byval argument in registers or on stack.
440 void passByValArg(SDValue Chain, SDLoc DL,
441 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
442 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
443 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
444 unsigned FirstReg, unsigned LastReg,
445 const ISD::ArgFlagsTy &Flags, bool isLittle,
446 const CCValAssign &VA) const;
448 /// writeVarArgRegs - Write variable function arguments passed in registers
449 /// to the stack. Also create a stack frame object for the first variable
451 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
452 SDLoc DL, SelectionDAG &DAG, CCState &State) const;
455 LowerFormalArguments(SDValue Chain,
456 CallingConv::ID CallConv, bool isVarArg,
457 const SmallVectorImpl<ISD::InputArg> &Ins,
458 SDLoc dl, SelectionDAG &DAG,
459 SmallVectorImpl<SDValue> &InVals) const override;
461 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
462 SDValue Arg, SDLoc DL, bool IsTailCall,
463 SelectionDAG &DAG) const;
465 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
466 SmallVectorImpl<SDValue> &InVals) const override;
468 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
470 const SmallVectorImpl<ISD::OutputArg> &Outs,
471 LLVMContext &Context) const override;
473 SDValue LowerReturn(SDValue Chain,
474 CallingConv::ID CallConv, bool isVarArg,
475 const SmallVectorImpl<ISD::OutputArg> &Outs,
476 const SmallVectorImpl<SDValue> &OutVals,
477 SDLoc dl, SelectionDAG &DAG) const override;
479 // Inline asm support
481 getConstraintType(const std::string &Constraint) const override;
483 /// Examine constraint string and operand type and determine a weight value.
484 /// The operand object must already have been set up with the operand type.
485 ConstraintWeight getSingleConstraintMatchWeight(
486 AsmOperandInfo &info, const char *constraint) const override;
488 /// This function parses registers that appear in inline-asm constraints.
489 /// It returns pair (0, 0) on failure.
490 std::pair<unsigned, const TargetRegisterClass *>
491 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
493 std::pair<unsigned, const TargetRegisterClass*>
494 getRegForInlineAsmConstraint(const std::string &Constraint,
495 MVT VT) const override;
497 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
498 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
499 /// true it means one of the asm constraint of the inline asm instruction
500 /// being processed is 'm'.
501 void LowerAsmOperandForConstraint(SDValue Op,
502 std::string &Constraint,
503 std::vector<SDValue> &Ops,
504 SelectionDAG &DAG) const override;
506 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
508 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
510 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
512 bool IsMemset, bool ZeroMemset,
514 MachineFunction &MF) const override;
516 /// isFPImmLegal - Returns true if the target can instruction select the
517 /// specified FP immediate natively. If false, the legalizer will
518 /// materialize the FP immediate as a load from a constant pool.
519 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
521 unsigned getJumpTableEncoding() const override;
523 /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
524 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI,
525 MachineBasicBlock *BB,
526 unsigned Size, unsigned DstReg,
527 unsigned SrcRec) const;
529 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
530 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
531 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
532 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
533 bool Nand = false) const;
534 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
535 MachineBasicBlock *BB, unsigned Size) const;
536 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
537 MachineBasicBlock *BB, unsigned Size) const;
538 MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const;
539 MachineBasicBlock *emitPseudoSELECT(MachineInstr *MI,
540 MachineBasicBlock *BB, bool isFPCmp,
544 /// Create MipsTargetLowering objects.
545 const MipsTargetLowering *
546 createMips16TargetLowering(const MipsTargetMachine &TM,
547 const MipsSubtarget &STI);
548 const MipsTargetLowering *
549 createMipsSETargetLowering(const MipsTargetMachine &TM,
550 const MipsSubtarget &STI);
553 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
554 const TargetLibraryInfo *libInfo);