1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetLowering.h"
21 #include "MipsSubtarget.h"
26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 // Jump and link (call)
32 // Get the Higher 16 bits from a 32-bit immediate
33 // No relation with Mips Hi register
36 // Get the Lower 16 bits from a 32-bit immediate
37 // No relation with Mips Lo register
40 // Handle gp_rel (small data/bss sections) relocation.
46 // Floating Point Branch Conditional
49 // Floating Point Compare
52 // Floating Point Conditional Moves
56 // Floating Point Rounding
86 //===--------------------------------------------------------------------===//
87 // TargetLowering Implementation
88 //===--------------------------------------------------------------------===//
90 class MipsTargetLowering : public TargetLowering {
92 explicit MipsTargetLowering(MipsTargetMachine &TM);
94 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
96 virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
98 /// LowerOperation - Provide custom lowering hooks for some operations.
99 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
101 /// getTargetNodeName - This method returns the name of a target specific
103 virtual const char *getTargetNodeName(unsigned Opcode) const;
105 /// getSetCCResultType - get the ISD::SETCC result ValueType
106 EVT getSetCCResultType(EVT VT) const;
108 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
111 const MipsSubtarget *Subtarget;
113 bool HasMips64, IsN64, IsO32;
115 // Lower Operand helpers
116 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
117 CallingConv::ID CallConv, bool isVarArg,
118 const SmallVectorImpl<ISD::InputArg> &Ins,
119 DebugLoc dl, SelectionDAG &DAG,
120 SmallVectorImpl<SDValue> &InVals) const;
122 // Lower Operand specifics
123 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
125 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
126 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
127 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
128 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
129 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
130 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
131 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
133 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
134 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
135 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
138 LowerFormalArguments(SDValue Chain,
139 CallingConv::ID CallConv, bool isVarArg,
140 const SmallVectorImpl<ISD::InputArg> &Ins,
141 DebugLoc dl, SelectionDAG &DAG,
142 SmallVectorImpl<SDValue> &InVals) const;
145 LowerCall(SDValue Chain, SDValue Callee,
146 CallingConv::ID CallConv, bool isVarArg,
148 const SmallVectorImpl<ISD::OutputArg> &Outs,
149 const SmallVectorImpl<SDValue> &OutVals,
150 const SmallVectorImpl<ISD::InputArg> &Ins,
151 DebugLoc dl, SelectionDAG &DAG,
152 SmallVectorImpl<SDValue> &InVals) const;
155 LowerReturn(SDValue Chain,
156 CallingConv::ID CallConv, bool isVarArg,
157 const SmallVectorImpl<ISD::OutputArg> &Outs,
158 const SmallVectorImpl<SDValue> &OutVals,
159 DebugLoc dl, SelectionDAG &DAG) const;
161 virtual MachineBasicBlock *
162 EmitInstrWithCustomInserter(MachineInstr *MI,
163 MachineBasicBlock *MBB) const;
165 // Inline asm support
166 ConstraintType getConstraintType(const std::string &Constraint) const;
168 /// Examine constraint string and operand type and determine a weight value.
169 /// The operand object must already have been set up with the operand type.
170 ConstraintWeight getSingleConstraintMatchWeight(
171 AsmOperandInfo &info, const char *constraint) const;
173 std::pair<unsigned, const TargetRegisterClass*>
174 getRegForInlineAsmConstraint(const std::string &Constraint,
177 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
179 /// isFPImmLegal - Returns true if the target can instruction select the
180 /// specified FP immediate natively. If false, the legalizer will
181 /// materialize the FP immediate as a load from a constant pool.
182 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
184 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
185 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
186 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
187 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
188 bool Nand = false) const;
189 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
190 MachineBasicBlock *BB, unsigned Size) const;
191 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
192 MachineBasicBlock *BB, unsigned Size) const;
196 #endif // MipsISELLOWERING_H