1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "MCTargetDesc/MipsBaseInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Target/TargetLowering.h"
31 // Start the numbering from where ISD NodeType finishes.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 // Jump and link (call)
40 // Get the Higher 16 bits from a 32-bit immediate
41 // No relation with Mips Hi register
44 // Get the Lower 16 bits from a 32-bit immediate
45 // No relation with Mips Lo register
48 // Handle gp_rel (small data/bss sections) relocation.
54 // Floating Point Branch Conditional
57 // Floating Point Compare
60 // Floating Point Conditional Moves
64 // FP-to-int truncation node.
72 // Node used to extract integer from accumulator.
75 // Node used to insert integers to accumulator.
106 // EXTR.W instrinsic nodes.
116 // DPA.W intrinsic nodes.
152 // DSP setcc and select_cc nodes.
156 // Vector comparisons.
157 // These take a vector and return a boolean.
163 // These take a vector and return a vector bitmask.
170 // Element-wise vector max/min.
176 // Vector Shuffle with mask as an operand
177 VSHF, // Generic shuffle
178 SHF, // 4-element set shuffle.
179 ILVEV, // Interleave even elements
180 ILVOD, // Interleave odd elements
181 ILVL, // Interleave left elements
182 ILVR, // Interleave right elements
183 PCKEV, // Pack even elements
184 PCKOD, // Pack odd elements
186 // Combined (XOR (OR $a, $b), -1)
189 // Extended vector element extraction
193 // Load/Store Left/Right nodes.
194 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
205 //===--------------------------------------------------------------------===//
206 // TargetLowering Implementation
207 //===--------------------------------------------------------------------===//
208 class MipsFunctionInfo;
210 class MipsTargetLowering : public TargetLowering {
212 explicit MipsTargetLowering(MipsTargetMachine &TM);
214 static const MipsTargetLowering *create(MipsTargetMachine &TM);
216 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
218 virtual void LowerOperationWrapper(SDNode *N,
219 SmallVectorImpl<SDValue> &Results,
220 SelectionDAG &DAG) const;
222 /// LowerOperation - Provide custom lowering hooks for some operations.
223 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
225 /// ReplaceNodeResults - Replace the results of node with an illegal result
226 /// type with new values built out of custom code.
228 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
229 SelectionDAG &DAG) const;
231 /// getTargetNodeName - This method returns the name of a target specific
233 virtual const char *getTargetNodeName(unsigned Opcode) const;
235 /// getSetCCResultType - get the ISD::SETCC result ValueType
236 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
238 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
240 virtual MachineBasicBlock *
241 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
244 bool operator()(const char *S1, const char *S2) const {
245 return strcmp(S1, S2) < 0;
250 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
252 // This method creates the following nodes, which are necessary for
253 // computing a local symbol's address:
255 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
256 template<class NodeTy>
257 SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
258 bool HasMips64) const {
260 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
261 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
262 getTargetNode(N, Ty, DAG, GOTFlag));
263 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
264 MachinePointerInfo::getGOT(), false, false,
266 unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
267 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
268 getTargetNode(N, Ty, DAG, LoFlag));
269 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
272 // This method creates the following nodes, which are necessary for
273 // computing a global symbol's address:
275 // (load (wrapper $gp, %got(sym)))
276 template<class NodeTy>
277 SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
278 unsigned Flag, SDValue Chain,
279 const MachinePointerInfo &PtrInfo) const {
281 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
282 getTargetNode(N, Ty, DAG, Flag));
283 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
286 // This method creates the following nodes, which are necessary for
287 // computing a global symbol's address in large-GOT mode:
289 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
290 template<class NodeTy>
291 SDValue getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG,
292 unsigned HiFlag, unsigned LoFlag,
294 const MachinePointerInfo &PtrInfo) const {
296 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty,
297 getTargetNode(N, Ty, DAG, HiFlag));
298 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
299 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
300 getTargetNode(N, Ty, DAG, LoFlag));
301 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
305 // This method creates the following nodes, which are necessary for
306 // computing a symbol's address in non-PIC mode:
308 // (add %hi(sym), %lo(sym))
309 template<class NodeTy>
310 SDValue getAddrNonPIC(NodeTy *N, EVT Ty, SelectionDAG &DAG) const {
312 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
313 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
314 return DAG.getNode(ISD::ADD, DL, Ty,
315 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
316 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
319 /// This function fills Ops, which is the list of operands that will later
320 /// be used when a function call node is created. It also generates
321 /// copyToReg nodes to set up argument registers.
323 getOpndList(SmallVectorImpl<SDValue> &Ops,
324 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
325 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
326 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
328 /// ByValArgInfo - Byval argument information.
329 struct ByValArgInfo {
330 unsigned FirstIdx; // Index of the first register used.
331 unsigned NumRegs; // Number of registers used for this argument.
332 unsigned Address; // Offset of the stack area used to pass this argument.
334 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
337 /// MipsCC - This class provides methods used to analyze formal and call
338 /// arguments and inquire about calling convention information.
341 enum SpecialCallingConvType {
342 Mips16RetHelperConv, NoSpecialCallingConv
345 MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
346 SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
349 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
350 bool IsVarArg, bool IsSoftFloat,
351 const SDNode *CallNode,
352 std::vector<ArgListEntry> &FuncArgs);
353 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
355 Function::const_arg_iterator FuncArg);
357 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
358 bool IsSoftFloat, const SDNode *CallNode,
359 const Type *RetTy) const;
361 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
362 bool IsSoftFloat, const Type *RetTy) const;
364 const CCState &getCCInfo() const { return CCInfo; }
366 /// hasByValArg - Returns true if function has byval arguments.
367 bool hasByValArg() const { return !ByValArgs.empty(); }
369 /// regSize - Size (in number of bits) of integer registers.
370 unsigned regSize() const { return IsO32 ? 4 : 8; }
372 /// numIntArgRegs - Number of integer registers available for calls.
373 unsigned numIntArgRegs() const;
375 /// reservedArgArea - The size of the area the caller reserves for
376 /// register arguments. This is 16-byte if ABI is O32.
377 unsigned reservedArgArea() const;
379 /// Return pointer to array of integer argument registers.
380 const uint16_t *intArgRegs() const;
382 typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
383 byval_iterator byval_begin() const { return ByValArgs.begin(); }
384 byval_iterator byval_end() const { return ByValArgs.end(); }
387 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
388 CCValAssign::LocInfo LocInfo,
389 ISD::ArgFlagsTy ArgFlags);
391 /// useRegsForByval - Returns true if the calling convention allows the
392 /// use of registers to pass byval arguments.
393 bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
395 /// Return the function that analyzes fixed argument list functions.
396 llvm::CCAssignFn *fixedArgFn() const;
398 /// Return the function that analyzes variable argument list functions.
399 llvm::CCAssignFn *varArgFn() const;
401 const uint16_t *shadowRegs() const;
403 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
406 /// Return the type of the register which is used to pass an argument or
407 /// return a value. This function returns f64 if the argument is an i64
408 /// value which has been generated as a result of softening an f128 value.
409 /// Otherwise, it just returns VT.
410 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
411 bool IsSoftFloat) const;
413 template<typename Ty>
414 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
415 const SDNode *CallNode, const Type *RetTy) const;
418 CallingConv::ID CallConv;
420 SpecialCallingConvType SpecialCallingConv;
421 SmallVector<ByValArgInfo, 2> ByValArgs;
424 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
425 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
428 const MipsSubtarget *Subtarget;
430 bool HasMips64, IsN64, IsO32;
433 // Create a TargetGlobalAddress node.
434 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
435 unsigned Flag) const;
437 // Create a TargetExternalSymbol node.
438 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
439 unsigned Flag) const;
441 // Create a TargetBlockAddress node.
442 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
443 unsigned Flag) const;
445 // Create a TargetJumpTable node.
446 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
447 unsigned Flag) const;
449 // Create a TargetConstantPool node.
450 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
451 unsigned Flag) const;
453 MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
454 // Lower Operand helpers
455 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
456 CallingConv::ID CallConv, bool isVarArg,
457 const SmallVectorImpl<ISD::InputArg> &Ins,
458 SDLoc dl, SelectionDAG &DAG,
459 SmallVectorImpl<SDValue> &InVals,
460 const SDNode *CallNode, const Type *RetTy) const;
462 // Lower Operand specifics
463 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
464 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
465 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
466 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
467 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
468 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
469 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
470 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
471 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
472 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
473 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
474 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
475 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
476 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
477 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
478 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
479 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
480 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
481 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
483 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
484 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
486 /// isEligibleForTailCallOptimization - Check whether the call is eligible
487 /// for tail call optimization.
489 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
490 unsigned NextStackOffset,
491 const MipsFunctionInfo& FI) const = 0;
493 /// copyByValArg - Copy argument registers which were used to pass a byval
494 /// argument to the stack. Create a stack frame object for the byval
496 void copyByValRegs(SDValue Chain, SDLoc DL,
497 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
498 const ISD::ArgFlagsTy &Flags,
499 SmallVectorImpl<SDValue> &InVals,
500 const Argument *FuncArg,
501 const MipsCC &CC, const ByValArgInfo &ByVal) const;
503 /// passByValArg - Pass a byval argument in registers or on stack.
504 void passByValArg(SDValue Chain, SDLoc DL,
505 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
506 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
507 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
508 const MipsCC &CC, const ByValArgInfo &ByVal,
509 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
511 /// writeVarArgRegs - Write variable function arguments passed in registers
512 /// to the stack. Also create a stack frame object for the first variable
514 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
515 SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
518 LowerFormalArguments(SDValue Chain,
519 CallingConv::ID CallConv, bool isVarArg,
520 const SmallVectorImpl<ISD::InputArg> &Ins,
521 SDLoc dl, SelectionDAG &DAG,
522 SmallVectorImpl<SDValue> &InVals) const;
524 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
525 SDValue Arg, SDLoc DL, bool IsTailCall,
526 SelectionDAG &DAG) const;
529 LowerCall(TargetLowering::CallLoweringInfo &CLI,
530 SmallVectorImpl<SDValue> &InVals) const;
533 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
535 const SmallVectorImpl<ISD::OutputArg> &Outs,
536 LLVMContext &Context) const;
539 LowerReturn(SDValue Chain,
540 CallingConv::ID CallConv, bool isVarArg,
541 const SmallVectorImpl<ISD::OutputArg> &Outs,
542 const SmallVectorImpl<SDValue> &OutVals,
543 SDLoc dl, SelectionDAG &DAG) const;
545 // Inline asm support
546 ConstraintType getConstraintType(const std::string &Constraint) const;
548 /// Examine constraint string and operand type and determine a weight value.
549 /// The operand object must already have been set up with the operand type.
550 ConstraintWeight getSingleConstraintMatchWeight(
551 AsmOperandInfo &info, const char *constraint) const;
553 /// This function parses registers that appear in inline-asm constraints.
554 /// It returns pair (0, 0) on failure.
555 std::pair<unsigned, const TargetRegisterClass *>
556 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
558 std::pair<unsigned, const TargetRegisterClass*>
559 getRegForInlineAsmConstraint(const std::string &Constraint,
562 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
563 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
564 /// true it means one of the asm constraint of the inline asm instruction
565 /// being processed is 'm'.
566 virtual void LowerAsmOperandForConstraint(SDValue Op,
567 std::string &Constraint,
568 std::vector<SDValue> &Ops,
569 SelectionDAG &DAG) const;
571 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
573 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
575 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
577 bool IsMemset, bool ZeroMemset,
579 MachineFunction &MF) const;
581 /// isFPImmLegal - Returns true if the target can instruction select the
582 /// specified FP immediate natively. If false, the legalizer will
583 /// materialize the FP immediate as a load from a constant pool.
584 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
586 virtual unsigned getJumpTableEncoding() const;
588 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
589 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
590 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
591 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
592 bool Nand = false) const;
593 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
594 MachineBasicBlock *BB, unsigned Size) const;
595 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
596 MachineBasicBlock *BB, unsigned Size) const;
599 /// Create MipsTargetLowering objects.
600 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
601 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
604 #endif // MipsISELLOWERING_H