1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
18 #include "MCTargetDesc/MipsBaseInfo.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Target/TargetLowering.h"
31 // Start the numbering from where ISD NodeType finishes.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 // Jump and link (call)
40 // Get the Higher 16 bits from a 32-bit immediate
41 // No relation with Mips Hi register
44 // Get the Lower 16 bits from a 32-bit immediate
45 // No relation with Mips Lo register
48 // Handle gp_rel (small data/bss sections) relocation.
54 // Floating Point Branch Conditional
57 // Floating Point Compare
60 // Floating Point Conditional Moves
64 // FP-to-int truncation node.
72 // Node used to extract integer from accumulator.
76 // Node used to insert integers to accumulator.
107 // EXTR.W instrinsic nodes.
117 // DPA.W intrinsic nodes.
153 // DSP setcc and select_cc nodes.
157 // Vector comparisons.
158 // These take a vector and return a boolean.
164 // These take a vector and return a vector bitmask.
171 // Element-wise vector max/min.
177 // Vector Shuffle with mask as an operand
178 VSHF, // Generic shuffle
179 SHF, // 4-element set shuffle.
180 ILVEV, // Interleave even elements
181 ILVOD, // Interleave odd elements
182 ILVL, // Interleave left elements
183 ILVR, // Interleave right elements
184 PCKEV, // Pack even elements
185 PCKOD, // Pack odd elements
187 // Combined (XOR (OR $a, $b), -1)
190 // Extended vector element extraction
194 // Load/Store Left/Right nodes.
195 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
206 //===--------------------------------------------------------------------===//
207 // TargetLowering Implementation
208 //===--------------------------------------------------------------------===//
209 class MipsFunctionInfo;
211 class MipsTargetLowering : public TargetLowering {
214 explicit MipsTargetLowering(MipsTargetMachine &TM);
216 static const MipsTargetLowering *create(MipsTargetMachine &TM);
218 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
220 virtual void LowerOperationWrapper(SDNode *N,
221 SmallVectorImpl<SDValue> &Results,
222 SelectionDAG &DAG) const;
224 /// LowerOperation - Provide custom lowering hooks for some operations.
225 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
227 /// ReplaceNodeResults - Replace the results of node with an illegal result
228 /// type with new values built out of custom code.
230 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
231 SelectionDAG &DAG) const;
233 /// getTargetNodeName - This method returns the name of a target specific
235 virtual const char *getTargetNodeName(unsigned Opcode) const;
237 /// getSetCCResultType - get the ISD::SETCC result ValueType
238 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
240 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
242 virtual MachineBasicBlock *
243 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
246 bool operator()(const char *S1, const char *S2) const {
247 return strcmp(S1, S2) < 0;
252 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
254 // This method creates the following nodes, which are necessary for
255 // computing a local symbol's address:
257 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
258 template<class NodeTy>
259 SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
260 bool HasMips64) const {
262 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
263 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
264 getTargetNode(N, Ty, DAG, GOTFlag));
265 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
266 MachinePointerInfo::getGOT(), false, false,
268 unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
269 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
270 getTargetNode(N, Ty, DAG, LoFlag));
271 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
274 // This method creates the following nodes, which are necessary for
275 // computing a global symbol's address:
277 // (load (wrapper $gp, %got(sym)))
278 template<class NodeTy>
279 SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
280 unsigned Flag, SDValue Chain,
281 const MachinePointerInfo &PtrInfo) const {
283 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
284 getTargetNode(N, Ty, DAG, Flag));
285 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
288 // This method creates the following nodes, which are necessary for
289 // computing a global symbol's address in large-GOT mode:
291 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
292 template<class NodeTy>
293 SDValue getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG,
294 unsigned HiFlag, unsigned LoFlag,
296 const MachinePointerInfo &PtrInfo) const {
298 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty,
299 getTargetNode(N, Ty, DAG, HiFlag));
300 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
301 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
302 getTargetNode(N, Ty, DAG, LoFlag));
303 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
307 // This method creates the following nodes, which are necessary for
308 // computing a symbol's address in non-PIC mode:
310 // (add %hi(sym), %lo(sym))
311 template<class NodeTy>
312 SDValue getAddrNonPIC(NodeTy *N, EVT Ty, SelectionDAG &DAG) const {
314 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
315 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
316 return DAG.getNode(ISD::ADD, DL, Ty,
317 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
318 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
321 /// This function fills Ops, which is the list of operands that will later
322 /// be used when a function call node is created. It also generates
323 /// copyToReg nodes to set up argument registers.
325 getOpndList(SmallVectorImpl<SDValue> &Ops,
326 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
327 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
328 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
330 /// ByValArgInfo - Byval argument information.
331 struct ByValArgInfo {
332 unsigned FirstIdx; // Index of the first register used.
333 unsigned NumRegs; // Number of registers used for this argument.
334 unsigned Address; // Offset of the stack area used to pass this argument.
336 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
339 /// MipsCC - This class provides methods used to analyze formal and call
340 /// arguments and inquire about calling convention information.
343 enum SpecialCallingConvType {
344 Mips16RetHelperConv, NoSpecialCallingConv
347 MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
348 SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
351 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
352 bool IsVarArg, bool IsSoftFloat,
353 const SDNode *CallNode,
354 std::vector<ArgListEntry> &FuncArgs);
355 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
357 Function::const_arg_iterator FuncArg);
359 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
360 bool IsSoftFloat, const SDNode *CallNode,
361 const Type *RetTy) const;
363 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
364 bool IsSoftFloat, const Type *RetTy) const;
366 const CCState &getCCInfo() const { return CCInfo; }
368 /// hasByValArg - Returns true if function has byval arguments.
369 bool hasByValArg() const { return !ByValArgs.empty(); }
371 /// regSize - Size (in number of bits) of integer registers.
372 unsigned regSize() const { return IsO32 ? 4 : 8; }
374 /// numIntArgRegs - Number of integer registers available for calls.
375 unsigned numIntArgRegs() const;
377 /// reservedArgArea - The size of the area the caller reserves for
378 /// register arguments. This is 16-byte if ABI is O32.
379 unsigned reservedArgArea() const;
381 /// Return pointer to array of integer argument registers.
382 const uint16_t *intArgRegs() const;
384 typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
385 byval_iterator byval_begin() const { return ByValArgs.begin(); }
386 byval_iterator byval_end() const { return ByValArgs.end(); }
389 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
390 CCValAssign::LocInfo LocInfo,
391 ISD::ArgFlagsTy ArgFlags);
393 /// useRegsForByval - Returns true if the calling convention allows the
394 /// use of registers to pass byval arguments.
395 bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
397 /// Return the function that analyzes fixed argument list functions.
398 llvm::CCAssignFn *fixedArgFn() const;
400 /// Return the function that analyzes variable argument list functions.
401 llvm::CCAssignFn *varArgFn() const;
403 const uint16_t *shadowRegs() const;
405 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
408 /// Return the type of the register which is used to pass an argument or
409 /// return a value. This function returns f64 if the argument is an i64
410 /// value which has been generated as a result of softening an f128 value.
411 /// Otherwise, it just returns VT.
412 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
413 bool IsSoftFloat) const;
415 template<typename Ty>
416 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
417 const SDNode *CallNode, const Type *RetTy) const;
420 CallingConv::ID CallConv;
422 SpecialCallingConvType SpecialCallingConv;
423 SmallVector<ByValArgInfo, 2> ByValArgs;
426 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
427 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
430 const MipsSubtarget *Subtarget;
432 bool HasMips64, IsN64, IsO32;
435 // Create a TargetGlobalAddress node.
436 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
437 unsigned Flag) const;
439 // Create a TargetExternalSymbol node.
440 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
441 unsigned Flag) const;
443 // Create a TargetBlockAddress node.
444 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
445 unsigned Flag) const;
447 // Create a TargetJumpTable node.
448 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
449 unsigned Flag) const;
451 // Create a TargetConstantPool node.
452 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
453 unsigned Flag) const;
455 MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
456 // Lower Operand helpers
457 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
458 CallingConv::ID CallConv, bool isVarArg,
459 const SmallVectorImpl<ISD::InputArg> &Ins,
460 SDLoc dl, SelectionDAG &DAG,
461 SmallVectorImpl<SDValue> &InVals,
462 const SDNode *CallNode, const Type *RetTy) const;
464 // Lower Operand specifics
465 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
466 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
467 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
468 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
469 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
470 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
471 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
472 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
473 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
474 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
475 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
476 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
477 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
478 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
479 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
480 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
481 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
482 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
483 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
485 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
486 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
488 /// isEligibleForTailCallOptimization - Check whether the call is eligible
489 /// for tail call optimization.
491 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
492 unsigned NextStackOffset,
493 const MipsFunctionInfo& FI) const = 0;
495 /// copyByValArg - Copy argument registers which were used to pass a byval
496 /// argument to the stack. Create a stack frame object for the byval
498 void copyByValRegs(SDValue Chain, SDLoc DL,
499 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
500 const ISD::ArgFlagsTy &Flags,
501 SmallVectorImpl<SDValue> &InVals,
502 const Argument *FuncArg,
503 const MipsCC &CC, const ByValArgInfo &ByVal) const;
505 /// passByValArg - Pass a byval argument in registers or on stack.
506 void passByValArg(SDValue Chain, SDLoc DL,
507 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
508 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
509 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
510 const MipsCC &CC, const ByValArgInfo &ByVal,
511 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
513 /// writeVarArgRegs - Write variable function arguments passed in registers
514 /// to the stack. Also create a stack frame object for the first variable
516 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
517 SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
520 LowerFormalArguments(SDValue Chain,
521 CallingConv::ID CallConv, bool isVarArg,
522 const SmallVectorImpl<ISD::InputArg> &Ins,
523 SDLoc dl, SelectionDAG &DAG,
524 SmallVectorImpl<SDValue> &InVals) const;
526 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
527 SDValue Arg, SDLoc DL, bool IsTailCall,
528 SelectionDAG &DAG) const;
531 LowerCall(TargetLowering::CallLoweringInfo &CLI,
532 SmallVectorImpl<SDValue> &InVals) const;
535 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
537 const SmallVectorImpl<ISD::OutputArg> &Outs,
538 LLVMContext &Context) const;
541 LowerReturn(SDValue Chain,
542 CallingConv::ID CallConv, bool isVarArg,
543 const SmallVectorImpl<ISD::OutputArg> &Outs,
544 const SmallVectorImpl<SDValue> &OutVals,
545 SDLoc dl, SelectionDAG &DAG) const;
547 // Inline asm support
548 ConstraintType getConstraintType(const std::string &Constraint) const;
550 /// Examine constraint string and operand type and determine a weight value.
551 /// The operand object must already have been set up with the operand type.
552 ConstraintWeight getSingleConstraintMatchWeight(
553 AsmOperandInfo &info, const char *constraint) const;
555 /// This function parses registers that appear in inline-asm constraints.
556 /// It returns pair (0, 0) on failure.
557 std::pair<unsigned, const TargetRegisterClass *>
558 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
560 std::pair<unsigned, const TargetRegisterClass*>
561 getRegForInlineAsmConstraint(const std::string &Constraint,
564 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
565 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
566 /// true it means one of the asm constraint of the inline asm instruction
567 /// being processed is 'm'.
568 virtual void LowerAsmOperandForConstraint(SDValue Op,
569 std::string &Constraint,
570 std::vector<SDValue> &Ops,
571 SelectionDAG &DAG) const;
573 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
575 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
577 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
579 bool IsMemset, bool ZeroMemset,
581 MachineFunction &MF) const;
583 /// isFPImmLegal - Returns true if the target can instruction select the
584 /// specified FP immediate natively. If false, the legalizer will
585 /// materialize the FP immediate as a load from a constant pool.
586 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
588 virtual unsigned getJumpTableEncoding() const;
590 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
591 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
592 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
593 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
594 bool Nand = false) const;
595 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
596 MachineBasicBlock *BB, unsigned Size) const;
597 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
598 MachineBasicBlock *BB, unsigned Size) const;
601 /// Create MipsTargetLowering objects.
602 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
603 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
606 #endif // MipsISELLOWERING_H