1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
18 #include "MCTargetDesc/MipsABIInfo.h"
19 #include "MCTargetDesc/MipsBaseInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Target/TargetLowering.h"
30 enum NodeType : unsigned {
31 // Start the numbering from where ISD NodeType finishes.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 // Jump and link (call)
40 // Get the Higher 16 bits from a 32-bit immediate
41 // No relation with Mips Hi register
44 // Get the Lower 16 bits from a 32-bit immediate
45 // No relation with Mips Lo register
48 // Handle gp_rel (small data/bss sections) relocation.
54 // Floating Point Branch Conditional
57 // Floating Point Compare
60 // Floating Point Conditional Moves
64 // FP-to-int truncation node.
72 // Node used to extract integer from accumulator.
76 // Node used to insert integers to accumulator.
107 // EXTR.W instrinsic nodes.
117 // DPA.W intrinsic nodes.
153 // DSP setcc and select_cc nodes.
157 // Vector comparisons.
158 // These take a vector and return a boolean.
164 // These take a vector and return a vector bitmask.
171 // Element-wise vector max/min.
177 // Vector Shuffle with mask as an operand
178 VSHF, // Generic shuffle
179 SHF, // 4-element set shuffle.
180 ILVEV, // Interleave even elements
181 ILVOD, // Interleave odd elements
182 ILVL, // Interleave left elements
183 ILVR, // Interleave right elements
184 PCKEV, // Pack even elements
185 PCKOD, // Pack odd elements
188 INSVE, // Copy element from one vector to another
190 // Combined (XOR (OR $a, $b), -1)
193 // Extended vector element extraction
197 // Load/Store Left/Right nodes.
198 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
209 //===--------------------------------------------------------------------===//
210 // TargetLowering Implementation
211 //===--------------------------------------------------------------------===//
212 class MipsFunctionInfo;
216 class MipsTargetLowering : public TargetLowering {
219 explicit MipsTargetLowering(const MipsTargetMachine &TM,
220 const MipsSubtarget &STI);
222 static const MipsTargetLowering *create(const MipsTargetMachine &TM,
223 const MipsSubtarget &STI);
225 /// createFastISel - This method returns a target specific FastISel object,
226 /// or null if the target does not support "fast" ISel.
227 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
228 const TargetLibraryInfo *libInfo) const override;
230 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
234 void LowerOperationWrapper(SDNode *N,
235 SmallVectorImpl<SDValue> &Results,
236 SelectionDAG &DAG) const override;
238 /// LowerOperation - Provide custom lowering hooks for some operations.
239 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
241 /// ReplaceNodeResults - Replace the results of node with an illegal result
242 /// type with new values built out of custom code.
244 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
245 SelectionDAG &DAG) const override;
247 /// getTargetNodeName - This method returns the name of a target specific
249 const char *getTargetNodeName(unsigned Opcode) const override;
251 /// getSetCCResultType - get the ISD::SETCC result ValueType
252 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
253 EVT VT) const override;
255 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
258 EmitInstrWithCustomInserter(MachineInstr *MI,
259 MachineBasicBlock *MBB) const override;
262 bool operator()(const char *S1, const char *S2) const {
263 return strcmp(S1, S2) < 0;
267 void HandleByVal(CCState *, unsigned &, unsigned) const override;
269 unsigned getRegisterByName(const char* RegName, EVT VT,
270 SelectionDAG &DAG) const override;
272 /// Returns true if a cast between SrcAS and DestAS is a noop.
273 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
274 // Mips doesn't have any special address spaces so we just reserve
275 // the first 256 for software use (e.g. OpenCL) and treat casts
276 // between them as noops.
277 return SrcAS < 256 && DestAS < 256;
281 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
283 // This method creates the following nodes, which are necessary for
284 // computing a local symbol's address:
286 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
287 template <class NodeTy>
288 SDValue getAddrLocal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG,
289 bool IsN32OrN64) const {
290 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
291 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
292 getTargetNode(N, Ty, DAG, GOTFlag));
294 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
295 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
296 false, false, false, 0);
297 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
298 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
299 getTargetNode(N, Ty, DAG, LoFlag));
300 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
303 // This method creates the following nodes, which are necessary for
304 // computing a global symbol's address:
306 // (load (wrapper $gp, %got(sym)))
307 template <class NodeTy>
308 SDValue getAddrGlobal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG,
309 unsigned Flag, SDValue Chain,
310 const MachinePointerInfo &PtrInfo) const {
311 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
312 getTargetNode(N, Ty, DAG, Flag));
313 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
316 // This method creates the following nodes, which are necessary for
317 // computing a global symbol's address in large-GOT mode:
319 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
320 template <class NodeTy>
321 SDValue getAddrGlobalLargeGOT(NodeTy *N, SDLoc DL, EVT Ty,
322 SelectionDAG &DAG, unsigned HiFlag,
323 unsigned LoFlag, SDValue Chain,
324 const MachinePointerInfo &PtrInfo) const {
326 DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(N, Ty, DAG, HiFlag));
327 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
328 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
329 getTargetNode(N, Ty, DAG, LoFlag));
330 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
334 // This method creates the following nodes, which are necessary for
335 // computing a symbol's address in non-PIC mode:
337 // (add %hi(sym), %lo(sym))
338 template <class NodeTy>
339 SDValue getAddrNonPIC(NodeTy *N, SDLoc DL, EVT Ty,
340 SelectionDAG &DAG) const {
341 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
342 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
343 return DAG.getNode(ISD::ADD, DL, Ty,
344 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
345 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
348 // This method creates the following nodes, which are necessary for
349 // computing a symbol's address using gp-relative addressing:
351 // (add $gp, %gp_rel(sym))
352 template <class NodeTy>
353 SDValue getAddrGPRel(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) const {
354 assert(Ty == MVT::i32);
355 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
356 return DAG.getNode(ISD::ADD, DL, Ty,
357 DAG.getRegister(Mips::GP, Ty),
358 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty),
362 /// This function fills Ops, which is the list of operands that will later
363 /// be used when a function call node is created. It also generates
364 /// copyToReg nodes to set up argument registers.
366 getOpndList(SmallVectorImpl<SDValue> &Ops,
367 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
368 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
369 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
370 SDValue Chain) const;
373 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
374 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
377 const MipsSubtarget &Subtarget;
378 // Cache the ABI from the TargetMachine, we use it everywhere.
379 const MipsABIInfo &ABI;
382 // Create a TargetGlobalAddress node.
383 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
384 unsigned Flag) const;
386 // Create a TargetExternalSymbol node.
387 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
388 unsigned Flag) const;
390 // Create a TargetBlockAddress node.
391 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
392 unsigned Flag) const;
394 // Create a TargetJumpTable node.
395 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
396 unsigned Flag) const;
398 // Create a TargetConstantPool node.
399 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
400 unsigned Flag) const;
402 // Lower Operand helpers
403 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
404 CallingConv::ID CallConv, bool isVarArg,
405 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
406 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
407 TargetLowering::CallLoweringInfo &CLI) const;
409 // Lower Operand specifics
410 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
411 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
412 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
413 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
414 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
415 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
416 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
417 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
418 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
419 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
420 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
421 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
422 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
423 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
424 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
425 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
426 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
427 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
428 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
429 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
431 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
432 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
434 /// isEligibleForTailCallOptimization - Check whether the call is eligible
435 /// for tail call optimization.
437 isEligibleForTailCallOptimization(const CCState &CCInfo,
438 unsigned NextStackOffset,
439 const MipsFunctionInfo &FI) const = 0;
441 /// copyByValArg - Copy argument registers which were used to pass a byval
442 /// argument to the stack. Create a stack frame object for the byval
444 void copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
445 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
446 SmallVectorImpl<SDValue> &InVals,
447 const Argument *FuncArg, unsigned FirstReg,
448 unsigned LastReg, const CCValAssign &VA,
449 MipsCCState &State) const;
451 /// passByValArg - Pass a byval argument in registers or on stack.
452 void passByValArg(SDValue Chain, SDLoc DL,
453 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
454 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
455 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
456 unsigned FirstReg, unsigned LastReg,
457 const ISD::ArgFlagsTy &Flags, bool isLittle,
458 const CCValAssign &VA) const;
460 /// writeVarArgRegs - Write variable function arguments passed in registers
461 /// to the stack. Also create a stack frame object for the first variable
463 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
464 SDLoc DL, SelectionDAG &DAG, CCState &State) const;
467 LowerFormalArguments(SDValue Chain,
468 CallingConv::ID CallConv, bool isVarArg,
469 const SmallVectorImpl<ISD::InputArg> &Ins,
470 SDLoc dl, SelectionDAG &DAG,
471 SmallVectorImpl<SDValue> &InVals) const override;
473 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
474 SDValue Arg, SDLoc DL, bool IsTailCall,
475 SelectionDAG &DAG) const;
477 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
478 SmallVectorImpl<SDValue> &InVals) const override;
480 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
482 const SmallVectorImpl<ISD::OutputArg> &Outs,
483 LLVMContext &Context) const override;
485 SDValue LowerReturn(SDValue Chain,
486 CallingConv::ID CallConv, bool isVarArg,
487 const SmallVectorImpl<ISD::OutputArg> &Outs,
488 const SmallVectorImpl<SDValue> &OutVals,
489 SDLoc dl, SelectionDAG &DAG) const override;
491 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
493 // Inline asm support
494 ConstraintType getConstraintType(StringRef Constraint) const override;
496 /// Examine constraint string and operand type and determine a weight value.
497 /// The operand object must already have been set up with the operand type.
498 ConstraintWeight getSingleConstraintMatchWeight(
499 AsmOperandInfo &info, const char *constraint) const override;
501 /// This function parses registers that appear in inline-asm constraints.
502 /// It returns pair (0, 0) on failure.
503 std::pair<unsigned, const TargetRegisterClass *>
504 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
506 std::pair<unsigned, const TargetRegisterClass *>
507 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
508 StringRef Constraint, MVT VT) const override;
510 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
511 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
512 /// true it means one of the asm constraint of the inline asm instruction
513 /// being processed is 'm'.
514 void LowerAsmOperandForConstraint(SDValue Op,
515 std::string &Constraint,
516 std::vector<SDValue> &Ops,
517 SelectionDAG &DAG) const override;
520 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
521 if (ConstraintCode == "R")
522 return InlineAsm::Constraint_R;
523 else if (ConstraintCode == "ZC")
524 return InlineAsm::Constraint_ZC;
525 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
528 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
529 Type *Ty, unsigned AS) const override;
531 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
533 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
535 bool IsMemset, bool ZeroMemset,
537 MachineFunction &MF) const override;
539 /// isFPImmLegal - Returns true if the target can instruction select the
540 /// specified FP immediate natively. If false, the legalizer will
541 /// materialize the FP immediate as a load from a constant pool.
542 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
544 unsigned getJumpTableEncoding() const override;
545 bool useSoftFloat() const override;
547 /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
548 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI,
549 MachineBasicBlock *BB,
550 unsigned Size, unsigned DstReg,
551 unsigned SrcRec) const;
553 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
554 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
555 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
556 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
557 bool Nand = false) const;
558 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
559 MachineBasicBlock *BB, unsigned Size) const;
560 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
561 MachineBasicBlock *BB, unsigned Size) const;
562 MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const;
563 MachineBasicBlock *emitPseudoSELECT(MachineInstr *MI,
564 MachineBasicBlock *BB, bool isFPCmp,
568 /// Create MipsTargetLowering objects.
569 const MipsTargetLowering *
570 createMips16TargetLowering(const MipsTargetMachine &TM,
571 const MipsSubtarget &STI);
572 const MipsTargetLowering *
573 createMipsSETargetLowering(const MipsTargetMachine &TM,
574 const MipsSubtarget &STI);
577 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
578 const TargetLibraryInfo *libInfo);