1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
18 #include "MCTargetDesc/MipsABIInfo.h"
19 #include "MCTargetDesc/MipsBaseInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Target/TargetLowering.h"
30 enum NodeType : unsigned {
31 // Start the numbering from where ISD NodeType finishes.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 // Jump and link (call)
40 // Get the Higher 16 bits from a 32-bit immediate
41 // No relation with Mips Hi register
44 // Get the Lower 16 bits from a 32-bit immediate
45 // No relation with Mips Lo register
48 // Handle gp_rel (small data/bss sections) relocation.
54 // Floating Point Branch Conditional
57 // Floating Point Compare
60 // Floating Point Conditional Moves
64 // FP-to-int truncation node.
70 // Interrupt, exception, error trap Return
73 // Software Exception Return.
76 // Node used to extract integer from accumulator.
80 // Node used to insert integers to accumulator.
111 // EXTR.W instrinsic nodes.
121 // DPA.W intrinsic nodes.
157 // DSP setcc and select_cc nodes.
161 // Vector comparisons.
162 // These take a vector and return a boolean.
168 // These take a vector and return a vector bitmask.
175 // Element-wise vector max/min.
181 // Vector Shuffle with mask as an operand
182 VSHF, // Generic shuffle
183 SHF, // 4-element set shuffle.
184 ILVEV, // Interleave even elements
185 ILVOD, // Interleave odd elements
186 ILVL, // Interleave left elements
187 ILVR, // Interleave right elements
188 PCKEV, // Pack even elements
189 PCKOD, // Pack odd elements
192 INSVE, // Copy element from one vector to another
194 // Combined (XOR (OR $a, $b), -1)
197 // Extended vector element extraction
201 // Load/Store Left/Right nodes.
202 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
213 //===--------------------------------------------------------------------===//
214 // TargetLowering Implementation
215 //===--------------------------------------------------------------------===//
216 class MipsFunctionInfo;
220 class MipsTargetLowering : public TargetLowering {
223 explicit MipsTargetLowering(const MipsTargetMachine &TM,
224 const MipsSubtarget &STI);
226 static const MipsTargetLowering *create(const MipsTargetMachine &TM,
227 const MipsSubtarget &STI);
229 /// createFastISel - This method returns a target specific FastISel object,
230 /// or null if the target does not support "fast" ISel.
231 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
232 const TargetLibraryInfo *libInfo) const override;
234 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
238 bool isCheapToSpeculateCttz() const override;
239 bool isCheapToSpeculateCtlz() const override;
241 void LowerOperationWrapper(SDNode *N,
242 SmallVectorImpl<SDValue> &Results,
243 SelectionDAG &DAG) const override;
245 /// LowerOperation - Provide custom lowering hooks for some operations.
246 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
248 /// ReplaceNodeResults - Replace the results of node with an illegal result
249 /// type with new values built out of custom code.
251 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
252 SelectionDAG &DAG) const override;
254 /// getTargetNodeName - This method returns the name of a target specific
256 const char *getTargetNodeName(unsigned Opcode) const override;
258 /// getSetCCResultType - get the ISD::SETCC result ValueType
259 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
260 EVT VT) const override;
262 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
265 EmitInstrWithCustomInserter(MachineInstr *MI,
266 MachineBasicBlock *MBB) const override;
268 void HandleByVal(CCState *, unsigned &, unsigned) const override;
270 unsigned getRegisterByName(const char* RegName, EVT VT,
271 SelectionDAG &DAG) const override;
273 /// If a physical register, this returns the register that receives the
274 /// exception address on entry to an EH pad.
276 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
277 return ABI.IsN64() ? Mips::A0_64 : Mips::A0;
280 /// If a physical register, this returns the register that receives the
281 /// exception typeid on entry to a landing pad.
283 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
284 return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
287 /// Returns true if a cast between SrcAS and DestAS is a noop.
288 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
289 // Mips doesn't have any special address spaces so we just reserve
290 // the first 256 for software use (e.g. OpenCL) and treat casts
291 // between them as noops.
292 return SrcAS < 256 && DestAS < 256;
296 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
298 // This method creates the following nodes, which are necessary for
299 // computing a local symbol's address:
301 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
302 template <class NodeTy>
303 SDValue getAddrLocal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG,
304 bool IsN32OrN64) const {
305 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
306 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
307 getTargetNode(N, Ty, DAG, GOTFlag));
309 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
310 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
311 false, false, false, 0);
312 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
313 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
314 getTargetNode(N, Ty, DAG, LoFlag));
315 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
318 // This method creates the following nodes, which are necessary for
319 // computing a global symbol's address:
321 // (load (wrapper $gp, %got(sym)))
322 template <class NodeTy>
323 SDValue getAddrGlobal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG,
324 unsigned Flag, SDValue Chain,
325 const MachinePointerInfo &PtrInfo) const {
326 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
327 getTargetNode(N, Ty, DAG, Flag));
328 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
331 // This method creates the following nodes, which are necessary for
332 // computing a global symbol's address in large-GOT mode:
334 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
335 template <class NodeTy>
336 SDValue getAddrGlobalLargeGOT(NodeTy *N, SDLoc DL, EVT Ty,
337 SelectionDAG &DAG, unsigned HiFlag,
338 unsigned LoFlag, SDValue Chain,
339 const MachinePointerInfo &PtrInfo) const {
341 DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(N, Ty, DAG, HiFlag));
342 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
343 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
344 getTargetNode(N, Ty, DAG, LoFlag));
345 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
349 // This method creates the following nodes, which are necessary for
350 // computing a symbol's address in non-PIC mode:
352 // (add %hi(sym), %lo(sym))
353 template <class NodeTy>
354 SDValue getAddrNonPIC(NodeTy *N, SDLoc DL, EVT Ty,
355 SelectionDAG &DAG) const {
356 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
357 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
358 return DAG.getNode(ISD::ADD, DL, Ty,
359 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
360 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
363 // This method creates the following nodes, which are necessary for
364 // computing a symbol's address using gp-relative addressing:
366 // (add $gp, %gp_rel(sym))
367 template <class NodeTy>
368 SDValue getAddrGPRel(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) const {
369 assert(Ty == MVT::i32);
370 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
371 return DAG.getNode(ISD::ADD, DL, Ty,
372 DAG.getRegister(Mips::GP, Ty),
373 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty),
377 /// This function fills Ops, which is the list of operands that will later
378 /// be used when a function call node is created. It also generates
379 /// copyToReg nodes to set up argument registers.
381 getOpndList(SmallVectorImpl<SDValue> &Ops,
382 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
383 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
384 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
385 SDValue Chain) const;
388 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
389 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
392 const MipsSubtarget &Subtarget;
393 // Cache the ABI from the TargetMachine, we use it everywhere.
394 const MipsABIInfo &ABI;
397 // Create a TargetGlobalAddress node.
398 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
399 unsigned Flag) const;
401 // Create a TargetExternalSymbol node.
402 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
403 unsigned Flag) const;
405 // Create a TargetBlockAddress node.
406 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
407 unsigned Flag) const;
409 // Create a TargetJumpTable node.
410 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
411 unsigned Flag) const;
413 // Create a TargetConstantPool node.
414 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
415 unsigned Flag) const;
417 // Lower Operand helpers
418 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
419 CallingConv::ID CallConv, bool isVarArg,
420 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
421 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
422 TargetLowering::CallLoweringInfo &CLI) const;
424 // Lower Operand specifics
425 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
426 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
427 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
428 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
429 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
430 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
431 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
432 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
433 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
434 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
435 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
436 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
437 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
438 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
439 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
440 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
441 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
442 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
443 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
444 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
446 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
447 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
449 /// isEligibleForTailCallOptimization - Check whether the call is eligible
450 /// for tail call optimization.
452 isEligibleForTailCallOptimization(const CCState &CCInfo,
453 unsigned NextStackOffset,
454 const MipsFunctionInfo &FI) const = 0;
456 /// copyByValArg - Copy argument registers which were used to pass a byval
457 /// argument to the stack. Create a stack frame object for the byval
459 void copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
460 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
461 SmallVectorImpl<SDValue> &InVals,
462 const Argument *FuncArg, unsigned FirstReg,
463 unsigned LastReg, const CCValAssign &VA,
464 MipsCCState &State) const;
466 /// passByValArg - Pass a byval argument in registers or on stack.
467 void passByValArg(SDValue Chain, SDLoc DL,
468 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
469 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
470 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
471 unsigned FirstReg, unsigned LastReg,
472 const ISD::ArgFlagsTy &Flags, bool isLittle,
473 const CCValAssign &VA) const;
475 /// writeVarArgRegs - Write variable function arguments passed in registers
476 /// to the stack. Also create a stack frame object for the first variable
478 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
479 SDLoc DL, SelectionDAG &DAG, CCState &State) const;
482 LowerFormalArguments(SDValue Chain,
483 CallingConv::ID CallConv, bool isVarArg,
484 const SmallVectorImpl<ISD::InputArg> &Ins,
485 SDLoc dl, SelectionDAG &DAG,
486 SmallVectorImpl<SDValue> &InVals) const override;
488 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
489 SDValue Arg, SDLoc DL, bool IsTailCall,
490 SelectionDAG &DAG) const;
492 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
493 SmallVectorImpl<SDValue> &InVals) const override;
495 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
497 const SmallVectorImpl<ISD::OutputArg> &Outs,
498 LLVMContext &Context) const override;
500 SDValue LowerReturn(SDValue Chain,
501 CallingConv::ID CallConv, bool isVarArg,
502 const SmallVectorImpl<ISD::OutputArg> &Outs,
503 const SmallVectorImpl<SDValue> &OutVals,
504 SDLoc dl, SelectionDAG &DAG) const override;
506 SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, SDLoc DL,
507 SelectionDAG &DAG) const;
509 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
511 // Inline asm support
512 ConstraintType getConstraintType(StringRef Constraint) const override;
514 /// Examine constraint string and operand type and determine a weight value.
515 /// The operand object must already have been set up with the operand type.
516 ConstraintWeight getSingleConstraintMatchWeight(
517 AsmOperandInfo &info, const char *constraint) const override;
519 /// This function parses registers that appear in inline-asm constraints.
520 /// It returns pair (0, 0) on failure.
521 std::pair<unsigned, const TargetRegisterClass *>
522 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
524 std::pair<unsigned, const TargetRegisterClass *>
525 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
526 StringRef Constraint, MVT VT) const override;
528 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
529 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
530 /// true it means one of the asm constraint of the inline asm instruction
531 /// being processed is 'm'.
532 void LowerAsmOperandForConstraint(SDValue Op,
533 std::string &Constraint,
534 std::vector<SDValue> &Ops,
535 SelectionDAG &DAG) const override;
538 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
539 if (ConstraintCode == "R")
540 return InlineAsm::Constraint_R;
541 else if (ConstraintCode == "ZC")
542 return InlineAsm::Constraint_ZC;
543 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
546 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
547 Type *Ty, unsigned AS) const override;
549 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
551 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
553 bool IsMemset, bool ZeroMemset,
555 MachineFunction &MF) const override;
557 /// isFPImmLegal - Returns true if the target can instruction select the
558 /// specified FP immediate natively. If false, the legalizer will
559 /// materialize the FP immediate as a load from a constant pool.
560 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
562 unsigned getJumpTableEncoding() const override;
563 bool useSoftFloat() const override;
565 /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
566 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI,
567 MachineBasicBlock *BB,
568 unsigned Size, unsigned DstReg,
569 unsigned SrcRec) const;
571 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
572 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
573 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
574 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
575 bool Nand = false) const;
576 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
577 MachineBasicBlock *BB, unsigned Size) const;
578 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
579 MachineBasicBlock *BB, unsigned Size) const;
580 MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const;
581 MachineBasicBlock *emitPseudoSELECT(MachineInstr *MI,
582 MachineBasicBlock *BB, bool isFPCmp,
586 /// Create MipsTargetLowering objects.
587 const MipsTargetLowering *
588 createMips16TargetLowering(const MipsTargetMachine &TM,
589 const MipsSubtarget &STI);
590 const MipsTargetLowering *
591 createMipsSETargetLowering(const MipsTargetMachine &TM,
592 const MipsSubtarget &STI);
595 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
596 const TargetLibraryInfo *libInfo);