1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/Target/TargetLowering.h"
27 // Start the numbering from where ISD NodeType finishes.
28 FIRST_NUMBER = ISD::BUILTIN_OP_END,
30 // Jump and link (call)
36 // Get the Higher 16 bits from a 32-bit immediate
37 // No relation with Mips Hi register
40 // Get the Lower 16 bits from a 32-bit immediate
41 // No relation with Mips Lo register
44 // Handle gp_rel (small data/bss sections) relocation.
50 // Floating Point Branch Conditional
53 // Floating Point Compare
56 // Floating Point Conditional Moves
60 // Floating Point Rounding
88 // EXTR.W instrinsic nodes.
98 // DPA.W intrinsic nodes.
129 // Load/Store Left/Right nodes.
130 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
141 //===--------------------------------------------------------------------===//
142 // TargetLowering Implementation
143 //===--------------------------------------------------------------------===//
144 class MipsFunctionInfo;
146 class MipsTargetLowering : public TargetLowering {
148 explicit MipsTargetLowering(MipsTargetMachine &TM);
150 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
152 virtual bool allowsUnalignedMemoryAccesses (EVT VT, bool *Fast) const;
154 virtual void LowerOperationWrapper(SDNode *N,
155 SmallVectorImpl<SDValue> &Results,
156 SelectionDAG &DAG) const;
158 /// LowerOperation - Provide custom lowering hooks for some operations.
159 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
161 /// ReplaceNodeResults - Replace the results of node with an illegal result
162 /// type with new values built out of custom code.
164 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
165 SelectionDAG &DAG) const;
167 /// getTargetNodeName - This method returns the name of a target specific
169 virtual const char *getTargetNodeName(unsigned Opcode) const;
171 /// getSetCCResultType - get the ISD::SETCC result ValueType
172 EVT getSetCCResultType(EVT VT) const;
174 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
177 void setMips16HardFloatLibCalls();
179 /// ByValArgInfo - Byval argument information.
180 struct ByValArgInfo {
181 unsigned FirstIdx; // Index of the first register used.
182 unsigned NumRegs; // Number of registers used for this argument.
183 unsigned Address; // Offset of the stack area used to pass this argument.
185 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
188 /// MipsCC - This class provides methods used to analyze formal and call
189 /// arguments and inquire about calling convention information.
192 MipsCC(CallingConv::ID CallConv, bool IsVarArg, bool IsO32,
195 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs);
196 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins);
197 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
198 CCValAssign::LocInfo LocInfo,
199 ISD::ArgFlagsTy ArgFlags);
201 const CCState &getCCInfo() const { return CCInfo; }
203 /// hasByValArg - Returns true if function has byval arguments.
204 bool hasByValArg() const { return !ByValArgs.empty(); }
206 /// useRegsForByval - Returns true if the calling convention allows the
207 /// use of registers to pass byval arguments.
208 bool useRegsForByval() const { return UseRegsForByval; }
210 /// regSize - Size (in number of bits) of integer registers.
211 unsigned regSize() const { return RegSize; }
213 /// numIntArgRegs - Number of integer registers available for calls.
214 unsigned numIntArgRegs() const { return NumIntArgRegs; }
216 /// reservedArgArea - The size of the area the caller reserves for
217 /// register arguments. This is 16-byte if ABI is O32.
218 unsigned reservedArgArea() const { return ReservedArgArea; }
220 /// intArgRegs - Pointer to array of integer registers.
221 const uint16_t *intArgRegs() const { return IntArgRegs; }
223 typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator;
224 byval_iterator byval_begin() const { return ByValArgs.begin(); }
225 byval_iterator byval_end() const { return ByValArgs.end(); }
228 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
232 bool UseRegsForByval;
234 unsigned NumIntArgRegs;
235 unsigned ReservedArgArea;
236 const uint16_t *IntArgRegs, *ShadowRegs;
237 SmallVector<ByValArgInfo, 2> ByValArgs;
238 llvm::CCAssignFn *FixedFn, *VarFn;
242 const MipsSubtarget *Subtarget;
244 bool HasMips64, IsN64, IsO32;
246 // Lower Operand helpers
247 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
248 CallingConv::ID CallConv, bool isVarArg,
249 const SmallVectorImpl<ISD::InputArg> &Ins,
250 DebugLoc dl, SelectionDAG &DAG,
251 SmallVectorImpl<SDValue> &InVals) const;
253 // Lower Operand specifics
254 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
255 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
256 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
257 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
258 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
259 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
260 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
261 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
262 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
263 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
264 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
265 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
266 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
267 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
268 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
269 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
270 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
271 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
273 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
274 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
275 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
276 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
277 SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
279 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
280 /// for tail call optimization.
281 bool IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
282 unsigned NextStackOffset,
283 const MipsFunctionInfo& FI) const;
285 /// copyByValArg - Copy argument registers which were used to pass a byval
286 /// argument to the stack. Create a stack frame object for the byval
288 void copyByValRegs(SDValue Chain, DebugLoc DL,
289 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
290 const ISD::ArgFlagsTy &Flags,
291 SmallVectorImpl<SDValue> &InVals,
292 const Argument *FuncArg,
293 const MipsCC &CC, const ByValArgInfo &ByVal) const;
295 /// passByValArg - Pass a byval argument in registers or on stack.
296 void passByValArg(SDValue Chain, DebugLoc DL,
297 SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass,
298 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
299 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
300 const MipsCC &CC, const ByValArgInfo &ByVal,
301 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
303 /// writeVarArgRegs - Write variable function arguments passed in registers
304 /// to the stack. Also create a stack frame object for the first variable
306 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
307 SDValue Chain, DebugLoc DL, SelectionDAG &DAG) const;
310 LowerFormalArguments(SDValue Chain,
311 CallingConv::ID CallConv, bool isVarArg,
312 const SmallVectorImpl<ISD::InputArg> &Ins,
313 DebugLoc dl, SelectionDAG &DAG,
314 SmallVectorImpl<SDValue> &InVals) const;
316 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
317 SDValue Arg, DebugLoc DL, bool IsTailCall,
318 SelectionDAG &DAG) const;
321 LowerCall(TargetLowering::CallLoweringInfo &CLI,
322 SmallVectorImpl<SDValue> &InVals) const;
325 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
327 const SmallVectorImpl<ISD::OutputArg> &Outs,
328 LLVMContext &Context) const;
331 LowerReturn(SDValue Chain,
332 CallingConv::ID CallConv, bool isVarArg,
333 const SmallVectorImpl<ISD::OutputArg> &Outs,
334 const SmallVectorImpl<SDValue> &OutVals,
335 DebugLoc dl, SelectionDAG &DAG) const;
337 virtual MachineBasicBlock *
338 EmitInstrWithCustomInserter(MachineInstr *MI,
339 MachineBasicBlock *MBB) const;
341 // Inline asm support
342 ConstraintType getConstraintType(const std::string &Constraint) const;
344 /// Examine constraint string and operand type and determine a weight value.
345 /// The operand object must already have been set up with the operand type.
346 ConstraintWeight getSingleConstraintMatchWeight(
347 AsmOperandInfo &info, const char *constraint) const;
349 std::pair<unsigned, const TargetRegisterClass*>
350 getRegForInlineAsmConstraint(const std::string &Constraint,
353 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
354 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
355 /// true it means one of the asm constraint of the inline asm instruction
356 /// being processed is 'm'.
357 virtual void LowerAsmOperandForConstraint(SDValue Op,
358 std::string &Constraint,
359 std::vector<SDValue> &Ops,
360 SelectionDAG &DAG) const;
362 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
364 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
366 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
368 bool IsMemset, bool ZeroMemset,
370 MachineFunction &MF) const;
372 /// isFPImmLegal - Returns true if the target can instruction select the
373 /// specified FP immediate natively. If false, the legalizer will
374 /// materialize the FP immediate as a load from a constant pool.
375 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
377 virtual unsigned getJumpTableEncoding() const;
379 MachineBasicBlock *EmitBPOSGE32(MachineInstr *MI,
380 MachineBasicBlock *BB) const;
381 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
382 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
383 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
384 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
385 bool Nand = false) const;
386 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
387 MachineBasicBlock *BB, unsigned Size) const;
388 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
389 MachineBasicBlock *BB, unsigned Size) const;
393 #endif // MipsISELLOWERING_H