1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/Target/TargetLowering.h"
30 // Start the numbering from where ISD NodeType finishes.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Jump and link (call)
39 // Get the Higher 16 bits from a 32-bit immediate
40 // No relation with Mips Hi register
43 // Get the Lower 16 bits from a 32-bit immediate
44 // No relation with Mips Lo register
47 // Handle gp_rel (small data/bss sections) relocation.
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // Floating Point Rounding
71 // Node used to extract integer from accumulator.
74 // Node used to insert integers to accumulator.
105 // EXTR.W instrinsic nodes.
115 // DPA.W intrinsic nodes.
151 // Load/Store Left/Right nodes.
152 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
163 //===--------------------------------------------------------------------===//
164 // TargetLowering Implementation
165 //===--------------------------------------------------------------------===//
166 class MipsFunctionInfo;
168 class MipsTargetLowering : public TargetLowering {
170 explicit MipsTargetLowering(MipsTargetMachine &TM);
172 static const MipsTargetLowering *create(MipsTargetMachine &TM);
174 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
176 virtual void LowerOperationWrapper(SDNode *N,
177 SmallVectorImpl<SDValue> &Results,
178 SelectionDAG &DAG) const;
180 /// LowerOperation - Provide custom lowering hooks for some operations.
181 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
183 /// ReplaceNodeResults - Replace the results of node with an illegal result
184 /// type with new values built out of custom code.
186 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
187 SelectionDAG &DAG) const;
189 /// getTargetNodeName - This method returns the name of a target specific
191 virtual const char *getTargetNodeName(unsigned Opcode) const;
193 /// getSetCCResultType - get the ISD::SETCC result ValueType
194 EVT getSetCCResultType(EVT VT) const;
196 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
198 virtual MachineBasicBlock *
199 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
202 bool operator()(const char *S1, const char *S2) const {
203 return strcmp(S1, S2) < 0;
208 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
210 SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
212 SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
214 SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
215 unsigned HiFlag, unsigned LoFlag) const;
217 /// This function fills Ops, which is the list of operands that will later
218 /// be used when a function call node is created. It also generates
219 /// copyToReg nodes to set up argument registers.
221 getOpndList(SmallVectorImpl<SDValue> &Ops,
222 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
223 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
224 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
226 /// ByValArgInfo - Byval argument information.
227 struct ByValArgInfo {
228 unsigned FirstIdx; // Index of the first register used.
229 unsigned NumRegs; // Number of registers used for this argument.
230 unsigned Address; // Offset of the stack area used to pass this argument.
232 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
235 /// MipsCC - This class provides methods used to analyze formal and call
236 /// arguments and inquire about calling convention information.
239 MipsCC(CallingConv::ID CallConv, bool IsO32, CCState &Info);
241 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
242 bool IsVarArg, bool IsSoftFloat,
243 const SDNode *CallNode,
244 std::vector<ArgListEntry> &FuncArgs);
245 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
247 Function::const_arg_iterator FuncArg);
249 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
250 bool IsSoftFloat, const SDNode *CallNode,
251 const Type *RetTy) const;
253 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
254 bool IsSoftFloat, const Type *RetTy) const;
256 const CCState &getCCInfo() const { return CCInfo; }
258 /// hasByValArg - Returns true if function has byval arguments.
259 bool hasByValArg() const { return !ByValArgs.empty(); }
261 /// regSize - Size (in number of bits) of integer registers.
262 unsigned regSize() const { return IsO32 ? 4 : 8; }
264 /// numIntArgRegs - Number of integer registers available for calls.
265 unsigned numIntArgRegs() const;
267 /// reservedArgArea - The size of the area the caller reserves for
268 /// register arguments. This is 16-byte if ABI is O32.
269 unsigned reservedArgArea() const;
271 /// Return pointer to array of integer argument registers.
272 const uint16_t *intArgRegs() const;
274 typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator;
275 byval_iterator byval_begin() const { return ByValArgs.begin(); }
276 byval_iterator byval_end() const { return ByValArgs.end(); }
279 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
280 CCValAssign::LocInfo LocInfo,
281 ISD::ArgFlagsTy ArgFlags);
283 /// useRegsForByval - Returns true if the calling convention allows the
284 /// use of registers to pass byval arguments.
285 bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
287 /// Return the function that analyzes fixed argument list functions.
288 llvm::CCAssignFn *fixedArgFn() const;
290 /// Return the function that analyzes variable argument list functions.
291 llvm::CCAssignFn *varArgFn() const;
293 const uint16_t *shadowRegs() const;
295 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
298 /// Return the type of the register which is used to pass an argument or
299 /// return a value. This function returns f64 if the argument is an i64
300 /// value which has been generated as a result of softening an f128 value.
301 /// Otherwise, it just returns VT.
302 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
303 bool IsSoftFloat) const;
305 template<typename Ty>
306 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
307 const SDNode *CallNode, const Type *RetTy) const;
310 CallingConv::ID CallConv;
312 SmallVector<ByValArgInfo, 2> ByValArgs;
316 const MipsSubtarget *Subtarget;
318 bool HasMips64, IsN64, IsO32;
321 // Lower Operand helpers
322 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
323 CallingConv::ID CallConv, bool isVarArg,
324 const SmallVectorImpl<ISD::InputArg> &Ins,
325 DebugLoc dl, SelectionDAG &DAG,
326 SmallVectorImpl<SDValue> &InVals,
327 const SDNode *CallNode, const Type *RetTy) const;
329 // Lower Operand specifics
330 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
331 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
332 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
333 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
334 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
335 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
336 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
337 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
338 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
339 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
340 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
341 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
342 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
343 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
344 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
345 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
346 SDValue lowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
347 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
348 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
349 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
351 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
352 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
353 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
355 /// isEligibleForTailCallOptimization - Check whether the call is eligible
356 /// for tail call optimization.
358 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
359 unsigned NextStackOffset,
360 const MipsFunctionInfo& FI) const = 0;
362 /// copyByValArg - Copy argument registers which were used to pass a byval
363 /// argument to the stack. Create a stack frame object for the byval
365 void copyByValRegs(SDValue Chain, DebugLoc DL,
366 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
367 const ISD::ArgFlagsTy &Flags,
368 SmallVectorImpl<SDValue> &InVals,
369 const Argument *FuncArg,
370 const MipsCC &CC, const ByValArgInfo &ByVal) const;
372 /// passByValArg - Pass a byval argument in registers or on stack.
373 void passByValArg(SDValue Chain, DebugLoc DL,
374 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
375 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
376 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
377 const MipsCC &CC, const ByValArgInfo &ByVal,
378 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
380 /// writeVarArgRegs - Write variable function arguments passed in registers
381 /// to the stack. Also create a stack frame object for the first variable
383 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
384 SDValue Chain, DebugLoc DL, SelectionDAG &DAG) const;
387 LowerFormalArguments(SDValue Chain,
388 CallingConv::ID CallConv, bool isVarArg,
389 const SmallVectorImpl<ISD::InputArg> &Ins,
390 DebugLoc dl, SelectionDAG &DAG,
391 SmallVectorImpl<SDValue> &InVals) const;
393 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
394 SDValue Arg, DebugLoc DL, bool IsTailCall,
395 SelectionDAG &DAG) const;
398 LowerCall(TargetLowering::CallLoweringInfo &CLI,
399 SmallVectorImpl<SDValue> &InVals) const;
402 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
404 const SmallVectorImpl<ISD::OutputArg> &Outs,
405 LLVMContext &Context) const;
408 LowerReturn(SDValue Chain,
409 CallingConv::ID CallConv, bool isVarArg,
410 const SmallVectorImpl<ISD::OutputArg> &Outs,
411 const SmallVectorImpl<SDValue> &OutVals,
412 DebugLoc dl, SelectionDAG &DAG) const;
414 // Inline asm support
415 ConstraintType getConstraintType(const std::string &Constraint) const;
417 /// Examine constraint string and operand type and determine a weight value.
418 /// The operand object must already have been set up with the operand type.
419 ConstraintWeight getSingleConstraintMatchWeight(
420 AsmOperandInfo &info, const char *constraint) const;
422 std::pair<unsigned, const TargetRegisterClass*>
423 getRegForInlineAsmConstraint(const std::string &Constraint,
426 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
427 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
428 /// true it means one of the asm constraint of the inline asm instruction
429 /// being processed is 'm'.
430 virtual void LowerAsmOperandForConstraint(SDValue Op,
431 std::string &Constraint,
432 std::vector<SDValue> &Ops,
433 SelectionDAG &DAG) const;
435 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
437 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
439 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
441 bool IsMemset, bool ZeroMemset,
443 MachineFunction &MF) const;
445 /// isFPImmLegal - Returns true if the target can instruction select the
446 /// specified FP immediate natively. If false, the legalizer will
447 /// materialize the FP immediate as a load from a constant pool.
448 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
450 virtual unsigned getJumpTableEncoding() const;
452 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
453 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
454 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
455 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
456 bool Nand = false) const;
457 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
458 MachineBasicBlock *BB, unsigned Size) const;
459 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
460 MachineBasicBlock *BB, unsigned Size) const;
463 /// Create MipsTargetLowering objects.
464 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
465 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
468 #endif // MipsISELLOWERING_H