1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
18 #include "MCTargetDesc/MipsBaseInfo.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Target/TargetLowering.h"
31 // Start the numbering from where ISD NodeType finishes.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 // Jump and link (call)
37 // MicroMIPS Jump and link (call)
43 // Get the Higher 16 bits from a 32-bit immediate
44 // No relation with Mips Hi register
47 // Get the Lower 16 bits from a 32-bit immediate
48 // No relation with Mips Lo register
51 // Handle gp_rel (small data/bss sections) relocation.
57 // Floating Point Branch Conditional
60 // Floating Point Compare
63 // Floating Point Conditional Moves
67 // FP-to-int truncation node.
75 // Node used to extract integer from accumulator.
79 // Node used to insert integers to accumulator.
110 // EXTR.W instrinsic nodes.
120 // DPA.W intrinsic nodes.
156 // DSP setcc and select_cc nodes.
160 // Vector comparisons.
161 // These take a vector and return a boolean.
167 // These take a vector and return a vector bitmask.
174 // Element-wise vector max/min.
180 // Vector Shuffle with mask as an operand
181 VSHF, // Generic shuffle
182 SHF, // 4-element set shuffle.
183 ILVEV, // Interleave even elements
184 ILVOD, // Interleave odd elements
185 ILVL, // Interleave left elements
186 ILVR, // Interleave right elements
187 PCKEV, // Pack even elements
188 PCKOD, // Pack odd elements
190 // Combined (XOR (OR $a, $b), -1)
193 // Extended vector element extraction
197 // Load/Store Left/Right nodes.
198 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
209 //===--------------------------------------------------------------------===//
210 // TargetLowering Implementation
211 //===--------------------------------------------------------------------===//
212 class MipsFunctionInfo;
214 class MipsTargetLowering : public TargetLowering {
217 explicit MipsTargetLowering(MipsTargetMachine &TM);
219 static const MipsTargetLowering *create(MipsTargetMachine &TM);
221 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
223 virtual void LowerOperationWrapper(SDNode *N,
224 SmallVectorImpl<SDValue> &Results,
225 SelectionDAG &DAG) const;
227 /// LowerOperation - Provide custom lowering hooks for some operations.
228 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
230 /// ReplaceNodeResults - Replace the results of node with an illegal result
231 /// type with new values built out of custom code.
233 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
234 SelectionDAG &DAG) const;
236 /// getTargetNodeName - This method returns the name of a target specific
238 virtual const char *getTargetNodeName(unsigned Opcode) const;
240 /// getSetCCResultType - get the ISD::SETCC result ValueType
241 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
243 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
245 virtual MachineBasicBlock *
246 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
249 bool operator()(const char *S1, const char *S2) const {
250 return strcmp(S1, S2) < 0;
255 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
257 // This method creates the following nodes, which are necessary for
258 // computing a local symbol's address:
260 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
261 template <class NodeTy>
262 SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
263 bool IsN32OrN64) const {
265 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
266 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
267 getTargetNode(N, Ty, DAG, GOTFlag));
268 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
269 MachinePointerInfo::getGOT(), false, false,
271 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
272 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
273 getTargetNode(N, Ty, DAG, LoFlag));
274 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
277 // This method creates the following nodes, which are necessary for
278 // computing a global symbol's address:
280 // (load (wrapper $gp, %got(sym)))
281 template<class NodeTy>
282 SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
283 unsigned Flag, SDValue Chain,
284 const MachinePointerInfo &PtrInfo) const {
286 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
287 getTargetNode(N, Ty, DAG, Flag));
288 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
291 // This method creates the following nodes, which are necessary for
292 // computing a global symbol's address in large-GOT mode:
294 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
295 template<class NodeTy>
296 SDValue getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG,
297 unsigned HiFlag, unsigned LoFlag,
299 const MachinePointerInfo &PtrInfo) const {
301 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty,
302 getTargetNode(N, Ty, DAG, HiFlag));
303 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
304 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
305 getTargetNode(N, Ty, DAG, LoFlag));
306 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
310 // This method creates the following nodes, which are necessary for
311 // computing a symbol's address in non-PIC mode:
313 // (add %hi(sym), %lo(sym))
314 template<class NodeTy>
315 SDValue getAddrNonPIC(NodeTy *N, EVT Ty, SelectionDAG &DAG) const {
317 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
318 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
319 return DAG.getNode(ISD::ADD, DL, Ty,
320 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
321 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
324 /// This function fills Ops, which is the list of operands that will later
325 /// be used when a function call node is created. It also generates
326 /// copyToReg nodes to set up argument registers.
328 getOpndList(SmallVectorImpl<SDValue> &Ops,
329 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
330 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
331 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
333 /// ByValArgInfo - Byval argument information.
334 struct ByValArgInfo {
335 unsigned FirstIdx; // Index of the first register used.
336 unsigned NumRegs; // Number of registers used for this argument.
337 unsigned Address; // Offset of the stack area used to pass this argument.
339 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
342 /// MipsCC - This class provides methods used to analyze formal and call
343 /// arguments and inquire about calling convention information.
346 enum SpecialCallingConvType {
347 Mips16RetHelperConv, NoSpecialCallingConv
350 MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
351 SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
354 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
355 bool IsVarArg, bool IsSoftFloat,
356 const SDNode *CallNode,
357 std::vector<ArgListEntry> &FuncArgs);
358 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
360 Function::const_arg_iterator FuncArg);
362 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
363 bool IsSoftFloat, const SDNode *CallNode,
364 const Type *RetTy) const;
366 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
367 bool IsSoftFloat, const Type *RetTy) const;
369 const CCState &getCCInfo() const { return CCInfo; }
371 /// hasByValArg - Returns true if function has byval arguments.
372 bool hasByValArg() const { return !ByValArgs.empty(); }
374 /// regSize - Size (in number of bits) of integer registers.
375 unsigned regSize() const { return IsO32 ? 4 : 8; }
377 /// numIntArgRegs - Number of integer registers available for calls.
378 unsigned numIntArgRegs() const;
380 /// reservedArgArea - The size of the area the caller reserves for
381 /// register arguments. This is 16-byte if ABI is O32.
382 unsigned reservedArgArea() const;
384 /// Return pointer to array of integer argument registers.
385 const uint16_t *intArgRegs() const;
387 typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
388 byval_iterator byval_begin() const { return ByValArgs.begin(); }
389 byval_iterator byval_end() const { return ByValArgs.end(); }
392 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
393 CCValAssign::LocInfo LocInfo,
394 ISD::ArgFlagsTy ArgFlags);
396 /// useRegsForByval - Returns true if the calling convention allows the
397 /// use of registers to pass byval arguments.
398 bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
400 /// Return the function that analyzes fixed argument list functions.
401 llvm::CCAssignFn *fixedArgFn() const;
403 /// Return the function that analyzes variable argument list functions.
404 llvm::CCAssignFn *varArgFn() const;
406 const uint16_t *shadowRegs() const;
408 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
411 /// Return the type of the register which is used to pass an argument or
412 /// return a value. This function returns f64 if the argument is an i64
413 /// value which has been generated as a result of softening an f128 value.
414 /// Otherwise, it just returns VT.
415 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
416 bool IsSoftFloat) const;
418 template<typename Ty>
419 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
420 const SDNode *CallNode, const Type *RetTy) const;
423 CallingConv::ID CallConv;
425 SpecialCallingConvType SpecialCallingConv;
426 SmallVector<ByValArgInfo, 2> ByValArgs;
429 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
430 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
433 const MipsSubtarget *Subtarget;
435 bool hasMips64() const { return Subtarget->hasMips64(); }
436 bool isO32() const { return Subtarget->isABI_O32(); }
437 bool isN32() const { return Subtarget->isABI_N32(); }
438 bool isN64() const { return Subtarget->isABI_N64(); }
441 // Create a TargetGlobalAddress node.
442 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
443 unsigned Flag) const;
445 // Create a TargetExternalSymbol node.
446 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
447 unsigned Flag) const;
449 // Create a TargetBlockAddress node.
450 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
451 unsigned Flag) const;
453 // Create a TargetJumpTable node.
454 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
455 unsigned Flag) const;
457 // Create a TargetConstantPool node.
458 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
459 unsigned Flag) const;
461 MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
462 // Lower Operand helpers
463 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
464 CallingConv::ID CallConv, bool isVarArg,
465 const SmallVectorImpl<ISD::InputArg> &Ins,
466 SDLoc dl, SelectionDAG &DAG,
467 SmallVectorImpl<SDValue> &InVals,
468 const SDNode *CallNode, const Type *RetTy) const;
470 // Lower Operand specifics
471 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
472 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
473 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
474 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
475 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
476 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
477 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
478 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
479 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
480 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
481 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
482 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
483 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
484 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
485 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
486 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
487 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
488 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
489 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
491 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
492 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
494 /// isEligibleForTailCallOptimization - Check whether the call is eligible
495 /// for tail call optimization.
497 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
498 unsigned NextStackOffset,
499 const MipsFunctionInfo& FI) const = 0;
501 /// copyByValArg - Copy argument registers which were used to pass a byval
502 /// argument to the stack. Create a stack frame object for the byval
504 void copyByValRegs(SDValue Chain, SDLoc DL,
505 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
506 const ISD::ArgFlagsTy &Flags,
507 SmallVectorImpl<SDValue> &InVals,
508 const Argument *FuncArg,
509 const MipsCC &CC, const ByValArgInfo &ByVal) const;
511 /// passByValArg - Pass a byval argument in registers or on stack.
512 void passByValArg(SDValue Chain, SDLoc DL,
513 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
514 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
515 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
516 const MipsCC &CC, const ByValArgInfo &ByVal,
517 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
519 /// writeVarArgRegs - Write variable function arguments passed in registers
520 /// to the stack. Also create a stack frame object for the first variable
522 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
523 SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
526 LowerFormalArguments(SDValue Chain,
527 CallingConv::ID CallConv, bool isVarArg,
528 const SmallVectorImpl<ISD::InputArg> &Ins,
529 SDLoc dl, SelectionDAG &DAG,
530 SmallVectorImpl<SDValue> &InVals) const;
532 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
533 SDValue Arg, SDLoc DL, bool IsTailCall,
534 SelectionDAG &DAG) const;
537 LowerCall(TargetLowering::CallLoweringInfo &CLI,
538 SmallVectorImpl<SDValue> &InVals) const;
541 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
543 const SmallVectorImpl<ISD::OutputArg> &Outs,
544 LLVMContext &Context) const;
547 LowerReturn(SDValue Chain,
548 CallingConv::ID CallConv, bool isVarArg,
549 const SmallVectorImpl<ISD::OutputArg> &Outs,
550 const SmallVectorImpl<SDValue> &OutVals,
551 SDLoc dl, SelectionDAG &DAG) const;
553 // Inline asm support
554 ConstraintType getConstraintType(const std::string &Constraint) const;
556 /// Examine constraint string and operand type and determine a weight value.
557 /// The operand object must already have been set up with the operand type.
558 ConstraintWeight getSingleConstraintMatchWeight(
559 AsmOperandInfo &info, const char *constraint) const;
561 /// This function parses registers that appear in inline-asm constraints.
562 /// It returns pair (0, 0) on failure.
563 std::pair<unsigned, const TargetRegisterClass *>
564 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
566 std::pair<unsigned, const TargetRegisterClass*>
567 getRegForInlineAsmConstraint(const std::string &Constraint,
570 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
571 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
572 /// true it means one of the asm constraint of the inline asm instruction
573 /// being processed is 'm'.
574 virtual void LowerAsmOperandForConstraint(SDValue Op,
575 std::string &Constraint,
576 std::vector<SDValue> &Ops,
577 SelectionDAG &DAG) const;
579 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
581 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
583 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
585 bool IsMemset, bool ZeroMemset,
587 MachineFunction &MF) const;
589 /// isFPImmLegal - Returns true if the target can instruction select the
590 /// specified FP immediate natively. If false, the legalizer will
591 /// materialize the FP immediate as a load from a constant pool.
592 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
594 virtual unsigned getJumpTableEncoding() const;
596 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
597 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
598 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
599 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
600 bool Nand = false) const;
601 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
602 MachineBasicBlock *BB, unsigned Size) const;
603 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
604 MachineBasicBlock *BB, unsigned Size) const;
607 /// Create MipsTargetLowering objects.
608 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
609 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
612 #endif // MipsISELLOWERING_H