1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetLowering.h"
21 #include "MipsSubtarget.h"
26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 // Jump and link (call)
32 // Get the Higher 16 bits from a 32-bit immediate
33 // No relation with Mips Hi register
36 // Get the Lower 16 bits from a 32-bit immediate
37 // No relation with Mips Lo register
40 // Handle gp_rel (small data/bss sections) relocation.
43 // General Dynamic TLS
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // Floating Point Rounding
93 //===--------------------------------------------------------------------===//
94 // TargetLowering Implementation
95 //===--------------------------------------------------------------------===//
97 class MipsTargetLowering : public TargetLowering {
99 explicit MipsTargetLowering(MipsTargetMachine &TM);
101 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
103 virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
105 /// LowerOperation - Provide custom lowering hooks for some operations.
106 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
108 /// getTargetNodeName - This method returns the name of a target specific
110 virtual const char *getTargetNodeName(unsigned Opcode) const;
112 /// getSetCCResultType - get the ISD::SETCC result ValueType
113 EVT getSetCCResultType(EVT VT) const;
115 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
118 const MipsSubtarget *Subtarget;
120 bool HasMips64, IsN64, IsO32;
122 // Lower Operand helpers
123 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
124 CallingConv::ID CallConv, bool isVarArg,
125 const SmallVectorImpl<ISD::InputArg> &Ins,
126 DebugLoc dl, SelectionDAG &DAG,
127 SmallVectorImpl<SDValue> &InVals) const;
129 // Lower Operand specifics
130 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
131 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
133 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
134 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
135 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
136 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
137 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
138 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
139 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
140 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
141 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
142 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
145 LowerFormalArguments(SDValue Chain,
146 CallingConv::ID CallConv, bool isVarArg,
147 const SmallVectorImpl<ISD::InputArg> &Ins,
148 DebugLoc dl, SelectionDAG &DAG,
149 SmallVectorImpl<SDValue> &InVals) const;
152 LowerCall(SDValue Chain, SDValue Callee,
153 CallingConv::ID CallConv, bool isVarArg,
155 const SmallVectorImpl<ISD::OutputArg> &Outs,
156 const SmallVectorImpl<SDValue> &OutVals,
157 const SmallVectorImpl<ISD::InputArg> &Ins,
158 DebugLoc dl, SelectionDAG &DAG,
159 SmallVectorImpl<SDValue> &InVals) const;
162 LowerReturn(SDValue Chain,
163 CallingConv::ID CallConv, bool isVarArg,
164 const SmallVectorImpl<ISD::OutputArg> &Outs,
165 const SmallVectorImpl<SDValue> &OutVals,
166 DebugLoc dl, SelectionDAG &DAG) const;
168 virtual MachineBasicBlock *
169 EmitInstrWithCustomInserter(MachineInstr *MI,
170 MachineBasicBlock *MBB) const;
172 // Inline asm support
173 ConstraintType getConstraintType(const std::string &Constraint) const;
175 /// Examine constraint string and operand type and determine a weight value.
176 /// The operand object must already have been set up with the operand type.
177 ConstraintWeight getSingleConstraintMatchWeight(
178 AsmOperandInfo &info, const char *constraint) const;
180 std::pair<unsigned, const TargetRegisterClass*>
181 getRegForInlineAsmConstraint(const std::string &Constraint,
184 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
186 /// isFPImmLegal - Returns true if the target can instruction select the
187 /// specified FP immediate natively. If false, the legalizer will
188 /// materialize the FP immediate as a load from a constant pool.
189 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
191 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
192 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
193 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
194 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
195 bool Nand = false) const;
196 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
197 MachineBasicBlock *BB, unsigned Size) const;
198 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
199 MachineBasicBlock *BB, unsigned Size) const;
203 #endif // MipsISELLOWERING_H