1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetLowering.h"
21 #include "MipsSubtarget.h"
26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 // Jump and link (call)
32 // Get the Higher 16 bits from a 32-bit immediate
33 // No relation with Mips Hi register
36 // Get the Lower 16 bits from a 32-bit immediate
37 // No relation with Mips Lo register
40 // Handle gp_rel (small data/bss sections) relocation.
46 // Select CC Pseudo Instruction
49 // Floating Point Select CC Pseudo Instruction
52 // Floating Point Branch Conditional
55 // Floating Point Compare
58 // Floating Point Rounding
66 //===--------------------------------------------------------------------===//
67 // TargetLowering Implementation
68 //===--------------------------------------------------------------------===//
70 class MipsTargetLowering : public TargetLowering {
72 explicit MipsTargetLowering(MipsTargetMachine &TM);
74 /// LowerOperation - Provide custom lowering hooks for some operations.
75 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
77 /// getTargetNodeName - This method returns the name of a target specific
79 virtual const char *getTargetNodeName(unsigned Opcode) const;
81 /// getSetCCResultType - get the ISD::SETCC result ValueType
82 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
84 /// getFunctionAlignment - Return the Log2 alignment of this function.
85 virtual unsigned getFunctionAlignment(const Function *F) const;
88 const MipsSubtarget *Subtarget;
91 // Lower Operand helpers
92 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
93 CallingConv::ID CallConv, bool isVarArg,
94 const SmallVectorImpl<ISD::InputArg> &Ins,
95 DebugLoc dl, SelectionDAG &DAG,
96 SmallVectorImpl<SDValue> &InVals) const;
98 // Lower Operand specifics
99 SDValue LowerANDOR(SDValue Op, SelectionDAG &DAG) const;
100 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
101 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
102 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
103 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
104 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
105 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
106 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
107 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
108 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
109 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
112 LowerFormalArguments(SDValue Chain,
113 CallingConv::ID CallConv, bool isVarArg,
114 const SmallVectorImpl<ISD::InputArg> &Ins,
115 DebugLoc dl, SelectionDAG &DAG,
116 SmallVectorImpl<SDValue> &InVals) const;
119 LowerCall(SDValue Chain, SDValue Callee,
120 CallingConv::ID CallConv, bool isVarArg,
122 const SmallVectorImpl<ISD::OutputArg> &Outs,
123 const SmallVectorImpl<ISD::InputArg> &Ins,
124 DebugLoc dl, SelectionDAG &DAG,
125 SmallVectorImpl<SDValue> &InVals) const;
128 LowerReturn(SDValue Chain,
129 CallingConv::ID CallConv, bool isVarArg,
130 const SmallVectorImpl<ISD::OutputArg> &Outs,
131 DebugLoc dl, SelectionDAG &DAG) const;
133 virtual MachineBasicBlock *
134 EmitInstrWithCustomInserter(MachineInstr *MI,
135 MachineBasicBlock *MBB) const;
137 // Inline asm support
138 ConstraintType getConstraintType(const std::string &Constraint) const;
140 std::pair<unsigned, const TargetRegisterClass*>
141 getRegForInlineAsmConstraint(const std::string &Constraint,
144 std::vector<unsigned>
145 getRegClassForInlineAsmConstraint(const std::string &Constraint,
148 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
150 /// isFPImmLegal - Returns true if the target can instruction select the
151 /// specified FP immediate natively. If false, the legalizer will
152 /// materialize the FP immediate as a load from a constant pool.
153 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
157 #endif // MipsISELLOWERING_H