1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetLowering.h"
21 #include "MipsSubtarget.h"
26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 // Jump and link (call)
32 // Get the Higher 16 bits from a 32-bit immediate
33 // No relation with Mips Hi register
36 // Get the Lower 16 bits from a 32-bit immediate
37 // No relation with Mips Lo register
40 // Handle gp_rel (small data/bss sections) relocation.
46 // Floating Point Branch Conditional
49 // Floating Point Compare
52 // Floating Point Conditional Moves
56 // Floating Point Rounding
86 //===--------------------------------------------------------------------===//
87 // TargetLowering Implementation
88 //===--------------------------------------------------------------------===//
90 class MipsTargetLowering : public TargetLowering {
92 explicit MipsTargetLowering(MipsTargetMachine &TM);
94 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
96 virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
98 /// LowerOperation - Provide custom lowering hooks for some operations.
99 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
101 /// getTargetNodeName - This method returns the name of a target specific
103 virtual const char *getTargetNodeName(unsigned Opcode) const;
105 /// getSetCCResultType - get the ISD::SETCC result ValueType
106 EVT getSetCCResultType(EVT VT) const;
108 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
111 const MipsSubtarget *Subtarget;
113 bool HasMips64, IsN64, IsO32;
115 // Lower Operand helpers
116 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
117 CallingConv::ID CallConv, bool isVarArg,
118 const SmallVectorImpl<ISD::InputArg> &Ins,
119 DebugLoc dl, SelectionDAG &DAG,
120 SmallVectorImpl<SDValue> &InVals) const;
122 // Lower Operand specifics
123 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
125 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
126 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
127 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
128 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
129 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
130 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
131 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
133 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
134 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
135 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
136 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
139 LowerFormalArguments(SDValue Chain,
140 CallingConv::ID CallConv, bool isVarArg,
141 const SmallVectorImpl<ISD::InputArg> &Ins,
142 DebugLoc dl, SelectionDAG &DAG,
143 SmallVectorImpl<SDValue> &InVals) const;
146 LowerCall(SDValue Chain, SDValue Callee,
147 CallingConv::ID CallConv, bool isVarArg,
148 bool doesNotRet, bool &isTailCall,
149 const SmallVectorImpl<ISD::OutputArg> &Outs,
150 const SmallVectorImpl<SDValue> &OutVals,
151 const SmallVectorImpl<ISD::InputArg> &Ins,
152 DebugLoc dl, SelectionDAG &DAG,
153 SmallVectorImpl<SDValue> &InVals) const;
156 LowerReturn(SDValue Chain,
157 CallingConv::ID CallConv, bool isVarArg,
158 const SmallVectorImpl<ISD::OutputArg> &Outs,
159 const SmallVectorImpl<SDValue> &OutVals,
160 DebugLoc dl, SelectionDAG &DAG) const;
162 virtual MachineBasicBlock *
163 EmitInstrWithCustomInserter(MachineInstr *MI,
164 MachineBasicBlock *MBB) const;
166 // Inline asm support
167 ConstraintType getConstraintType(const std::string &Constraint) const;
169 /// Examine constraint string and operand type and determine a weight value.
170 /// The operand object must already have been set up with the operand type.
171 ConstraintWeight getSingleConstraintMatchWeight(
172 AsmOperandInfo &info, const char *constraint) const;
174 std::pair<unsigned, const TargetRegisterClass*>
175 getRegForInlineAsmConstraint(const std::string &Constraint,
178 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
180 /// isFPImmLegal - Returns true if the target can instruction select the
181 /// specified FP immediate natively. If false, the legalizer will
182 /// materialize the FP immediate as a load from a constant pool.
183 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
185 virtual unsigned getJumpTableEncoding() const;
187 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
188 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
189 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
190 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
191 bool Nand = false) const;
192 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
193 MachineBasicBlock *BB, unsigned Size) const;
194 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
195 MachineBasicBlock *BB, unsigned Size) const;
199 #endif // MipsISELLOWERING_H