1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===---------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===---------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetLowering.h"
21 #include "MipsSubtarget.h"
26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 // Jump and link (call)
32 // Get the Higher 16 bits from a 32-bit immediate
33 // No relation with Mips Hi register
36 // Get the Lower 16 bits from a 32-bit immediate
37 // No relation with Mips Lo register
40 // Handle gp_rel (small data/bss sections) relocation.
43 // Floating Point Branch Conditional
46 // Floating Point Compare
49 // Floating Point Conditional Moves
53 // Floating Point Rounding
74 //===-------------------------------------------------------------------===//
75 // TargetLowering Implementation
76 //===-------------------------------------------------------------------===//
78 class MipsTargetLowering : public TargetLowering {
80 explicit MipsTargetLowering(MipsTargetMachine &TM);
82 /// LowerOperation - Provide custom lowering hooks for some operations.
83 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
85 /// getTargetNodeName - This method returns the name of a target specific
87 virtual const char *getTargetNodeName(unsigned Opcode) const;
89 /// getSetCCResultType - get the ISD::SETCC result ValueType
90 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
92 /// getFunctionAlignment - Return the Log2 alignment of this function.
93 virtual unsigned getFunctionAlignment(const Function *F) const;
95 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
98 const MipsSubtarget *Subtarget;
101 // Lower Operand helpers
102 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
103 CallingConv::ID CallConv, bool isVarArg,
104 const SmallVectorImpl<ISD::InputArg> &Ins,
105 DebugLoc dl, SelectionDAG &DAG,
106 SmallVectorImpl<SDValue> &InVals) const;
108 // Lower Operand specifics
109 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
110 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
111 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
112 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
113 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
114 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
115 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
116 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
117 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
118 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
121 LowerFormalArguments(SDValue Chain,
122 CallingConv::ID CallConv, bool isVarArg,
123 const SmallVectorImpl<ISD::InputArg> &Ins,
124 DebugLoc dl, SelectionDAG &DAG,
125 SmallVectorImpl<SDValue> &InVals) const;
128 LowerCall(SDValue Chain, SDValue Callee,
129 CallingConv::ID CallConv, bool isVarArg,
131 const SmallVectorImpl<ISD::OutputArg> &Outs,
132 const SmallVectorImpl<SDValue> &OutVals,
133 const SmallVectorImpl<ISD::InputArg> &Ins,
134 DebugLoc dl, SelectionDAG &DAG,
135 SmallVectorImpl<SDValue> &InVals) const;
138 LowerReturn(SDValue Chain,
139 CallingConv::ID CallConv, bool isVarArg,
140 const SmallVectorImpl<ISD::OutputArg> &Outs,
141 const SmallVectorImpl<SDValue> &OutVals,
142 DebugLoc dl, SelectionDAG &DAG) const;
144 virtual MachineBasicBlock *
145 EmitInstrWithCustomInserter(MachineInstr *MI,
146 MachineBasicBlock *MBB) const;
148 // Inline asm support
149 ConstraintType getConstraintType(const std::string &Constraint) const;
151 /// Examine constraint string and operand type and determine a weight
152 /// value. The operand object must already have been set up with the
154 ConstraintWeight getSingleConstraintMatchWeight(
155 AsmOperandInfo &info, const char *constraint) const;
157 std::pair<unsigned, const TargetRegisterClass*>
158 getRegForInlineAsmConstraint(const std::string &Constraint,
161 std::vector<unsigned>
162 getRegClassForInlineAsmConstraint(const std::string &Constraint,
165 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
167 /// isFPImmLegal - Returns true if the target can instruction select the
168 /// specified FP immediate natively. If false, the legalizer will
169 /// materialize the FP immediate as a load from a constant pool.
170 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
174 #endif // MipsISELLOWERING_H