1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
18 #include "MCTargetDesc/MipsBaseInfo.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/Target/TargetLowering.h"
30 // Start the numbering from where ISD NodeType finishes.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Jump and link (call)
39 // Get the Higher 16 bits from a 32-bit immediate
40 // No relation with Mips Hi register
43 // Get the Lower 16 bits from a 32-bit immediate
44 // No relation with Mips Lo register
47 // Handle gp_rel (small data/bss sections) relocation.
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // FP-to-int truncation node.
71 // Node used to extract integer from accumulator.
75 // Node used to insert integers to accumulator.
106 // EXTR.W instrinsic nodes.
116 // DPA.W intrinsic nodes.
152 // DSP setcc and select_cc nodes.
156 // Vector comparisons.
157 // These take a vector and return a boolean.
163 // These take a vector and return a vector bitmask.
170 // Element-wise vector max/min.
176 // Vector Shuffle with mask as an operand
177 VSHF, // Generic shuffle
178 SHF, // 4-element set shuffle.
179 ILVEV, // Interleave even elements
180 ILVOD, // Interleave odd elements
181 ILVL, // Interleave left elements
182 ILVR, // Interleave right elements
183 PCKEV, // Pack even elements
184 PCKOD, // Pack odd elements
187 INSVE, // Copy element from one vector to another
189 // Combined (XOR (OR $a, $b), -1)
192 // Extended vector element extraction
196 // Load/Store Left/Right nodes.
197 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
208 //===--------------------------------------------------------------------===//
209 // TargetLowering Implementation
210 //===--------------------------------------------------------------------===//
211 class MipsFunctionInfo;
215 class MipsTargetLowering : public TargetLowering {
218 explicit MipsTargetLowering(const MipsTargetMachine &TM,
219 const MipsSubtarget &STI);
221 static const MipsTargetLowering *create(const MipsTargetMachine &TM,
222 const MipsSubtarget &STI);
224 /// createFastISel - This method returns a target specific FastISel object,
225 /// or null if the target does not support "fast" ISel.
226 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
227 const TargetLibraryInfo *libInfo) const override;
229 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
231 void LowerOperationWrapper(SDNode *N,
232 SmallVectorImpl<SDValue> &Results,
233 SelectionDAG &DAG) const override;
235 /// LowerOperation - Provide custom lowering hooks for some operations.
236 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
238 /// ReplaceNodeResults - Replace the results of node with an illegal result
239 /// type with new values built out of custom code.
241 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
242 SelectionDAG &DAG) const override;
244 /// getTargetNodeName - This method returns the name of a target specific
246 const char *getTargetNodeName(unsigned Opcode) const override;
248 /// getSetCCResultType - get the ISD::SETCC result ValueType
249 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
251 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
254 EmitInstrWithCustomInserter(MachineInstr *MI,
255 MachineBasicBlock *MBB) const override;
258 bool operator()(const char *S1, const char *S2) const {
259 return strcmp(S1, S2) < 0;
263 void HandleByVal(CCState *, unsigned &, unsigned) const override;
265 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
268 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
270 // This method creates the following nodes, which are necessary for
271 // computing a local symbol's address:
273 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
274 template <class NodeTy>
275 SDValue getAddrLocal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG,
276 bool IsN32OrN64) const {
277 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
278 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
279 getTargetNode(N, Ty, DAG, GOTFlag));
280 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
281 MachinePointerInfo::getGOT(), false, false,
283 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
284 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
285 getTargetNode(N, Ty, DAG, LoFlag));
286 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
289 // This method creates the following nodes, which are necessary for
290 // computing a global symbol's address:
292 // (load (wrapper $gp, %got(sym)))
293 template <class NodeTy>
294 SDValue getAddrGlobal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG,
295 unsigned Flag, SDValue Chain,
296 const MachinePointerInfo &PtrInfo) const {
297 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
298 getTargetNode(N, Ty, DAG, Flag));
299 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
302 // This method creates the following nodes, which are necessary for
303 // computing a global symbol's address in large-GOT mode:
305 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
306 template <class NodeTy>
307 SDValue getAddrGlobalLargeGOT(NodeTy *N, SDLoc DL, EVT Ty,
308 SelectionDAG &DAG, unsigned HiFlag,
309 unsigned LoFlag, SDValue Chain,
310 const MachinePointerInfo &PtrInfo) const {
312 DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(N, Ty, DAG, HiFlag));
313 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
314 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
315 getTargetNode(N, Ty, DAG, LoFlag));
316 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
320 // This method creates the following nodes, which are necessary for
321 // computing a symbol's address in non-PIC mode:
323 // (add %hi(sym), %lo(sym))
324 template <class NodeTy>
325 SDValue getAddrNonPIC(NodeTy *N, SDLoc DL, EVT Ty,
326 SelectionDAG &DAG) const {
327 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
328 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
329 return DAG.getNode(ISD::ADD, DL, Ty,
330 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
331 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
334 // This method creates the following nodes, which are necessary for
335 // computing a symbol's address using gp-relative addressing:
337 // (add $gp, %gp_rel(sym))
338 template <class NodeTy>
339 SDValue getAddrGPRel(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) const {
340 assert(Ty == MVT::i32);
341 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
342 return DAG.getNode(ISD::ADD, DL, Ty,
343 DAG.getRegister(Mips::GP, Ty),
344 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty),
348 /// This function fills Ops, which is the list of operands that will later
349 /// be used when a function call node is created. It also generates
350 /// copyToReg nodes to set up argument registers.
352 getOpndList(SmallVectorImpl<SDValue> &Ops,
353 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
354 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
355 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
356 SDValue Chain) const;
359 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
360 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
363 const MipsSubtarget &Subtarget;
366 // Create a TargetGlobalAddress node.
367 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
368 unsigned Flag) const;
370 // Create a TargetExternalSymbol node.
371 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
372 unsigned Flag) const;
374 // Create a TargetBlockAddress node.
375 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
376 unsigned Flag) const;
378 // Create a TargetJumpTable node.
379 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
380 unsigned Flag) const;
382 // Create a TargetConstantPool node.
383 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
384 unsigned Flag) const;
386 // Lower Operand helpers
387 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
388 CallingConv::ID CallConv, bool isVarArg,
389 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
390 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
391 TargetLowering::CallLoweringInfo &CLI) const;
393 // Lower Operand specifics
394 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
395 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
396 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
397 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
398 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
399 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
400 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
401 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
402 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
403 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
404 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
405 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
406 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
407 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
408 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
409 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
410 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
411 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
412 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
413 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
415 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
416 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
418 /// isEligibleForTailCallOptimization - Check whether the call is eligible
419 /// for tail call optimization.
421 isEligibleForTailCallOptimization(const CCState &CCInfo,
422 unsigned NextStackOffset,
423 const MipsFunctionInfo &FI) const = 0;
425 /// copyByValArg - Copy argument registers which were used to pass a byval
426 /// argument to the stack. Create a stack frame object for the byval
428 void copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
429 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
430 SmallVectorImpl<SDValue> &InVals,
431 const Argument *FuncArg, unsigned FirstReg,
432 unsigned LastReg, const CCValAssign &VA,
433 MipsCCState &State) const;
435 /// passByValArg - Pass a byval argument in registers or on stack.
436 void passByValArg(SDValue Chain, SDLoc DL,
437 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
438 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
439 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
440 unsigned FirstReg, unsigned LastReg,
441 const ISD::ArgFlagsTy &Flags, bool isLittle,
442 const CCValAssign &VA) const;
444 /// writeVarArgRegs - Write variable function arguments passed in registers
445 /// to the stack. Also create a stack frame object for the first variable
447 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
448 SDLoc DL, SelectionDAG &DAG, CCState &State) const;
451 LowerFormalArguments(SDValue Chain,
452 CallingConv::ID CallConv, bool isVarArg,
453 const SmallVectorImpl<ISD::InputArg> &Ins,
454 SDLoc dl, SelectionDAG &DAG,
455 SmallVectorImpl<SDValue> &InVals) const override;
457 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
458 SDValue Arg, SDLoc DL, bool IsTailCall,
459 SelectionDAG &DAG) const;
461 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
462 SmallVectorImpl<SDValue> &InVals) const override;
464 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
466 const SmallVectorImpl<ISD::OutputArg> &Outs,
467 LLVMContext &Context) const override;
469 SDValue LowerReturn(SDValue Chain,
470 CallingConv::ID CallConv, bool isVarArg,
471 const SmallVectorImpl<ISD::OutputArg> &Outs,
472 const SmallVectorImpl<SDValue> &OutVals,
473 SDLoc dl, SelectionDAG &DAG) const override;
475 // Inline asm support
477 getConstraintType(const std::string &Constraint) const override;
479 /// Examine constraint string and operand type and determine a weight value.
480 /// The operand object must already have been set up with the operand type.
481 ConstraintWeight getSingleConstraintMatchWeight(
482 AsmOperandInfo &info, const char *constraint) const override;
484 /// This function parses registers that appear in inline-asm constraints.
485 /// It returns pair (0, 0) on failure.
486 std::pair<unsigned, const TargetRegisterClass *>
487 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
489 std::pair<unsigned, const TargetRegisterClass*>
490 getRegForInlineAsmConstraint(const std::string &Constraint,
491 MVT VT) const override;
493 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
494 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
495 /// true it means one of the asm constraint of the inline asm instruction
496 /// being processed is 'm'.
497 void LowerAsmOperandForConstraint(SDValue Op,
498 std::string &Constraint,
499 std::vector<SDValue> &Ops,
500 SelectionDAG &DAG) const override;
502 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
504 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
506 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
508 bool IsMemset, bool ZeroMemset,
510 MachineFunction &MF) const override;
512 /// isFPImmLegal - Returns true if the target can instruction select the
513 /// specified FP immediate natively. If false, the legalizer will
514 /// materialize the FP immediate as a load from a constant pool.
515 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
517 unsigned getJumpTableEncoding() const override;
519 /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
520 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI,
521 MachineBasicBlock *BB,
522 unsigned Size, unsigned DstReg,
523 unsigned SrcRec) const;
525 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
526 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
527 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
528 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
529 bool Nand = false) const;
530 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
531 MachineBasicBlock *BB, unsigned Size) const;
532 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
533 MachineBasicBlock *BB, unsigned Size) const;
534 MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const;
535 MachineBasicBlock *emitPseudoSELECT(MachineInstr *MI,
536 MachineBasicBlock *BB, bool isFPCmp,
540 /// Create MipsTargetLowering objects.
541 const MipsTargetLowering *
542 createMips16TargetLowering(const MipsTargetMachine &TM,
543 const MipsSubtarget &STI);
544 const MipsTargetLowering *
545 createMipsSETargetLowering(const MipsTargetMachine &TM,
546 const MipsSubtarget &STI);
549 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
550 const TargetLibraryInfo *libInfo);