1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
18 #include "MCTargetDesc/MipsBaseInfo.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/Target/TargetLowering.h"
30 // Start the numbering from where ISD NodeType finishes.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Jump and link (call)
39 // Get the Higher 16 bits from a 32-bit immediate
40 // No relation with Mips Hi register
43 // Get the Lower 16 bits from a 32-bit immediate
44 // No relation with Mips Lo register
47 // Handle gp_rel (small data/bss sections) relocation.
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // FP-to-int truncation node.
71 // Node used to extract integer from accumulator.
75 // Node used to insert integers to accumulator.
106 // EXTR.W instrinsic nodes.
116 // DPA.W intrinsic nodes.
152 // DSP setcc and select_cc nodes.
156 // Vector comparisons.
157 // These take a vector and return a boolean.
163 // These take a vector and return a vector bitmask.
170 // Element-wise vector max/min.
176 // Vector Shuffle with mask as an operand
177 VSHF, // Generic shuffle
178 SHF, // 4-element set shuffle.
179 ILVEV, // Interleave even elements
180 ILVOD, // Interleave odd elements
181 ILVL, // Interleave left elements
182 ILVR, // Interleave right elements
183 PCKEV, // Pack even elements
184 PCKOD, // Pack odd elements
187 INSVE, // Copy element from one vector to another
189 // Combined (XOR (OR $a, $b), -1)
192 // Extended vector element extraction
196 // Load/Store Left/Right nodes.
197 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
208 //===--------------------------------------------------------------------===//
209 // TargetLowering Implementation
210 //===--------------------------------------------------------------------===//
211 class MipsFunctionInfo;
215 class MipsTargetLowering : public TargetLowering {
218 explicit MipsTargetLowering(const MipsTargetMachine &TM,
219 const MipsSubtarget &STI);
221 static const MipsTargetLowering *create(const MipsTargetMachine &TM,
222 const MipsSubtarget &STI);
224 /// createFastISel - This method returns a target specific FastISel object,
225 /// or null if the target does not support "fast" ISel.
226 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
227 const TargetLibraryInfo *libInfo) const override;
229 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
231 void LowerOperationWrapper(SDNode *N,
232 SmallVectorImpl<SDValue> &Results,
233 SelectionDAG &DAG) const override;
235 /// LowerOperation - Provide custom lowering hooks for some operations.
236 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
238 /// ReplaceNodeResults - Replace the results of node with an illegal result
239 /// type with new values built out of custom code.
241 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
242 SelectionDAG &DAG) const override;
244 /// getTargetNodeName - This method returns the name of a target specific
246 const char *getTargetNodeName(unsigned Opcode) const override;
248 /// getSetCCResultType - get the ISD::SETCC result ValueType
249 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
251 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
254 EmitInstrWithCustomInserter(MachineInstr *MI,
255 MachineBasicBlock *MBB) const override;
258 bool operator()(const char *S1, const char *S2) const {
259 return strcmp(S1, S2) < 0;
263 void HandleByVal(CCState *, unsigned &, unsigned) const override;
266 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
268 // This method creates the following nodes, which are necessary for
269 // computing a local symbol's address:
271 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
272 template <class NodeTy>
273 SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
274 bool IsN32OrN64) const {
276 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
277 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
278 getTargetNode(N, Ty, DAG, GOTFlag));
279 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
280 MachinePointerInfo::getGOT(), false, false,
282 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
283 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
284 getTargetNode(N, Ty, DAG, LoFlag));
285 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
288 // This method creates the following nodes, which are necessary for
289 // computing a global symbol's address:
291 // (load (wrapper $gp, %got(sym)))
292 template<class NodeTy>
293 SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
294 unsigned Flag, SDValue Chain,
295 const MachinePointerInfo &PtrInfo) const {
297 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
298 getTargetNode(N, Ty, DAG, Flag));
299 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
302 // This method creates the following nodes, which are necessary for
303 // computing a global symbol's address in large-GOT mode:
305 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
306 template<class NodeTy>
307 SDValue getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG,
308 unsigned HiFlag, unsigned LoFlag,
310 const MachinePointerInfo &PtrInfo) const {
312 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty,
313 getTargetNode(N, Ty, DAG, HiFlag));
314 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
315 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
316 getTargetNode(N, Ty, DAG, LoFlag));
317 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
321 // This method creates the following nodes, which are necessary for
322 // computing a symbol's address in non-PIC mode:
324 // (add %hi(sym), %lo(sym))
325 template<class NodeTy>
326 SDValue getAddrNonPIC(NodeTy *N, EVT Ty, SelectionDAG &DAG) const {
328 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
329 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
330 return DAG.getNode(ISD::ADD, DL, Ty,
331 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
332 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
335 // This method creates the following nodes, which are necessary for
336 // computing a symbol's address using gp-relative addressing:
338 // (add $gp, %gp_rel(sym))
339 template<class NodeTy>
340 SDValue getAddrGPRel(NodeTy *N, EVT Ty, SelectionDAG &DAG) const {
342 assert(Ty == MVT::i32);
343 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
344 return DAG.getNode(ISD::ADD, DL, Ty,
345 DAG.getRegister(Mips::GP, Ty),
346 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty),
350 /// This function fills Ops, which is the list of operands that will later
351 /// be used when a function call node is created. It also generates
352 /// copyToReg nodes to set up argument registers.
354 getOpndList(SmallVectorImpl<SDValue> &Ops,
355 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
356 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
357 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
358 SDValue Chain) const;
361 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
362 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
365 const MipsSubtarget &Subtarget;
368 // Create a TargetGlobalAddress node.
369 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
370 unsigned Flag) const;
372 // Create a TargetExternalSymbol node.
373 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
374 unsigned Flag) const;
376 // Create a TargetBlockAddress node.
377 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
378 unsigned Flag) const;
380 // Create a TargetJumpTable node.
381 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
382 unsigned Flag) const;
384 // Create a TargetConstantPool node.
385 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
386 unsigned Flag) const;
388 // Lower Operand helpers
389 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
390 CallingConv::ID CallConv, bool isVarArg,
391 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
392 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
393 TargetLowering::CallLoweringInfo &CLI) const;
395 // Lower Operand specifics
396 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
397 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
398 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
399 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
400 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
401 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
402 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
403 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
404 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
405 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
406 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
407 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
408 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
409 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
410 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
411 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
412 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
413 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
414 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
415 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
417 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
418 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
420 /// isEligibleForTailCallOptimization - Check whether the call is eligible
421 /// for tail call optimization.
423 isEligibleForTailCallOptimization(const CCState &CCInfo,
424 unsigned NextStackOffset,
425 const MipsFunctionInfo &FI) const = 0;
427 /// copyByValArg - Copy argument registers which were used to pass a byval
428 /// argument to the stack. Create a stack frame object for the byval
430 void copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
431 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
432 SmallVectorImpl<SDValue> &InVals,
433 const Argument *FuncArg, unsigned FirstReg,
434 unsigned LastReg, const CCValAssign &VA,
435 MipsCCState &State) const;
437 /// passByValArg - Pass a byval argument in registers or on stack.
438 void passByValArg(SDValue Chain, SDLoc DL,
439 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
440 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
441 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
442 unsigned FirstReg, unsigned LastReg,
443 const ISD::ArgFlagsTy &Flags, bool isLittle,
444 const CCValAssign &VA) const;
446 /// writeVarArgRegs - Write variable function arguments passed in registers
447 /// to the stack. Also create a stack frame object for the first variable
449 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
450 SDLoc DL, SelectionDAG &DAG, CCState &State) const;
453 LowerFormalArguments(SDValue Chain,
454 CallingConv::ID CallConv, bool isVarArg,
455 const SmallVectorImpl<ISD::InputArg> &Ins,
456 SDLoc dl, SelectionDAG &DAG,
457 SmallVectorImpl<SDValue> &InVals) const override;
459 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
460 SDValue Arg, SDLoc DL, bool IsTailCall,
461 SelectionDAG &DAG) const;
463 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
464 SmallVectorImpl<SDValue> &InVals) const override;
466 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
468 const SmallVectorImpl<ISD::OutputArg> &Outs,
469 LLVMContext &Context) const override;
471 SDValue LowerReturn(SDValue Chain,
472 CallingConv::ID CallConv, bool isVarArg,
473 const SmallVectorImpl<ISD::OutputArg> &Outs,
474 const SmallVectorImpl<SDValue> &OutVals,
475 SDLoc dl, SelectionDAG &DAG) const override;
477 // Inline asm support
479 getConstraintType(const std::string &Constraint) const override;
481 /// Examine constraint string and operand type and determine a weight value.
482 /// The operand object must already have been set up with the operand type.
483 ConstraintWeight getSingleConstraintMatchWeight(
484 AsmOperandInfo &info, const char *constraint) const override;
486 /// This function parses registers that appear in inline-asm constraints.
487 /// It returns pair (0, 0) on failure.
488 std::pair<unsigned, const TargetRegisterClass *>
489 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
491 std::pair<unsigned, const TargetRegisterClass*>
492 getRegForInlineAsmConstraint(const std::string &Constraint,
493 MVT VT) const override;
495 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
496 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
497 /// true it means one of the asm constraint of the inline asm instruction
498 /// being processed is 'm'.
499 void LowerAsmOperandForConstraint(SDValue Op,
500 std::string &Constraint,
501 std::vector<SDValue> &Ops,
502 SelectionDAG &DAG) const override;
504 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
506 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
508 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
510 bool IsMemset, bool ZeroMemset,
512 MachineFunction &MF) const override;
514 /// isFPImmLegal - Returns true if the target can instruction select the
515 /// specified FP immediate natively. If false, the legalizer will
516 /// materialize the FP immediate as a load from a constant pool.
517 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
519 unsigned getJumpTableEncoding() const override;
521 /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
522 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI,
523 MachineBasicBlock *BB,
524 unsigned Size, unsigned DstReg,
525 unsigned SrcRec) const;
527 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
528 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
529 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
530 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
531 bool Nand = false) const;
532 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
533 MachineBasicBlock *BB, unsigned Size) const;
534 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
535 MachineBasicBlock *BB, unsigned Size) const;
536 MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const;
537 MachineBasicBlock *emitPseudoSELECT(MachineInstr *MI,
538 MachineBasicBlock *BB, bool isFPCmp,
542 /// Create MipsTargetLowering objects.
543 const MipsTargetLowering *
544 createMips16TargetLowering(const MipsTargetMachine &TM,
545 const MipsSubtarget &STI);
546 const MipsTargetLowering *
547 createMipsSETargetLowering(const MipsTargetMachine &TM,
548 const MipsSubtarget &STI);
551 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
552 const TargetLibraryInfo *libInfo);