1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/Target/TargetLowering.h"
30 // Start the numbering from where ISD NodeType finishes.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Jump and link (call)
39 // Get the Higher 16 bits from a 32-bit immediate
40 // No relation with Mips Hi register
43 // Get the Lower 16 bits from a 32-bit immediate
44 // No relation with Mips Lo register
47 // Handle gp_rel (small data/bss sections) relocation.
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // FP-to-int truncation node.
71 // Node used to extract integer from accumulator.
74 // Node used to insert integers to accumulator.
105 // EXTR.W instrinsic nodes.
115 // DPA.W intrinsic nodes.
151 // DSP setcc and select_cc nodes.
155 // Vector comparisons
161 // Load/Store Left/Right nodes.
162 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
173 //===--------------------------------------------------------------------===//
174 // TargetLowering Implementation
175 //===--------------------------------------------------------------------===//
176 class MipsFunctionInfo;
178 class MipsTargetLowering : public TargetLowering {
180 explicit MipsTargetLowering(MipsTargetMachine &TM);
182 static const MipsTargetLowering *create(MipsTargetMachine &TM);
184 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
186 virtual void LowerOperationWrapper(SDNode *N,
187 SmallVectorImpl<SDValue> &Results,
188 SelectionDAG &DAG) const;
190 /// LowerOperation - Provide custom lowering hooks for some operations.
191 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
193 /// ReplaceNodeResults - Replace the results of node with an illegal result
194 /// type with new values built out of custom code.
196 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
197 SelectionDAG &DAG) const;
199 /// getTargetNodeName - This method returns the name of a target specific
201 virtual const char *getTargetNodeName(unsigned Opcode) const;
203 /// getSetCCResultType - get the ISD::SETCC result ValueType
204 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
206 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
208 virtual MachineBasicBlock *
209 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
212 bool operator()(const char *S1, const char *S2) const {
213 return strcmp(S1, S2) < 0;
218 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
220 SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
222 SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
224 SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
225 unsigned HiFlag, unsigned LoFlag) const;
227 /// This function fills Ops, which is the list of operands that will later
228 /// be used when a function call node is created. It also generates
229 /// copyToReg nodes to set up argument registers.
231 getOpndList(SmallVectorImpl<SDValue> &Ops,
232 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
233 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
234 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
236 /// ByValArgInfo - Byval argument information.
237 struct ByValArgInfo {
238 unsigned FirstIdx; // Index of the first register used.
239 unsigned NumRegs; // Number of registers used for this argument.
240 unsigned Address; // Offset of the stack area used to pass this argument.
242 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
245 /// MipsCC - This class provides methods used to analyze formal and call
246 /// arguments and inquire about calling convention information.
249 enum SpecialCallingConvType {
250 Mips16RetHelperConv, NoSpecialCallingConv
253 MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
254 SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
257 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
258 bool IsVarArg, bool IsSoftFloat,
259 const SDNode *CallNode,
260 std::vector<ArgListEntry> &FuncArgs);
261 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
263 Function::const_arg_iterator FuncArg);
265 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
266 bool IsSoftFloat, const SDNode *CallNode,
267 const Type *RetTy) const;
269 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
270 bool IsSoftFloat, const Type *RetTy) const;
272 const CCState &getCCInfo() const { return CCInfo; }
274 /// hasByValArg - Returns true if function has byval arguments.
275 bool hasByValArg() const { return !ByValArgs.empty(); }
277 /// regSize - Size (in number of bits) of integer registers.
278 unsigned regSize() const { return IsO32 ? 4 : 8; }
280 /// numIntArgRegs - Number of integer registers available for calls.
281 unsigned numIntArgRegs() const;
283 /// reservedArgArea - The size of the area the caller reserves for
284 /// register arguments. This is 16-byte if ABI is O32.
285 unsigned reservedArgArea() const;
287 /// Return pointer to array of integer argument registers.
288 const uint16_t *intArgRegs() const;
290 typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
291 byval_iterator byval_begin() const { return ByValArgs.begin(); }
292 byval_iterator byval_end() const { return ByValArgs.end(); }
295 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
296 CCValAssign::LocInfo LocInfo,
297 ISD::ArgFlagsTy ArgFlags);
299 /// useRegsForByval - Returns true if the calling convention allows the
300 /// use of registers to pass byval arguments.
301 bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
303 /// Return the function that analyzes fixed argument list functions.
304 llvm::CCAssignFn *fixedArgFn() const;
306 /// Return the function that analyzes variable argument list functions.
307 llvm::CCAssignFn *varArgFn() const;
309 const uint16_t *shadowRegs() const;
311 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
314 /// Return the type of the register which is used to pass an argument or
315 /// return a value. This function returns f64 if the argument is an i64
316 /// value which has been generated as a result of softening an f128 value.
317 /// Otherwise, it just returns VT.
318 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
319 bool IsSoftFloat) const;
321 template<typename Ty>
322 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
323 const SDNode *CallNode, const Type *RetTy) const;
326 CallingConv::ID CallConv;
328 SpecialCallingConvType SpecialCallingConv;
329 SmallVector<ByValArgInfo, 2> ByValArgs;
332 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
333 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
336 const MipsSubtarget *Subtarget;
338 bool HasMips64, IsN64, IsO32;
342 MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
343 // Lower Operand helpers
344 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
345 CallingConv::ID CallConv, bool isVarArg,
346 const SmallVectorImpl<ISD::InputArg> &Ins,
347 SDLoc dl, SelectionDAG &DAG,
348 SmallVectorImpl<SDValue> &InVals,
349 const SDNode *CallNode, const Type *RetTy) const;
351 // Lower Operand specifics
352 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
353 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
354 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
355 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
356 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
357 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
358 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
359 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
360 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
361 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
362 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
363 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
364 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
365 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
366 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
367 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
368 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
369 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
370 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
372 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
373 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
375 /// isEligibleForTailCallOptimization - Check whether the call is eligible
376 /// for tail call optimization.
378 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
379 unsigned NextStackOffset,
380 const MipsFunctionInfo& FI) const = 0;
382 /// copyByValArg - Copy argument registers which were used to pass a byval
383 /// argument to the stack. Create a stack frame object for the byval
385 void copyByValRegs(SDValue Chain, SDLoc DL,
386 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
387 const ISD::ArgFlagsTy &Flags,
388 SmallVectorImpl<SDValue> &InVals,
389 const Argument *FuncArg,
390 const MipsCC &CC, const ByValArgInfo &ByVal) const;
392 /// passByValArg - Pass a byval argument in registers or on stack.
393 void passByValArg(SDValue Chain, SDLoc DL,
394 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
395 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
396 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
397 const MipsCC &CC, const ByValArgInfo &ByVal,
398 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
400 /// writeVarArgRegs - Write variable function arguments passed in registers
401 /// to the stack. Also create a stack frame object for the first variable
403 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
404 SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
407 LowerFormalArguments(SDValue Chain,
408 CallingConv::ID CallConv, bool isVarArg,
409 const SmallVectorImpl<ISD::InputArg> &Ins,
410 SDLoc dl, SelectionDAG &DAG,
411 SmallVectorImpl<SDValue> &InVals) const;
413 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
414 SDValue Arg, SDLoc DL, bool IsTailCall,
415 SelectionDAG &DAG) const;
418 LowerCall(TargetLowering::CallLoweringInfo &CLI,
419 SmallVectorImpl<SDValue> &InVals) const;
422 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
424 const SmallVectorImpl<ISD::OutputArg> &Outs,
425 LLVMContext &Context) const;
428 LowerReturn(SDValue Chain,
429 CallingConv::ID CallConv, bool isVarArg,
430 const SmallVectorImpl<ISD::OutputArg> &Outs,
431 const SmallVectorImpl<SDValue> &OutVals,
432 SDLoc dl, SelectionDAG &DAG) const;
434 // Inline asm support
435 ConstraintType getConstraintType(const std::string &Constraint) const;
437 /// Examine constraint string and operand type and determine a weight value.
438 /// The operand object must already have been set up with the operand type.
439 ConstraintWeight getSingleConstraintMatchWeight(
440 AsmOperandInfo &info, const char *constraint) const;
442 /// This function parses registers that appear in inline-asm constraints.
443 /// It returns pair (0, 0) on failure.
444 std::pair<unsigned, const TargetRegisterClass *>
445 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
447 std::pair<unsigned, const TargetRegisterClass*>
448 getRegForInlineAsmConstraint(const std::string &Constraint,
451 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
452 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
453 /// true it means one of the asm constraint of the inline asm instruction
454 /// being processed is 'm'.
455 virtual void LowerAsmOperandForConstraint(SDValue Op,
456 std::string &Constraint,
457 std::vector<SDValue> &Ops,
458 SelectionDAG &DAG) const;
460 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
462 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
464 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
466 bool IsMemset, bool ZeroMemset,
468 MachineFunction &MF) const;
470 /// isFPImmLegal - Returns true if the target can instruction select the
471 /// specified FP immediate natively. If false, the legalizer will
472 /// materialize the FP immediate as a load from a constant pool.
473 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
475 virtual unsigned getJumpTableEncoding() const;
477 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
478 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
479 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
480 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
481 bool Nand = false) const;
482 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
483 MachineBasicBlock *BB, unsigned Size) const;
484 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
485 MachineBasicBlock *BB, unsigned Size) const;
488 /// Create MipsTargetLowering objects.
489 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
490 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
493 #endif // MipsISELLOWERING_H