1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/Target/TargetLowering.h"
30 // Start the numbering from where ISD NodeType finishes.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Jump and link (call)
39 // Get the Higher 16 bits from a 32-bit immediate
40 // No relation with Mips Hi register
43 // Get the Lower 16 bits from a 32-bit immediate
44 // No relation with Mips Lo register
47 // Handle gp_rel (small data/bss sections) relocation.
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // Floating Point Rounding
71 // Node used to extract integer from accumulator.
74 // Node used to insert integers to accumulator.
105 // EXTR.W instrinsic nodes.
115 // DPA.W intrinsic nodes.
146 // Load/Store Left/Right nodes.
147 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
158 //===--------------------------------------------------------------------===//
159 // TargetLowering Implementation
160 //===--------------------------------------------------------------------===//
161 class MipsFunctionInfo;
163 class MipsTargetLowering : public TargetLowering {
165 explicit MipsTargetLowering(MipsTargetMachine &TM);
167 static const MipsTargetLowering *create(MipsTargetMachine &TM);
169 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
171 virtual void LowerOperationWrapper(SDNode *N,
172 SmallVectorImpl<SDValue> &Results,
173 SelectionDAG &DAG) const;
175 /// LowerOperation - Provide custom lowering hooks for some operations.
176 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
178 /// ReplaceNodeResults - Replace the results of node with an illegal result
179 /// type with new values built out of custom code.
181 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
182 SelectionDAG &DAG) const;
184 /// getTargetNodeName - This method returns the name of a target specific
186 virtual const char *getTargetNodeName(unsigned Opcode) const;
188 /// getSetCCResultType - get the ISD::SETCC result ValueType
189 EVT getSetCCResultType(EVT VT) const;
191 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
193 virtual MachineBasicBlock *
194 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
197 bool operator()(const char *S1, const char *S2) const {
198 return strcmp(S1, S2) < 0;
203 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
205 SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
207 SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
209 SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
210 unsigned HiFlag, unsigned LoFlag) const;
212 /// This function fills Ops, which is the list of operands that will later
213 /// be used when a function call node is created. It also generates
214 /// copyToReg nodes to set up argument registers.
216 getOpndList(SmallVectorImpl<SDValue> &Ops,
217 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
218 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
219 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
221 /// ByValArgInfo - Byval argument information.
222 struct ByValArgInfo {
223 unsigned FirstIdx; // Index of the first register used.
224 unsigned NumRegs; // Number of registers used for this argument.
225 unsigned Address; // Offset of the stack area used to pass this argument.
227 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
230 /// MipsCC - This class provides methods used to analyze formal and call
231 /// arguments and inquire about calling convention information.
234 MipsCC(CallingConv::ID CallConv, bool IsO32, CCState &Info);
236 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
237 bool IsVarArg, bool IsSoftFloat,
238 const SDNode *CallNode,
239 std::vector<ArgListEntry> &FuncArgs);
240 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
242 Function::const_arg_iterator FuncArg);
244 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
245 bool IsSoftFloat, const SDNode *CallNode,
246 const Type *RetTy) const;
248 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
249 bool IsSoftFloat, const Type *RetTy) const;
251 const CCState &getCCInfo() const { return CCInfo; }
253 /// hasByValArg - Returns true if function has byval arguments.
254 bool hasByValArg() const { return !ByValArgs.empty(); }
256 /// regSize - Size (in number of bits) of integer registers.
257 unsigned regSize() const { return IsO32 ? 4 : 8; }
259 /// numIntArgRegs - Number of integer registers available for calls.
260 unsigned numIntArgRegs() const;
262 /// reservedArgArea - The size of the area the caller reserves for
263 /// register arguments. This is 16-byte if ABI is O32.
264 unsigned reservedArgArea() const;
266 /// Return pointer to array of integer argument registers.
267 const uint16_t *intArgRegs() const;
269 typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator;
270 byval_iterator byval_begin() const { return ByValArgs.begin(); }
271 byval_iterator byval_end() const { return ByValArgs.end(); }
274 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
275 CCValAssign::LocInfo LocInfo,
276 ISD::ArgFlagsTy ArgFlags);
278 /// useRegsForByval - Returns true if the calling convention allows the
279 /// use of registers to pass byval arguments.
280 bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
282 /// Return the function that analyzes fixed argument list functions.
283 llvm::CCAssignFn *fixedArgFn() const;
285 /// Return the function that analyzes variable argument list functions.
286 llvm::CCAssignFn *varArgFn() const;
288 const uint16_t *shadowRegs() const;
290 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
293 /// Return the type of the register which is used to pass an argument or
294 /// return a value. This function returns f64 if the argument is an i64
295 /// value which has been generated as a result of softening an f128 value.
296 /// Otherwise, it just returns VT.
297 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
298 bool IsSoftFloat) const;
300 template<typename Ty>
301 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
302 const SDNode *CallNode, const Type *RetTy) const;
305 CallingConv::ID CallConv;
307 SmallVector<ByValArgInfo, 2> ByValArgs;
311 const MipsSubtarget *Subtarget;
313 bool HasMips64, IsN64, IsO32;
316 // Lower Operand helpers
317 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
318 CallingConv::ID CallConv, bool isVarArg,
319 const SmallVectorImpl<ISD::InputArg> &Ins,
320 DebugLoc dl, SelectionDAG &DAG,
321 SmallVectorImpl<SDValue> &InVals,
322 const SDNode *CallNode, const Type *RetTy) const;
324 // Lower Operand specifics
325 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
326 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
327 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
328 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
329 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
330 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
331 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
332 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
333 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
334 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
335 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
336 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
337 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
338 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
339 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
340 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
341 SDValue lowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
342 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
343 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
344 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
346 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
347 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
348 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
350 /// isEligibleForTailCallOptimization - Check whether the call is eligible
351 /// for tail call optimization.
353 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
354 unsigned NextStackOffset,
355 const MipsFunctionInfo& FI) const = 0;
357 /// copyByValArg - Copy argument registers which were used to pass a byval
358 /// argument to the stack. Create a stack frame object for the byval
360 void copyByValRegs(SDValue Chain, DebugLoc DL,
361 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
362 const ISD::ArgFlagsTy &Flags,
363 SmallVectorImpl<SDValue> &InVals,
364 const Argument *FuncArg,
365 const MipsCC &CC, const ByValArgInfo &ByVal) const;
367 /// passByValArg - Pass a byval argument in registers or on stack.
368 void passByValArg(SDValue Chain, DebugLoc DL,
369 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
370 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
371 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
372 const MipsCC &CC, const ByValArgInfo &ByVal,
373 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
375 /// writeVarArgRegs - Write variable function arguments passed in registers
376 /// to the stack. Also create a stack frame object for the first variable
378 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
379 SDValue Chain, DebugLoc DL, SelectionDAG &DAG) const;
382 LowerFormalArguments(SDValue Chain,
383 CallingConv::ID CallConv, bool isVarArg,
384 const SmallVectorImpl<ISD::InputArg> &Ins,
385 DebugLoc dl, SelectionDAG &DAG,
386 SmallVectorImpl<SDValue> &InVals) const;
388 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
389 SDValue Arg, DebugLoc DL, bool IsTailCall,
390 SelectionDAG &DAG) const;
393 LowerCall(TargetLowering::CallLoweringInfo &CLI,
394 SmallVectorImpl<SDValue> &InVals) const;
397 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
399 const SmallVectorImpl<ISD::OutputArg> &Outs,
400 LLVMContext &Context) const;
403 LowerReturn(SDValue Chain,
404 CallingConv::ID CallConv, bool isVarArg,
405 const SmallVectorImpl<ISD::OutputArg> &Outs,
406 const SmallVectorImpl<SDValue> &OutVals,
407 DebugLoc dl, SelectionDAG &DAG) const;
409 // Inline asm support
410 ConstraintType getConstraintType(const std::string &Constraint) const;
412 /// Examine constraint string and operand type and determine a weight value.
413 /// The operand object must already have been set up with the operand type.
414 ConstraintWeight getSingleConstraintMatchWeight(
415 AsmOperandInfo &info, const char *constraint) const;
417 std::pair<unsigned, const TargetRegisterClass*>
418 getRegForInlineAsmConstraint(const std::string &Constraint,
421 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
422 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
423 /// true it means one of the asm constraint of the inline asm instruction
424 /// being processed is 'm'.
425 virtual void LowerAsmOperandForConstraint(SDValue Op,
426 std::string &Constraint,
427 std::vector<SDValue> &Ops,
428 SelectionDAG &DAG) const;
430 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
432 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
434 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
436 bool IsMemset, bool ZeroMemset,
438 MachineFunction &MF) const;
440 /// isFPImmLegal - Returns true if the target can instruction select the
441 /// specified FP immediate natively. If false, the legalizer will
442 /// materialize the FP immediate as a load from a constant pool.
443 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
445 virtual unsigned getJumpTableEncoding() const;
447 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
448 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
449 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
450 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
451 bool Nand = false) const;
452 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
453 MachineBasicBlock *BB, unsigned Size) const;
454 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
455 MachineBasicBlock *BB, unsigned Size) const;
458 /// Create MipsTargetLowering objects.
459 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
460 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
463 #endif // MipsISELLOWERING_H