1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/Target/TargetLowering.h"
30 // Start the numbering from where ISD NodeType finishes.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Jump and link (call)
39 // Get the Higher 16 bits from a 32-bit immediate
40 // No relation with Mips Hi register
43 // Get the Lower 16 bits from a 32-bit immediate
44 // No relation with Mips Lo register
47 // Handle gp_rel (small data/bss sections) relocation.
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // FP-to-int truncation node.
71 // Node used to extract integer from accumulator.
74 // Node used to insert integers to accumulator.
105 // EXTR.W instrinsic nodes.
115 // DPA.W intrinsic nodes.
151 // DSP setcc and select_cc nodes.
155 // Vector comparisons.
156 // These take a vector and return a boolean.
162 // These take a vector and return a vector bitmask.
169 // Element-wise vector max/min.
175 // Vector Shuffle with mask as an operand
176 VSHF, // Generic shuffle
177 SHF, // 4-element set shuffle.
178 ILVEV, // Interleave even elements
179 ILVOD, // Interleave odd elements
180 ILVL, // Interleave left elements
181 ILVR, // Interleave right elements
182 PCKEV, // Pack even elements
183 PCKOD, // Pack odd elements
185 // Combined (XOR (OR $a, $b), -1)
188 // Extended vector element extraction
192 // Load/Store Left/Right nodes.
193 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
204 //===--------------------------------------------------------------------===//
205 // TargetLowering Implementation
206 //===--------------------------------------------------------------------===//
207 class MipsFunctionInfo;
209 class MipsTargetLowering : public TargetLowering {
211 explicit MipsTargetLowering(MipsTargetMachine &TM);
213 static const MipsTargetLowering *create(MipsTargetMachine &TM);
215 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
217 virtual void LowerOperationWrapper(SDNode *N,
218 SmallVectorImpl<SDValue> &Results,
219 SelectionDAG &DAG) const;
221 /// LowerOperation - Provide custom lowering hooks for some operations.
222 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
224 /// ReplaceNodeResults - Replace the results of node with an illegal result
225 /// type with new values built out of custom code.
227 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
228 SelectionDAG &DAG) const;
230 /// getTargetNodeName - This method returns the name of a target specific
232 virtual const char *getTargetNodeName(unsigned Opcode) const;
234 /// getSetCCResultType - get the ISD::SETCC result ValueType
235 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
237 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
239 virtual MachineBasicBlock *
240 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
243 bool operator()(const char *S1, const char *S2) const {
244 return strcmp(S1, S2) < 0;
249 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
251 template<class NodeTy>
252 SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
253 bool HasMips64) const;
255 template<class NodeTy>
256 SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
257 unsigned Flag) const;
259 template<class NodeTy>
260 SDValue getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG,
261 unsigned HiFlag, unsigned LoFlag) const;
263 /// This function fills Ops, which is the list of operands that will later
264 /// be used when a function call node is created. It also generates
265 /// copyToReg nodes to set up argument registers.
267 getOpndList(SmallVectorImpl<SDValue> &Ops,
268 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
269 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
270 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
272 /// ByValArgInfo - Byval argument information.
273 struct ByValArgInfo {
274 unsigned FirstIdx; // Index of the first register used.
275 unsigned NumRegs; // Number of registers used for this argument.
276 unsigned Address; // Offset of the stack area used to pass this argument.
278 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
281 /// MipsCC - This class provides methods used to analyze formal and call
282 /// arguments and inquire about calling convention information.
285 enum SpecialCallingConvType {
286 Mips16RetHelperConv, NoSpecialCallingConv
289 MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
290 SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
293 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
294 bool IsVarArg, bool IsSoftFloat,
295 const SDNode *CallNode,
296 std::vector<ArgListEntry> &FuncArgs);
297 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
299 Function::const_arg_iterator FuncArg);
301 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
302 bool IsSoftFloat, const SDNode *CallNode,
303 const Type *RetTy) const;
305 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
306 bool IsSoftFloat, const Type *RetTy) const;
308 const CCState &getCCInfo() const { return CCInfo; }
310 /// hasByValArg - Returns true if function has byval arguments.
311 bool hasByValArg() const { return !ByValArgs.empty(); }
313 /// regSize - Size (in number of bits) of integer registers.
314 unsigned regSize() const { return IsO32 ? 4 : 8; }
316 /// numIntArgRegs - Number of integer registers available for calls.
317 unsigned numIntArgRegs() const;
319 /// reservedArgArea - The size of the area the caller reserves for
320 /// register arguments. This is 16-byte if ABI is O32.
321 unsigned reservedArgArea() const;
323 /// Return pointer to array of integer argument registers.
324 const uint16_t *intArgRegs() const;
326 typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
327 byval_iterator byval_begin() const { return ByValArgs.begin(); }
328 byval_iterator byval_end() const { return ByValArgs.end(); }
331 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
332 CCValAssign::LocInfo LocInfo,
333 ISD::ArgFlagsTy ArgFlags);
335 /// useRegsForByval - Returns true if the calling convention allows the
336 /// use of registers to pass byval arguments.
337 bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
339 /// Return the function that analyzes fixed argument list functions.
340 llvm::CCAssignFn *fixedArgFn() const;
342 /// Return the function that analyzes variable argument list functions.
343 llvm::CCAssignFn *varArgFn() const;
345 const uint16_t *shadowRegs() const;
347 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
350 /// Return the type of the register which is used to pass an argument or
351 /// return a value. This function returns f64 if the argument is an i64
352 /// value which has been generated as a result of softening an f128 value.
353 /// Otherwise, it just returns VT.
354 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
355 bool IsSoftFloat) const;
357 template<typename Ty>
358 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
359 const SDNode *CallNode, const Type *RetTy) const;
362 CallingConv::ID CallConv;
364 SpecialCallingConvType SpecialCallingConv;
365 SmallVector<ByValArgInfo, 2> ByValArgs;
368 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
369 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
372 const MipsSubtarget *Subtarget;
374 bool HasMips64, IsN64, IsO32;
378 MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
379 // Lower Operand helpers
380 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
381 CallingConv::ID CallConv, bool isVarArg,
382 const SmallVectorImpl<ISD::InputArg> &Ins,
383 SDLoc dl, SelectionDAG &DAG,
384 SmallVectorImpl<SDValue> &InVals,
385 const SDNode *CallNode, const Type *RetTy) const;
387 // Lower Operand specifics
388 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
389 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
390 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
391 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
392 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
393 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
394 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
395 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
396 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
397 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
398 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
399 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
400 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
401 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
402 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
403 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
404 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
405 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
406 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
408 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
409 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
411 /// isEligibleForTailCallOptimization - Check whether the call is eligible
412 /// for tail call optimization.
414 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
415 unsigned NextStackOffset,
416 const MipsFunctionInfo& FI) const = 0;
418 /// copyByValArg - Copy argument registers which were used to pass a byval
419 /// argument to the stack. Create a stack frame object for the byval
421 void copyByValRegs(SDValue Chain, SDLoc DL,
422 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
423 const ISD::ArgFlagsTy &Flags,
424 SmallVectorImpl<SDValue> &InVals,
425 const Argument *FuncArg,
426 const MipsCC &CC, const ByValArgInfo &ByVal) const;
428 /// passByValArg - Pass a byval argument in registers or on stack.
429 void passByValArg(SDValue Chain, SDLoc DL,
430 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
431 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
432 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
433 const MipsCC &CC, const ByValArgInfo &ByVal,
434 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
436 /// writeVarArgRegs - Write variable function arguments passed in registers
437 /// to the stack. Also create a stack frame object for the first variable
439 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
440 SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
443 LowerFormalArguments(SDValue Chain,
444 CallingConv::ID CallConv, bool isVarArg,
445 const SmallVectorImpl<ISD::InputArg> &Ins,
446 SDLoc dl, SelectionDAG &DAG,
447 SmallVectorImpl<SDValue> &InVals) const;
449 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
450 SDValue Arg, SDLoc DL, bool IsTailCall,
451 SelectionDAG &DAG) const;
454 LowerCall(TargetLowering::CallLoweringInfo &CLI,
455 SmallVectorImpl<SDValue> &InVals) const;
458 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
460 const SmallVectorImpl<ISD::OutputArg> &Outs,
461 LLVMContext &Context) const;
464 LowerReturn(SDValue Chain,
465 CallingConv::ID CallConv, bool isVarArg,
466 const SmallVectorImpl<ISD::OutputArg> &Outs,
467 const SmallVectorImpl<SDValue> &OutVals,
468 SDLoc dl, SelectionDAG &DAG) const;
470 // Inline asm support
471 ConstraintType getConstraintType(const std::string &Constraint) const;
473 /// Examine constraint string and operand type and determine a weight value.
474 /// The operand object must already have been set up with the operand type.
475 ConstraintWeight getSingleConstraintMatchWeight(
476 AsmOperandInfo &info, const char *constraint) const;
478 /// This function parses registers that appear in inline-asm constraints.
479 /// It returns pair (0, 0) on failure.
480 std::pair<unsigned, const TargetRegisterClass *>
481 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
483 std::pair<unsigned, const TargetRegisterClass*>
484 getRegForInlineAsmConstraint(const std::string &Constraint,
487 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
488 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
489 /// true it means one of the asm constraint of the inline asm instruction
490 /// being processed is 'm'.
491 virtual void LowerAsmOperandForConstraint(SDValue Op,
492 std::string &Constraint,
493 std::vector<SDValue> &Ops,
494 SelectionDAG &DAG) const;
496 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
498 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
500 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
502 bool IsMemset, bool ZeroMemset,
504 MachineFunction &MF) const;
506 /// isFPImmLegal - Returns true if the target can instruction select the
507 /// specified FP immediate natively. If false, the legalizer will
508 /// materialize the FP immediate as a load from a constant pool.
509 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
511 virtual unsigned getJumpTableEncoding() const;
513 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
514 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
515 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
516 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
517 bool Nand = false) const;
518 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
519 MachineBasicBlock *BB, unsigned Size) const;
520 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
521 MachineBasicBlock *BB, unsigned Size) const;
524 /// Create MipsTargetLowering objects.
525 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
526 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
529 #endif // MipsISELLOWERING_H