1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/Target/TargetLowering.h"
30 // Start the numbering from where ISD NodeType finishes.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Jump and link (call)
39 // Get the Higher 16 bits from a 32-bit immediate
40 // No relation with Mips Hi register
43 // Get the Lower 16 bits from a 32-bit immediate
44 // No relation with Mips Lo register
47 // Handle gp_rel (small data/bss sections) relocation.
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // FP-to-int truncation node.
71 // Node used to extract integer from accumulator.
74 // Node used to insert integers to accumulator.
105 // EXTR.W instrinsic nodes.
115 // DPA.W intrinsic nodes.
151 // DSP setcc and select_cc nodes.
155 // Vector comparisons.
156 // These take a vector and return a boolean.
162 // These take a vector and return a vector bitmask.
169 // Element-wise vector max/min.
175 // Vector Shuffle with mask as an operand
176 VSHF, // Generic shuffle
177 SHF, // 4-element set shuffle.
179 // Combined (XOR (OR $a, $b), -1)
182 // Extended vector element extraction
186 // Load/Store Left/Right nodes.
187 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
198 //===--------------------------------------------------------------------===//
199 // TargetLowering Implementation
200 //===--------------------------------------------------------------------===//
201 class MipsFunctionInfo;
203 class MipsTargetLowering : public TargetLowering {
205 explicit MipsTargetLowering(MipsTargetMachine &TM);
207 static const MipsTargetLowering *create(MipsTargetMachine &TM);
209 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
211 virtual void LowerOperationWrapper(SDNode *N,
212 SmallVectorImpl<SDValue> &Results,
213 SelectionDAG &DAG) const;
215 /// LowerOperation - Provide custom lowering hooks for some operations.
216 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
218 /// ReplaceNodeResults - Replace the results of node with an illegal result
219 /// type with new values built out of custom code.
221 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
222 SelectionDAG &DAG) const;
224 /// getTargetNodeName - This method returns the name of a target specific
226 virtual const char *getTargetNodeName(unsigned Opcode) const;
228 /// getSetCCResultType - get the ISD::SETCC result ValueType
229 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
231 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
233 virtual MachineBasicBlock *
234 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
237 bool operator()(const char *S1, const char *S2) const {
238 return strcmp(S1, S2) < 0;
243 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
245 SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
247 SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
249 SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
250 unsigned HiFlag, unsigned LoFlag) const;
252 /// This function fills Ops, which is the list of operands that will later
253 /// be used when a function call node is created. It also generates
254 /// copyToReg nodes to set up argument registers.
256 getOpndList(SmallVectorImpl<SDValue> &Ops,
257 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
258 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
259 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
261 /// ByValArgInfo - Byval argument information.
262 struct ByValArgInfo {
263 unsigned FirstIdx; // Index of the first register used.
264 unsigned NumRegs; // Number of registers used for this argument.
265 unsigned Address; // Offset of the stack area used to pass this argument.
267 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
270 /// MipsCC - This class provides methods used to analyze formal and call
271 /// arguments and inquire about calling convention information.
274 enum SpecialCallingConvType {
275 Mips16RetHelperConv, NoSpecialCallingConv
278 MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
279 SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
282 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
283 bool IsVarArg, bool IsSoftFloat,
284 const SDNode *CallNode,
285 std::vector<ArgListEntry> &FuncArgs);
286 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
288 Function::const_arg_iterator FuncArg);
290 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
291 bool IsSoftFloat, const SDNode *CallNode,
292 const Type *RetTy) const;
294 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
295 bool IsSoftFloat, const Type *RetTy) const;
297 const CCState &getCCInfo() const { return CCInfo; }
299 /// hasByValArg - Returns true if function has byval arguments.
300 bool hasByValArg() const { return !ByValArgs.empty(); }
302 /// regSize - Size (in number of bits) of integer registers.
303 unsigned regSize() const { return IsO32 ? 4 : 8; }
305 /// numIntArgRegs - Number of integer registers available for calls.
306 unsigned numIntArgRegs() const;
308 /// reservedArgArea - The size of the area the caller reserves for
309 /// register arguments. This is 16-byte if ABI is O32.
310 unsigned reservedArgArea() const;
312 /// Return pointer to array of integer argument registers.
313 const uint16_t *intArgRegs() const;
315 typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
316 byval_iterator byval_begin() const { return ByValArgs.begin(); }
317 byval_iterator byval_end() const { return ByValArgs.end(); }
320 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
321 CCValAssign::LocInfo LocInfo,
322 ISD::ArgFlagsTy ArgFlags);
324 /// useRegsForByval - Returns true if the calling convention allows the
325 /// use of registers to pass byval arguments.
326 bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
328 /// Return the function that analyzes fixed argument list functions.
329 llvm::CCAssignFn *fixedArgFn() const;
331 /// Return the function that analyzes variable argument list functions.
332 llvm::CCAssignFn *varArgFn() const;
334 const uint16_t *shadowRegs() const;
336 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
339 /// Return the type of the register which is used to pass an argument or
340 /// return a value. This function returns f64 if the argument is an i64
341 /// value which has been generated as a result of softening an f128 value.
342 /// Otherwise, it just returns VT.
343 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
344 bool IsSoftFloat) const;
346 template<typename Ty>
347 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
348 const SDNode *CallNode, const Type *RetTy) const;
351 CallingConv::ID CallConv;
353 SpecialCallingConvType SpecialCallingConv;
354 SmallVector<ByValArgInfo, 2> ByValArgs;
357 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
358 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
361 const MipsSubtarget *Subtarget;
363 bool HasMips64, IsN64, IsO32;
367 MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
368 // Lower Operand helpers
369 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
370 CallingConv::ID CallConv, bool isVarArg,
371 const SmallVectorImpl<ISD::InputArg> &Ins,
372 SDLoc dl, SelectionDAG &DAG,
373 SmallVectorImpl<SDValue> &InVals,
374 const SDNode *CallNode, const Type *RetTy) const;
376 // Lower Operand specifics
377 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
378 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
379 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
380 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
381 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
382 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
383 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
384 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
385 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
386 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
387 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
388 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
389 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
390 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
391 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
392 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
393 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
394 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
395 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
397 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
398 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
400 /// isEligibleForTailCallOptimization - Check whether the call is eligible
401 /// for tail call optimization.
403 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
404 unsigned NextStackOffset,
405 const MipsFunctionInfo& FI) const = 0;
407 /// copyByValArg - Copy argument registers which were used to pass a byval
408 /// argument to the stack. Create a stack frame object for the byval
410 void copyByValRegs(SDValue Chain, SDLoc DL,
411 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
412 const ISD::ArgFlagsTy &Flags,
413 SmallVectorImpl<SDValue> &InVals,
414 const Argument *FuncArg,
415 const MipsCC &CC, const ByValArgInfo &ByVal) const;
417 /// passByValArg - Pass a byval argument in registers or on stack.
418 void passByValArg(SDValue Chain, SDLoc DL,
419 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
420 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
421 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
422 const MipsCC &CC, const ByValArgInfo &ByVal,
423 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
425 /// writeVarArgRegs - Write variable function arguments passed in registers
426 /// to the stack. Also create a stack frame object for the first variable
428 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
429 SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
432 LowerFormalArguments(SDValue Chain,
433 CallingConv::ID CallConv, bool isVarArg,
434 const SmallVectorImpl<ISD::InputArg> &Ins,
435 SDLoc dl, SelectionDAG &DAG,
436 SmallVectorImpl<SDValue> &InVals) const;
438 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
439 SDValue Arg, SDLoc DL, bool IsTailCall,
440 SelectionDAG &DAG) const;
443 LowerCall(TargetLowering::CallLoweringInfo &CLI,
444 SmallVectorImpl<SDValue> &InVals) const;
447 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
449 const SmallVectorImpl<ISD::OutputArg> &Outs,
450 LLVMContext &Context) const;
453 LowerReturn(SDValue Chain,
454 CallingConv::ID CallConv, bool isVarArg,
455 const SmallVectorImpl<ISD::OutputArg> &Outs,
456 const SmallVectorImpl<SDValue> &OutVals,
457 SDLoc dl, SelectionDAG &DAG) const;
459 // Inline asm support
460 ConstraintType getConstraintType(const std::string &Constraint) const;
462 /// Examine constraint string and operand type and determine a weight value.
463 /// The operand object must already have been set up with the operand type.
464 ConstraintWeight getSingleConstraintMatchWeight(
465 AsmOperandInfo &info, const char *constraint) const;
467 /// This function parses registers that appear in inline-asm constraints.
468 /// It returns pair (0, 0) on failure.
469 std::pair<unsigned, const TargetRegisterClass *>
470 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
472 std::pair<unsigned, const TargetRegisterClass*>
473 getRegForInlineAsmConstraint(const std::string &Constraint,
476 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
477 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
478 /// true it means one of the asm constraint of the inline asm instruction
479 /// being processed is 'm'.
480 virtual void LowerAsmOperandForConstraint(SDValue Op,
481 std::string &Constraint,
482 std::vector<SDValue> &Ops,
483 SelectionDAG &DAG) const;
485 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
487 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
489 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
491 bool IsMemset, bool ZeroMemset,
493 MachineFunction &MF) const;
495 /// isFPImmLegal - Returns true if the target can instruction select the
496 /// specified FP immediate natively. If false, the legalizer will
497 /// materialize the FP immediate as a load from a constant pool.
498 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
500 virtual unsigned getJumpTableEncoding() const;
502 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
503 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
504 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
505 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
506 bool Nand = false) const;
507 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
508 MachineBasicBlock *BB, unsigned Size) const;
509 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
510 MachineBasicBlock *BB, unsigned Size) const;
513 /// Create MipsTargetLowering objects.
514 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
515 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
518 #endif // MipsISELLOWERING_H