1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/Target/TargetLowering.h"
30 // Start the numbering from where ISD NodeType finishes.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Jump and link (call)
39 // Get the Higher 16 bits from a 32-bit immediate
40 // No relation with Mips Hi register
43 // Get the Lower 16 bits from a 32-bit immediate
44 // No relation with Mips Lo register
47 // Handle gp_rel (small data/bss sections) relocation.
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // FP-to-int truncation node.
71 // Node used to extract integer from accumulator.
74 // Node used to insert integers to accumulator.
105 // EXTR.W instrinsic nodes.
115 // DPA.W intrinsic nodes.
151 // DSP setcc and select_cc nodes.
155 // Vector comparisons.
156 // These take a vector and return a boolean.
162 // These take a vector and return a vector bitmask.
169 // Special case of BUILD_VECTOR where all elements are the same.
171 // Special case of VSPLAT where the result is v2i64, the operand is
172 // constant, and the operand fits in a signed 10-bits value.
175 // Combined (XOR (OR $a, $b), -1)
178 // Extended vector element extraction
182 // Load/Store Left/Right nodes.
183 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
194 //===--------------------------------------------------------------------===//
195 // TargetLowering Implementation
196 //===--------------------------------------------------------------------===//
197 class MipsFunctionInfo;
199 class MipsTargetLowering : public TargetLowering {
201 explicit MipsTargetLowering(MipsTargetMachine &TM);
203 static const MipsTargetLowering *create(MipsTargetMachine &TM);
205 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
207 virtual void LowerOperationWrapper(SDNode *N,
208 SmallVectorImpl<SDValue> &Results,
209 SelectionDAG &DAG) const;
211 /// LowerOperation - Provide custom lowering hooks for some operations.
212 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
214 /// ReplaceNodeResults - Replace the results of node with an illegal result
215 /// type with new values built out of custom code.
217 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
218 SelectionDAG &DAG) const;
220 /// getTargetNodeName - This method returns the name of a target specific
222 virtual const char *getTargetNodeName(unsigned Opcode) const;
224 /// getSetCCResultType - get the ISD::SETCC result ValueType
225 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
227 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
229 virtual MachineBasicBlock *
230 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
233 bool operator()(const char *S1, const char *S2) const {
234 return strcmp(S1, S2) < 0;
239 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
241 SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
243 SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
245 SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
246 unsigned HiFlag, unsigned LoFlag) const;
248 /// This function fills Ops, which is the list of operands that will later
249 /// be used when a function call node is created. It also generates
250 /// copyToReg nodes to set up argument registers.
252 getOpndList(SmallVectorImpl<SDValue> &Ops,
253 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
254 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
255 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
257 /// ByValArgInfo - Byval argument information.
258 struct ByValArgInfo {
259 unsigned FirstIdx; // Index of the first register used.
260 unsigned NumRegs; // Number of registers used for this argument.
261 unsigned Address; // Offset of the stack area used to pass this argument.
263 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
266 /// MipsCC - This class provides methods used to analyze formal and call
267 /// arguments and inquire about calling convention information.
270 enum SpecialCallingConvType {
271 Mips16RetHelperConv, NoSpecialCallingConv
274 MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
275 SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
278 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
279 bool IsVarArg, bool IsSoftFloat,
280 const SDNode *CallNode,
281 std::vector<ArgListEntry> &FuncArgs);
282 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
284 Function::const_arg_iterator FuncArg);
286 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
287 bool IsSoftFloat, const SDNode *CallNode,
288 const Type *RetTy) const;
290 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
291 bool IsSoftFloat, const Type *RetTy) const;
293 const CCState &getCCInfo() const { return CCInfo; }
295 /// hasByValArg - Returns true if function has byval arguments.
296 bool hasByValArg() const { return !ByValArgs.empty(); }
298 /// regSize - Size (in number of bits) of integer registers.
299 unsigned regSize() const { return IsO32 ? 4 : 8; }
301 /// numIntArgRegs - Number of integer registers available for calls.
302 unsigned numIntArgRegs() const;
304 /// reservedArgArea - The size of the area the caller reserves for
305 /// register arguments. This is 16-byte if ABI is O32.
306 unsigned reservedArgArea() const;
308 /// Return pointer to array of integer argument registers.
309 const uint16_t *intArgRegs() const;
311 typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
312 byval_iterator byval_begin() const { return ByValArgs.begin(); }
313 byval_iterator byval_end() const { return ByValArgs.end(); }
316 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
317 CCValAssign::LocInfo LocInfo,
318 ISD::ArgFlagsTy ArgFlags);
320 /// useRegsForByval - Returns true if the calling convention allows the
321 /// use of registers to pass byval arguments.
322 bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
324 /// Return the function that analyzes fixed argument list functions.
325 llvm::CCAssignFn *fixedArgFn() const;
327 /// Return the function that analyzes variable argument list functions.
328 llvm::CCAssignFn *varArgFn() const;
330 const uint16_t *shadowRegs() const;
332 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
335 /// Return the type of the register which is used to pass an argument or
336 /// return a value. This function returns f64 if the argument is an i64
337 /// value which has been generated as a result of softening an f128 value.
338 /// Otherwise, it just returns VT.
339 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
340 bool IsSoftFloat) const;
342 template<typename Ty>
343 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
344 const SDNode *CallNode, const Type *RetTy) const;
347 CallingConv::ID CallConv;
349 SpecialCallingConvType SpecialCallingConv;
350 SmallVector<ByValArgInfo, 2> ByValArgs;
353 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
354 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
357 const MipsSubtarget *Subtarget;
359 bool HasMips64, IsN64, IsO32;
363 MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
364 // Lower Operand helpers
365 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
366 CallingConv::ID CallConv, bool isVarArg,
367 const SmallVectorImpl<ISD::InputArg> &Ins,
368 SDLoc dl, SelectionDAG &DAG,
369 SmallVectorImpl<SDValue> &InVals,
370 const SDNode *CallNode, const Type *RetTy) const;
372 // Lower Operand specifics
373 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
374 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
375 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
376 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
377 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
378 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
379 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
380 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
381 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
382 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
383 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
384 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
385 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
386 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
387 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
388 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
389 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
390 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
391 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
393 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
394 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
396 /// isEligibleForTailCallOptimization - Check whether the call is eligible
397 /// for tail call optimization.
399 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
400 unsigned NextStackOffset,
401 const MipsFunctionInfo& FI) const = 0;
403 /// copyByValArg - Copy argument registers which were used to pass a byval
404 /// argument to the stack. Create a stack frame object for the byval
406 void copyByValRegs(SDValue Chain, SDLoc DL,
407 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
408 const ISD::ArgFlagsTy &Flags,
409 SmallVectorImpl<SDValue> &InVals,
410 const Argument *FuncArg,
411 const MipsCC &CC, const ByValArgInfo &ByVal) const;
413 /// passByValArg - Pass a byval argument in registers or on stack.
414 void passByValArg(SDValue Chain, SDLoc DL,
415 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
416 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
417 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
418 const MipsCC &CC, const ByValArgInfo &ByVal,
419 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
421 /// writeVarArgRegs - Write variable function arguments passed in registers
422 /// to the stack. Also create a stack frame object for the first variable
424 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
425 SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
428 LowerFormalArguments(SDValue Chain,
429 CallingConv::ID CallConv, bool isVarArg,
430 const SmallVectorImpl<ISD::InputArg> &Ins,
431 SDLoc dl, SelectionDAG &DAG,
432 SmallVectorImpl<SDValue> &InVals) const;
434 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
435 SDValue Arg, SDLoc DL, bool IsTailCall,
436 SelectionDAG &DAG) const;
439 LowerCall(TargetLowering::CallLoweringInfo &CLI,
440 SmallVectorImpl<SDValue> &InVals) const;
443 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
445 const SmallVectorImpl<ISD::OutputArg> &Outs,
446 LLVMContext &Context) const;
449 LowerReturn(SDValue Chain,
450 CallingConv::ID CallConv, bool isVarArg,
451 const SmallVectorImpl<ISD::OutputArg> &Outs,
452 const SmallVectorImpl<SDValue> &OutVals,
453 SDLoc dl, SelectionDAG &DAG) const;
455 // Inline asm support
456 ConstraintType getConstraintType(const std::string &Constraint) const;
458 /// Examine constraint string and operand type and determine a weight value.
459 /// The operand object must already have been set up with the operand type.
460 ConstraintWeight getSingleConstraintMatchWeight(
461 AsmOperandInfo &info, const char *constraint) const;
463 /// This function parses registers that appear in inline-asm constraints.
464 /// It returns pair (0, 0) on failure.
465 std::pair<unsigned, const TargetRegisterClass *>
466 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
468 std::pair<unsigned, const TargetRegisterClass*>
469 getRegForInlineAsmConstraint(const std::string &Constraint,
472 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
473 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
474 /// true it means one of the asm constraint of the inline asm instruction
475 /// being processed is 'm'.
476 virtual void LowerAsmOperandForConstraint(SDValue Op,
477 std::string &Constraint,
478 std::vector<SDValue> &Ops,
479 SelectionDAG &DAG) const;
481 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
483 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
485 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
487 bool IsMemset, bool ZeroMemset,
489 MachineFunction &MF) const;
491 /// isFPImmLegal - Returns true if the target can instruction select the
492 /// specified FP immediate natively. If false, the legalizer will
493 /// materialize the FP immediate as a load from a constant pool.
494 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
496 virtual unsigned getJumpTableEncoding() const;
498 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
499 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
500 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
501 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
502 bool Nand = false) const;
503 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
504 MachineBasicBlock *BB, unsigned Size) const;
505 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
506 MachineBasicBlock *BB, unsigned Size) const;
509 /// Create MipsTargetLowering objects.
510 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
511 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
514 #endif // MipsISELLOWERING_H