1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/Target/TargetLowering.h"
30 // Start the numbering from where ISD NodeType finishes.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Jump and link (call)
39 // Get the Higher 16 bits from a 32-bit immediate
40 // No relation with Mips Hi register
43 // Get the Lower 16 bits from a 32-bit immediate
44 // No relation with Mips Lo register
47 // Handle gp_rel (small data/bss sections) relocation.
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // Floating Point Rounding
93 // EXTR.W instrinsic nodes.
103 // DPA.W intrinsic nodes.
134 // Load/Store Left/Right nodes.
135 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
146 //===--------------------------------------------------------------------===//
147 // TargetLowering Implementation
148 //===--------------------------------------------------------------------===//
149 class MipsFunctionInfo;
151 class MipsTargetLowering : public TargetLowering {
153 explicit MipsTargetLowering(MipsTargetMachine &TM);
155 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
157 virtual bool allowsUnalignedMemoryAccesses (EVT VT, bool *Fast) const;
159 virtual void LowerOperationWrapper(SDNode *N,
160 SmallVectorImpl<SDValue> &Results,
161 SelectionDAG &DAG) const;
163 /// LowerOperation - Provide custom lowering hooks for some operations.
164 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
166 /// ReplaceNodeResults - Replace the results of node with an illegal result
167 /// type with new values built out of custom code.
169 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
170 SelectionDAG &DAG) const;
172 /// getTargetNodeName - This method returns the name of a target specific
174 virtual const char *getTargetNodeName(unsigned Opcode) const;
176 /// getSetCCResultType - get the ISD::SETCC result ValueType
177 EVT getSetCCResultType(EVT VT) const;
179 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
182 void SetMips16LibcallName(RTLIB::Libcall, const char *Name);
184 void setMips16HardFloatLibCalls();
187 getMips16HelperFunctionStubNumber(ArgListTy &Args) const;
189 const char *getMips16HelperFunction
190 (Type* RetTy, ArgListTy &Args, bool &needHelper) const;
192 /// ByValArgInfo - Byval argument information.
193 struct ByValArgInfo {
194 unsigned FirstIdx; // Index of the first register used.
195 unsigned NumRegs; // Number of registers used for this argument.
196 unsigned Address; // Offset of the stack area used to pass this argument.
198 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
201 /// MipsCC - This class provides methods used to analyze formal and call
202 /// arguments and inquire about calling convention information.
205 MipsCC(CallingConv::ID CallConv, bool IsO32, CCState &Info);
207 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
208 bool IsVarArg, bool IsSoftFloat,
209 const SDNode *CallNode,
210 std::vector<ArgListEntry> &FuncArgs);
211 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
213 Function::const_arg_iterator FuncArg);
215 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
216 bool IsSoftFloat, const SDNode *CallNode,
217 const Type *RetTy) const;
219 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
220 bool IsSoftFloat, const Type *RetTy) const;
222 const CCState &getCCInfo() const { return CCInfo; }
224 /// hasByValArg - Returns true if function has byval arguments.
225 bool hasByValArg() const { return !ByValArgs.empty(); }
227 /// regSize - Size (in number of bits) of integer registers.
228 unsigned regSize() const { return IsO32 ? 4 : 8; }
230 /// numIntArgRegs - Number of integer registers available for calls.
231 unsigned numIntArgRegs() const;
233 /// reservedArgArea - The size of the area the caller reserves for
234 /// register arguments. This is 16-byte if ABI is O32.
235 unsigned reservedArgArea() const;
237 /// Return pointer to array of integer argument registers.
238 const uint16_t *intArgRegs() const;
240 typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator;
241 byval_iterator byval_begin() const { return ByValArgs.begin(); }
242 byval_iterator byval_end() const { return ByValArgs.end(); }
245 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
246 CCValAssign::LocInfo LocInfo,
247 ISD::ArgFlagsTy ArgFlags);
249 /// useRegsForByval - Returns true if the calling convention allows the
250 /// use of registers to pass byval arguments.
251 bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
253 /// Return the function that analyzes fixed argument list functions.
254 llvm::CCAssignFn *fixedArgFn() const;
256 /// Return the function that analyzes variable argument list functions.
257 llvm::CCAssignFn *varArgFn() const;
259 const uint16_t *shadowRegs() const;
261 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
264 /// Return the type of the register which is used to pass an argument or
265 /// return a value. This function returns f64 if the argument is an i64
266 /// value which has been generated as a result of softening an f128 value.
267 /// Otherwise, it just returns VT.
268 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
269 bool IsSoftFloat) const;
271 template<typename Ty>
272 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
273 const SDNode *CallNode, const Type *RetTy) const;
276 CallingConv::ID CallConv;
278 SmallVector<ByValArgInfo, 2> ByValArgs;
282 const MipsSubtarget *Subtarget;
284 bool HasMips64, IsN64, IsO32;
286 // Lower Operand helpers
287 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
288 CallingConv::ID CallConv, bool isVarArg,
289 const SmallVectorImpl<ISD::InputArg> &Ins,
290 DebugLoc dl, SelectionDAG &DAG,
291 SmallVectorImpl<SDValue> &InVals,
292 const SDNode *CallNode, const Type *RetTy) const;
294 // Lower Operand specifics
295 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
296 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
297 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
298 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
299 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
300 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
301 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
302 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
303 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
304 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
305 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
306 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
307 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
308 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
309 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
310 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
311 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
312 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
313 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
314 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
316 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
317 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
318 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
319 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
320 SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
322 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
323 /// for tail call optimization.
324 bool IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
325 unsigned NextStackOffset,
326 const MipsFunctionInfo& FI) const;
328 /// copyByValArg - Copy argument registers which were used to pass a byval
329 /// argument to the stack. Create a stack frame object for the byval
331 void copyByValRegs(SDValue Chain, DebugLoc DL,
332 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
333 const ISD::ArgFlagsTy &Flags,
334 SmallVectorImpl<SDValue> &InVals,
335 const Argument *FuncArg,
336 const MipsCC &CC, const ByValArgInfo &ByVal) const;
338 /// passByValArg - Pass a byval argument in registers or on stack.
339 void passByValArg(SDValue Chain, DebugLoc DL,
340 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
341 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
342 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
343 const MipsCC &CC, const ByValArgInfo &ByVal,
344 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
346 /// writeVarArgRegs - Write variable function arguments passed in registers
347 /// to the stack. Also create a stack frame object for the first variable
349 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
350 SDValue Chain, DebugLoc DL, SelectionDAG &DAG) const;
353 LowerFormalArguments(SDValue Chain,
354 CallingConv::ID CallConv, bool isVarArg,
355 const SmallVectorImpl<ISD::InputArg> &Ins,
356 DebugLoc dl, SelectionDAG &DAG,
357 SmallVectorImpl<SDValue> &InVals) const;
359 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
360 SDValue Arg, DebugLoc DL, bool IsTailCall,
361 SelectionDAG &DAG) const;
364 LowerCall(TargetLowering::CallLoweringInfo &CLI,
365 SmallVectorImpl<SDValue> &InVals) const;
368 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
370 const SmallVectorImpl<ISD::OutputArg> &Outs,
371 LLVMContext &Context) const;
374 LowerReturn(SDValue Chain,
375 CallingConv::ID CallConv, bool isVarArg,
376 const SmallVectorImpl<ISD::OutputArg> &Outs,
377 const SmallVectorImpl<SDValue> &OutVals,
378 DebugLoc dl, SelectionDAG &DAG) const;
380 virtual MachineBasicBlock *
381 EmitInstrWithCustomInserter(MachineInstr *MI,
382 MachineBasicBlock *MBB) const;
384 // Inline asm support
385 ConstraintType getConstraintType(const std::string &Constraint) const;
387 /// Examine constraint string and operand type and determine a weight value.
388 /// The operand object must already have been set up with the operand type.
389 ConstraintWeight getSingleConstraintMatchWeight(
390 AsmOperandInfo &info, const char *constraint) const;
392 std::pair<unsigned, const TargetRegisterClass*>
393 getRegForInlineAsmConstraint(const std::string &Constraint,
396 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
397 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
398 /// true it means one of the asm constraint of the inline asm instruction
399 /// being processed is 'm'.
400 virtual void LowerAsmOperandForConstraint(SDValue Op,
401 std::string &Constraint,
402 std::vector<SDValue> &Ops,
403 SelectionDAG &DAG) const;
405 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
407 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
409 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
411 bool IsMemset, bool ZeroMemset,
413 MachineFunction &MF) const;
415 /// isFPImmLegal - Returns true if the target can instruction select the
416 /// specified FP immediate natively. If false, the legalizer will
417 /// materialize the FP immediate as a load from a constant pool.
418 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
420 virtual unsigned getJumpTableEncoding() const;
422 MachineBasicBlock *EmitBPOSGE32(MachineInstr *MI,
423 MachineBasicBlock *BB) const;
424 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
425 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
426 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
427 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
428 bool Nand = false) const;
429 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
430 MachineBasicBlock *BB, unsigned Size) const;
431 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
432 MachineBasicBlock *BB, unsigned Size) const;
433 MachineBasicBlock *EmitSel16(unsigned Opc, MachineInstr *MI,
434 MachineBasicBlock *BB) const;
435 MachineBasicBlock *EmitSeliT16(unsigned Opc1, unsigned Opc2,
437 MachineBasicBlock *BB) const;
439 MachineBasicBlock *EmitSelT16(unsigned Opc1, unsigned Opc2,
441 MachineBasicBlock *BB) const;
442 MachineBasicBlock *EmitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
444 MachineBasicBlock *BB) const;
445 MachineBasicBlock *EmitFEXT_T8I8I16_ins(
446 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc,
447 MachineInstr *MI, MachineBasicBlock *BB) const;
448 MachineBasicBlock *EmitFEXT_CCRX16_ins(
450 MachineInstr *MI, MachineBasicBlock *BB) const;
451 MachineBasicBlock *EmitFEXT_CCRXI16_ins(
452 unsigned SltiOpc, unsigned SltiXOpc,
453 MachineInstr *MI, MachineBasicBlock *BB )const;
458 #endif // MipsISELLOWERING_H