1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetLowering.h"
21 #include "MipsSubtarget.h"
26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 // Jump and link (call)
32 // Get the Higher 16 bits from a 32-bit immediate
33 // No relation with Mips Hi register
36 // Get the Lower 16 bits from a 32-bit immediate
37 // No relation with Mips Lo register
40 // Handle gp_rel (small data/bss sections) relocation.
43 // General Dynamic TLS
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // Floating Point Rounding
93 //===--------------------------------------------------------------------===//
94 // TargetLowering Implementation
95 //===--------------------------------------------------------------------===//
97 class MipsTargetLowering : public TargetLowering {
99 explicit MipsTargetLowering(MipsTargetMachine &TM);
101 virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
103 /// LowerOperation - Provide custom lowering hooks for some operations.
104 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
106 /// getTargetNodeName - This method returns the name of a target specific
108 virtual const char *getTargetNodeName(unsigned Opcode) const;
110 /// getSetCCResultType - get the ISD::SETCC result ValueType
111 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
113 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
116 const MipsSubtarget *Subtarget;
119 // Lower Operand helpers
120 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
121 CallingConv::ID CallConv, bool isVarArg,
122 const SmallVectorImpl<ISD::InputArg> &Ins,
123 DebugLoc dl, SelectionDAG &DAG,
124 SmallVectorImpl<SDValue> &InVals) const;
126 // Lower Operand specifics
127 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
128 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
129 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
130 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
131 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
133 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
134 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
135 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
136 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
137 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
138 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
139 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
140 SDValue LowerAND(SDValue Op, SelectionDAG& DAG) const;
141 SDValue LowerOR(SDValue Op, SelectionDAG& DAG) const;
144 LowerFormalArguments(SDValue Chain,
145 CallingConv::ID CallConv, bool isVarArg,
146 const SmallVectorImpl<ISD::InputArg> &Ins,
147 DebugLoc dl, SelectionDAG &DAG,
148 SmallVectorImpl<SDValue> &InVals) const;
151 LowerCall(SDValue Chain, SDValue Callee,
152 CallingConv::ID CallConv, bool isVarArg,
154 const SmallVectorImpl<ISD::OutputArg> &Outs,
155 const SmallVectorImpl<SDValue> &OutVals,
156 const SmallVectorImpl<ISD::InputArg> &Ins,
157 DebugLoc dl, SelectionDAG &DAG,
158 SmallVectorImpl<SDValue> &InVals) const;
161 LowerReturn(SDValue Chain,
162 CallingConv::ID CallConv, bool isVarArg,
163 const SmallVectorImpl<ISD::OutputArg> &Outs,
164 const SmallVectorImpl<SDValue> &OutVals,
165 DebugLoc dl, SelectionDAG &DAG) const;
167 virtual MachineBasicBlock *
168 EmitInstrWithCustomInserter(MachineInstr *MI,
169 MachineBasicBlock *MBB) const;
171 // Inline asm support
172 ConstraintType getConstraintType(const std::string &Constraint) const;
174 /// Examine constraint string and operand type and determine a weight value.
175 /// The operand object must already have been set up with the operand type.
176 ConstraintWeight getSingleConstraintMatchWeight(
177 AsmOperandInfo &info, const char *constraint) const;
179 std::pair<unsigned, const TargetRegisterClass*>
180 getRegForInlineAsmConstraint(const std::string &Constraint,
183 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
185 /// isFPImmLegal - Returns true if the target can instruction select the
186 /// specified FP immediate natively. If false, the legalizer will
187 /// materialize the FP immediate as a load from a constant pool.
188 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
190 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
191 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
192 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
193 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
194 bool Nand = false) const;
195 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
196 MachineBasicBlock *BB, unsigned Size) const;
197 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
198 MachineBasicBlock *BB, unsigned Size) const;
202 #endif // MipsISELLOWERING_H