1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/Target/TargetLowering.h"
28 // Start the numbering from where ISD NodeType finishes.
29 FIRST_NUMBER = ISD::BUILTIN_OP_END,
31 // Jump and link (call)
37 // Get the Higher 16 bits from a 32-bit immediate
38 // No relation with Mips Hi register
41 // Get the Lower 16 bits from a 32-bit immediate
42 // No relation with Mips Lo register
45 // Handle gp_rel (small data/bss sections) relocation.
51 // Floating Point Branch Conditional
54 // Floating Point Compare
57 // Floating Point Conditional Moves
61 // Floating Point Rounding
89 // EXTR.W instrinsic nodes.
99 // DPA.W intrinsic nodes.
130 // Load/Store Left/Right nodes.
131 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
142 //===--------------------------------------------------------------------===//
143 // TargetLowering Implementation
144 //===--------------------------------------------------------------------===//
145 class MipsFunctionInfo;
147 class MipsTargetLowering : public TargetLowering {
149 explicit MipsTargetLowering(MipsTargetMachine &TM);
151 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
153 virtual bool allowsUnalignedMemoryAccesses (EVT VT, bool *Fast) const;
155 virtual void LowerOperationWrapper(SDNode *N,
156 SmallVectorImpl<SDValue> &Results,
157 SelectionDAG &DAG) const;
159 /// LowerOperation - Provide custom lowering hooks for some operations.
160 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
162 /// ReplaceNodeResults - Replace the results of node with an illegal result
163 /// type with new values built out of custom code.
165 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
166 SelectionDAG &DAG) const;
168 /// getTargetNodeName - This method returns the name of a target specific
170 virtual const char *getTargetNodeName(unsigned Opcode) const;
172 /// getSetCCResultType - get the ISD::SETCC result ValueType
173 EVT getSetCCResultType(EVT VT) const;
175 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
178 void setMips16HardFloatLibCalls();
180 /// ByValArgInfo - Byval argument information.
181 struct ByValArgInfo {
182 unsigned FirstIdx; // Index of the first register used.
183 unsigned NumRegs; // Number of registers used for this argument.
184 unsigned Address; // Offset of the stack area used to pass this argument.
186 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
189 /// MipsCC - This class provides methods used to analyze formal and call
190 /// arguments and inquire about calling convention information.
193 MipsCC(CallingConv::ID CallConv, bool IsVarArg, bool IsO32,
196 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs);
197 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins);
198 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
199 CCValAssign::LocInfo LocInfo,
200 ISD::ArgFlagsTy ArgFlags);
202 const CCState &getCCInfo() const { return CCInfo; }
204 /// hasByValArg - Returns true if function has byval arguments.
205 bool hasByValArg() const { return !ByValArgs.empty(); }
207 /// useRegsForByval - Returns true if the calling convention allows the
208 /// use of registers to pass byval arguments.
209 bool useRegsForByval() const { return UseRegsForByval; }
211 /// regSize - Size (in number of bits) of integer registers.
212 unsigned regSize() const { return RegSize; }
214 /// numIntArgRegs - Number of integer registers available for calls.
215 unsigned numIntArgRegs() const { return NumIntArgRegs; }
217 /// reservedArgArea - The size of the area the caller reserves for
218 /// register arguments. This is 16-byte if ABI is O32.
219 unsigned reservedArgArea() const { return ReservedArgArea; }
221 /// intArgRegs - Pointer to array of integer registers.
222 const uint16_t *intArgRegs() const { return IntArgRegs; }
224 typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator;
225 byval_iterator byval_begin() const { return ByValArgs.begin(); }
226 byval_iterator byval_end() const { return ByValArgs.end(); }
229 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
233 bool UseRegsForByval;
235 unsigned NumIntArgRegs;
236 unsigned ReservedArgArea;
237 const uint16_t *IntArgRegs, *ShadowRegs;
238 SmallVector<ByValArgInfo, 2> ByValArgs;
239 llvm::CCAssignFn *FixedFn, *VarFn;
243 const MipsSubtarget *Subtarget;
245 bool HasMips64, IsN64, IsO32;
247 // Lower Operand helpers
248 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
249 CallingConv::ID CallConv, bool isVarArg,
250 const SmallVectorImpl<ISD::InputArg> &Ins,
251 DebugLoc dl, SelectionDAG &DAG,
252 SmallVectorImpl<SDValue> &InVals) const;
254 // Lower Operand specifics
255 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
256 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
257 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
258 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
259 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
260 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
261 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
262 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
263 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
264 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
265 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
266 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
267 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
268 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
269 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
270 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
271 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
272 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
274 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
275 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
276 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
277 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
278 SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
280 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
281 /// for tail call optimization.
282 bool IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
283 unsigned NextStackOffset,
284 const MipsFunctionInfo& FI) const;
286 /// copyByValArg - Copy argument registers which were used to pass a byval
287 /// argument to the stack. Create a stack frame object for the byval
289 void copyByValRegs(SDValue Chain, DebugLoc DL,
290 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
291 const ISD::ArgFlagsTy &Flags,
292 SmallVectorImpl<SDValue> &InVals,
293 const Argument *FuncArg,
294 const MipsCC &CC, const ByValArgInfo &ByVal) const;
296 /// passByValArg - Pass a byval argument in registers or on stack.
297 void passByValArg(SDValue Chain, DebugLoc DL,
298 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
299 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
300 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
301 const MipsCC &CC, const ByValArgInfo &ByVal,
302 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
304 /// writeVarArgRegs - Write variable function arguments passed in registers
305 /// to the stack. Also create a stack frame object for the first variable
307 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
308 SDValue Chain, DebugLoc DL, SelectionDAG &DAG) const;
311 LowerFormalArguments(SDValue Chain,
312 CallingConv::ID CallConv, bool isVarArg,
313 const SmallVectorImpl<ISD::InputArg> &Ins,
314 DebugLoc dl, SelectionDAG &DAG,
315 SmallVectorImpl<SDValue> &InVals) const;
317 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
318 SDValue Arg, DebugLoc DL, bool IsTailCall,
319 SelectionDAG &DAG) const;
322 LowerCall(TargetLowering::CallLoweringInfo &CLI,
323 SmallVectorImpl<SDValue> &InVals) const;
326 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
328 const SmallVectorImpl<ISD::OutputArg> &Outs,
329 LLVMContext &Context) const;
332 LowerReturn(SDValue Chain,
333 CallingConv::ID CallConv, bool isVarArg,
334 const SmallVectorImpl<ISD::OutputArg> &Outs,
335 const SmallVectorImpl<SDValue> &OutVals,
336 DebugLoc dl, SelectionDAG &DAG) const;
338 virtual MachineBasicBlock *
339 EmitInstrWithCustomInserter(MachineInstr *MI,
340 MachineBasicBlock *MBB) const;
342 // Inline asm support
343 ConstraintType getConstraintType(const std::string &Constraint) const;
345 /// Examine constraint string and operand type and determine a weight value.
346 /// The operand object must already have been set up with the operand type.
347 ConstraintWeight getSingleConstraintMatchWeight(
348 AsmOperandInfo &info, const char *constraint) const;
350 std::pair<unsigned, const TargetRegisterClass*>
351 getRegForInlineAsmConstraint(const std::string &Constraint,
354 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
355 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
356 /// true it means one of the asm constraint of the inline asm instruction
357 /// being processed is 'm'.
358 virtual void LowerAsmOperandForConstraint(SDValue Op,
359 std::string &Constraint,
360 std::vector<SDValue> &Ops,
361 SelectionDAG &DAG) const;
363 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
365 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
367 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
369 bool IsMemset, bool ZeroMemset,
371 MachineFunction &MF) const;
373 /// isFPImmLegal - Returns true if the target can instruction select the
374 /// specified FP immediate natively. If false, the legalizer will
375 /// materialize the FP immediate as a load from a constant pool.
376 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
378 virtual unsigned getJumpTableEncoding() const;
380 MachineBasicBlock *EmitBPOSGE32(MachineInstr *MI,
381 MachineBasicBlock *BB) const;
382 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
383 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
384 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
385 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
386 bool Nand = false) const;
387 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
388 MachineBasicBlock *BB, unsigned Size) const;
389 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
390 MachineBasicBlock *BB, unsigned Size) const;
394 #endif // MipsISELLOWERING_H