1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/Target/TargetLowering.h"
30 // Start the numbering from where ISD NodeType finishes.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Jump and link (call)
39 // Get the Higher 16 bits from a 32-bit immediate
40 // No relation with Mips Hi register
43 // Get the Lower 16 bits from a 32-bit immediate
44 // No relation with Mips Lo register
47 // Handle gp_rel (small data/bss sections) relocation.
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // Floating Point Rounding
93 // EXTR.W instrinsic nodes.
103 // DPA.W intrinsic nodes.
134 // Load/Store Left/Right nodes.
135 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
146 //===--------------------------------------------------------------------===//
147 // TargetLowering Implementation
148 //===--------------------------------------------------------------------===//
149 class MipsFunctionInfo;
151 class MipsTargetLowering : public TargetLowering {
153 explicit MipsTargetLowering(MipsTargetMachine &TM);
155 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
157 virtual bool allowsUnalignedMemoryAccesses (EVT VT, bool *Fast) const;
159 virtual void LowerOperationWrapper(SDNode *N,
160 SmallVectorImpl<SDValue> &Results,
161 SelectionDAG &DAG) const;
163 /// LowerOperation - Provide custom lowering hooks for some operations.
164 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
166 /// ReplaceNodeResults - Replace the results of node with an illegal result
167 /// type with new values built out of custom code.
169 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
170 SelectionDAG &DAG) const;
172 /// getTargetNodeName - This method returns the name of a target specific
174 virtual const char *getTargetNodeName(unsigned Opcode) const;
176 /// getSetCCResultType - get the ISD::SETCC result ValueType
177 EVT getSetCCResultType(EVT VT) const;
179 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
182 void SetMips16LibcallName(RTLIB::Libcall, const char *Name);
184 void setMips16HardFloatLibCalls();
187 getMips16HelperFunctionStubNumber(ArgListTy &Args) const;
189 const char *getMips16HelperFunction
190 (Type* RetTy, ArgListTy &Args, bool &needHelper) const;
192 /// ByValArgInfo - Byval argument information.
193 struct ByValArgInfo {
194 unsigned FirstIdx; // Index of the first register used.
195 unsigned NumRegs; // Number of registers used for this argument.
196 unsigned Address; // Offset of the stack area used to pass this argument.
198 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
201 /// MipsCC - This class provides methods used to analyze formal and call
202 /// arguments and inquire about calling convention information.
205 MipsCC(CallingConv::ID CallConv, bool IsO32, CCState &Info);
207 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
208 bool IsVarArg, bool IsSoftFloat,
209 const SDNode *CallNode,
210 std::vector<ArgListEntry> &FuncArgs);
211 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
213 Function::const_arg_iterator FuncArg);
214 const CCState &getCCInfo() const { return CCInfo; }
216 /// hasByValArg - Returns true if function has byval arguments.
217 bool hasByValArg() const { return !ByValArgs.empty(); }
219 /// regSize - Size (in number of bits) of integer registers.
220 unsigned regSize() const { return IsO32 ? 4 : 8; }
222 /// numIntArgRegs - Number of integer registers available for calls.
223 unsigned numIntArgRegs() const;
225 /// reservedArgArea - The size of the area the caller reserves for
226 /// register arguments. This is 16-byte if ABI is O32.
227 unsigned reservedArgArea() const;
229 /// Return pointer to array of integer argument registers.
230 const uint16_t *intArgRegs() const;
232 typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator;
233 byval_iterator byval_begin() const { return ByValArgs.begin(); }
234 byval_iterator byval_end() const { return ByValArgs.end(); }
237 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
238 CCValAssign::LocInfo LocInfo,
239 ISD::ArgFlagsTy ArgFlags);
241 /// useRegsForByval - Returns true if the calling convention allows the
242 /// use of registers to pass byval arguments.
243 bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
245 /// Return the function that analyzes fixed argument list functions.
246 llvm::CCAssignFn *fixedArgFn() const;
248 /// Return the function that analyzes variable argument list functions.
249 llvm::CCAssignFn *varArgFn() const;
251 const uint16_t *shadowRegs() const;
253 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
256 /// Return the type of the register which is used to pass an argument or
257 /// return a value. This function returns f64 if the argument is an i64
258 /// value which has been generated as a result of softening an f128 value.
259 /// Otherwise, it just returns VT.
260 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
261 bool IsSoftFloat) const;
264 CallingConv::ID CallConv;
266 SmallVector<ByValArgInfo, 2> ByValArgs;
270 const MipsSubtarget *Subtarget;
272 bool HasMips64, IsN64, IsO32;
274 // Lower Operand helpers
275 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
276 CallingConv::ID CallConv, bool isVarArg,
277 const SmallVectorImpl<ISD::InputArg> &Ins,
278 DebugLoc dl, SelectionDAG &DAG,
279 SmallVectorImpl<SDValue> &InVals) const;
281 // Lower Operand specifics
282 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
283 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
284 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
285 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
286 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
287 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
288 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
289 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
290 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
291 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
292 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
293 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
294 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
295 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
296 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
297 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
298 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
299 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
300 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
302 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
303 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
304 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
305 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
306 SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
308 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
309 /// for tail call optimization.
310 bool IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
311 unsigned NextStackOffset,
312 const MipsFunctionInfo& FI) const;
314 /// copyByValArg - Copy argument registers which were used to pass a byval
315 /// argument to the stack. Create a stack frame object for the byval
317 void copyByValRegs(SDValue Chain, DebugLoc DL,
318 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
319 const ISD::ArgFlagsTy &Flags,
320 SmallVectorImpl<SDValue> &InVals,
321 const Argument *FuncArg,
322 const MipsCC &CC, const ByValArgInfo &ByVal) const;
324 /// passByValArg - Pass a byval argument in registers or on stack.
325 void passByValArg(SDValue Chain, DebugLoc DL,
326 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
327 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
328 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
329 const MipsCC &CC, const ByValArgInfo &ByVal,
330 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
332 /// writeVarArgRegs - Write variable function arguments passed in registers
333 /// to the stack. Also create a stack frame object for the first variable
335 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
336 SDValue Chain, DebugLoc DL, SelectionDAG &DAG) const;
339 LowerFormalArguments(SDValue Chain,
340 CallingConv::ID CallConv, bool isVarArg,
341 const SmallVectorImpl<ISD::InputArg> &Ins,
342 DebugLoc dl, SelectionDAG &DAG,
343 SmallVectorImpl<SDValue> &InVals) const;
345 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
346 SDValue Arg, DebugLoc DL, bool IsTailCall,
347 SelectionDAG &DAG) const;
350 LowerCall(TargetLowering::CallLoweringInfo &CLI,
351 SmallVectorImpl<SDValue> &InVals) const;
354 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
356 const SmallVectorImpl<ISD::OutputArg> &Outs,
357 LLVMContext &Context) const;
360 LowerReturn(SDValue Chain,
361 CallingConv::ID CallConv, bool isVarArg,
362 const SmallVectorImpl<ISD::OutputArg> &Outs,
363 const SmallVectorImpl<SDValue> &OutVals,
364 DebugLoc dl, SelectionDAG &DAG) const;
366 virtual MachineBasicBlock *
367 EmitInstrWithCustomInserter(MachineInstr *MI,
368 MachineBasicBlock *MBB) const;
370 // Inline asm support
371 ConstraintType getConstraintType(const std::string &Constraint) const;
373 /// Examine constraint string and operand type and determine a weight value.
374 /// The operand object must already have been set up with the operand type.
375 ConstraintWeight getSingleConstraintMatchWeight(
376 AsmOperandInfo &info, const char *constraint) const;
378 std::pair<unsigned, const TargetRegisterClass*>
379 getRegForInlineAsmConstraint(const std::string &Constraint,
382 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
383 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
384 /// true it means one of the asm constraint of the inline asm instruction
385 /// being processed is 'm'.
386 virtual void LowerAsmOperandForConstraint(SDValue Op,
387 std::string &Constraint,
388 std::vector<SDValue> &Ops,
389 SelectionDAG &DAG) const;
391 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
393 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
395 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
397 bool IsMemset, bool ZeroMemset,
399 MachineFunction &MF) const;
401 /// isFPImmLegal - Returns true if the target can instruction select the
402 /// specified FP immediate natively. If false, the legalizer will
403 /// materialize the FP immediate as a load from a constant pool.
404 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
406 virtual unsigned getJumpTableEncoding() const;
408 MachineBasicBlock *EmitBPOSGE32(MachineInstr *MI,
409 MachineBasicBlock *BB) const;
410 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
411 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
412 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
413 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
414 bool Nand = false) const;
415 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
416 MachineBasicBlock *BB, unsigned Size) const;
417 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
418 MachineBasicBlock *BB, unsigned Size) const;
419 MachineBasicBlock *EmitSel16(unsigned Opc, MachineInstr *MI,
420 MachineBasicBlock *BB) const;
421 MachineBasicBlock *EmitSeliT16(unsigned Opc1, unsigned Opc2,
423 MachineBasicBlock *BB) const;
425 MachineBasicBlock *EmitSelT16(unsigned Opc1, unsigned Opc2,
427 MachineBasicBlock *BB) const;
428 MachineBasicBlock *EmitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
430 MachineBasicBlock *BB) const;
431 MachineBasicBlock *EmitFEXT_T8I8I16_ins(
432 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc,
433 MachineInstr *MI, MachineBasicBlock *BB) const;
434 MachineBasicBlock *EmitFEXT_CCRX16_ins(
436 MachineInstr *MI, MachineBasicBlock *BB) const;
437 MachineBasicBlock *EmitFEXT_CCRXI16_ins(
438 unsigned SltiOpc, unsigned SltiXOpc,
439 MachineInstr *MI, MachineBasicBlock *BB )const;
444 #endif // MipsISELLOWERING_H