1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetLowering.h"
21 #include "MipsSubtarget.h"
26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 // Jump and link (call)
32 // Get the Higher 16 bits from a 32-bit immediate
33 // No relation with Mips Hi register
36 // Get the Lower 16 bits from a 32-bit immediate
37 // No relation with Mips Lo register
40 // Handle gp_rel (small data/bss sections) relocation.
43 // General Dynamic TLS
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // Floating Point Rounding
90 //===--------------------------------------------------------------------===//
91 // TargetLowering Implementation
92 //===--------------------------------------------------------------------===//
94 class MipsTargetLowering : public TargetLowering {
96 explicit MipsTargetLowering(MipsTargetMachine &TM);
98 /// LowerOperation - Provide custom lowering hooks for some operations.
99 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
101 /// getTargetNodeName - This method returns the name of a target specific
103 virtual const char *getTargetNodeName(unsigned Opcode) const;
105 /// getSetCCResultType - get the ISD::SETCC result ValueType
106 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
108 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
111 const MipsSubtarget *Subtarget;
114 // Lower Operand helpers
115 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
116 CallingConv::ID CallConv, bool isVarArg,
117 const SmallVectorImpl<ISD::InputArg> &Ins,
118 DebugLoc dl, SelectionDAG &DAG,
119 SmallVectorImpl<SDValue> &InVals) const;
121 // Lower Operand specifics
122 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
123 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
125 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
126 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
127 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
128 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
129 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
130 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
131 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
133 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
136 LowerFormalArguments(SDValue Chain,
137 CallingConv::ID CallConv, bool isVarArg,
138 const SmallVectorImpl<ISD::InputArg> &Ins,
139 DebugLoc dl, SelectionDAG &DAG,
140 SmallVectorImpl<SDValue> &InVals) const;
143 LowerCall(SDValue Chain, SDValue Callee,
144 CallingConv::ID CallConv, bool isVarArg,
146 const SmallVectorImpl<ISD::OutputArg> &Outs,
147 const SmallVectorImpl<SDValue> &OutVals,
148 const SmallVectorImpl<ISD::InputArg> &Ins,
149 DebugLoc dl, SelectionDAG &DAG,
150 SmallVectorImpl<SDValue> &InVals) const;
153 LowerReturn(SDValue Chain,
154 CallingConv::ID CallConv, bool isVarArg,
155 const SmallVectorImpl<ISD::OutputArg> &Outs,
156 const SmallVectorImpl<SDValue> &OutVals,
157 DebugLoc dl, SelectionDAG &DAG) const;
159 virtual MachineBasicBlock *
160 EmitInstrWithCustomInserter(MachineInstr *MI,
161 MachineBasicBlock *MBB) const;
163 // Inline asm support
164 ConstraintType getConstraintType(const std::string &Constraint) const;
166 /// Examine constraint string and operand type and determine a weight value.
167 /// The operand object must already have been set up with the operand type.
168 ConstraintWeight getSingleConstraintMatchWeight(
169 AsmOperandInfo &info, const char *constraint) const;
171 std::pair<unsigned, const TargetRegisterClass*>
172 getRegForInlineAsmConstraint(const std::string &Constraint,
175 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
177 /// isFPImmLegal - Returns true if the target can instruction select the
178 /// specified FP immediate natively. If false, the legalizer will
179 /// materialize the FP immediate as a load from a constant pool.
180 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
182 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
183 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
184 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
185 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
186 bool Nand = false) const;
187 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
188 MachineBasicBlock *BB, unsigned Size) const;
189 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
190 MachineBasicBlock *BB, unsigned Size) const;
194 #endif // MipsISELLOWERING_H