1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 // Jump and link (call)
32 // Get the Higher 16 bits from a 32-bit immediate
33 // No relation with Mips Hi register
36 // Get the Lower 16 bits from a 32-bit immediate
37 // No relation with Mips Lo register
40 // Handle gp_rel (small data/bss sections) relocation.
46 // Floating Point Branch Conditional
49 // Floating Point Compare
52 // Floating Point Conditional Moves
56 // Floating Point Rounding
84 // EXTR.W instrinsic nodes.
94 // DPA.W intrinsic nodes.
125 // Load/Store Left/Right nodes.
126 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
137 //===--------------------------------------------------------------------===//
138 // TargetLowering Implementation
139 //===--------------------------------------------------------------------===//
141 class MipsTargetLowering : public TargetLowering {
143 explicit MipsTargetLowering(MipsTargetMachine &TM);
145 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
147 virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
149 virtual void LowerOperationWrapper(SDNode *N,
150 SmallVectorImpl<SDValue> &Results,
151 SelectionDAG &DAG) const;
153 /// LowerOperation - Provide custom lowering hooks for some operations.
154 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
156 /// ReplaceNodeResults - Replace the results of node with an illegal result
157 /// type with new values built out of custom code.
159 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
160 SelectionDAG &DAG) const;
162 /// getTargetNodeName - This method returns the name of a target specific
164 virtual const char *getTargetNodeName(unsigned Opcode) const;
166 /// getSetCCResultType - get the ISD::SETCC result ValueType
167 EVT getSetCCResultType(EVT VT) const;
169 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
172 const MipsSubtarget *Subtarget;
174 bool HasMips64, IsN64, IsO32;
176 // Lower Operand helpers
177 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
178 CallingConv::ID CallConv, bool isVarArg,
179 const SmallVectorImpl<ISD::InputArg> &Ins,
180 DebugLoc dl, SelectionDAG &DAG,
181 SmallVectorImpl<SDValue> &InVals) const;
183 // Lower Operand specifics
184 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
185 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
186 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
187 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
188 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
189 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
190 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
191 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
192 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
193 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
194 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
195 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
196 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
197 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
198 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
199 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
200 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
201 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
203 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
204 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
205 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
206 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
209 LowerFormalArguments(SDValue Chain,
210 CallingConv::ID CallConv, bool isVarArg,
211 const SmallVectorImpl<ISD::InputArg> &Ins,
212 DebugLoc dl, SelectionDAG &DAG,
213 SmallVectorImpl<SDValue> &InVals) const;
216 LowerCall(TargetLowering::CallLoweringInfo &CLI,
217 SmallVectorImpl<SDValue> &InVals) const;
220 LowerReturn(SDValue Chain,
221 CallingConv::ID CallConv, bool isVarArg,
222 const SmallVectorImpl<ISD::OutputArg> &Outs,
223 const SmallVectorImpl<SDValue> &OutVals,
224 DebugLoc dl, SelectionDAG &DAG) const;
226 virtual MachineBasicBlock *
227 EmitInstrWithCustomInserter(MachineInstr *MI,
228 MachineBasicBlock *MBB) const;
230 // Inline asm support
231 ConstraintType getConstraintType(const std::string &Constraint) const;
233 /// Examine constraint string and operand type and determine a weight value.
234 /// The operand object must already have been set up with the operand type.
235 ConstraintWeight getSingleConstraintMatchWeight(
236 AsmOperandInfo &info, const char *constraint) const;
238 std::pair<unsigned, const TargetRegisterClass*>
239 getRegForInlineAsmConstraint(const std::string &Constraint,
242 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
243 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
244 /// true it means one of the asm constraint of the inline asm instruction
245 /// being processed is 'm'.
246 virtual void LowerAsmOperandForConstraint(SDValue Op,
247 std::string &Constraint,
248 std::vector<SDValue> &Ops,
249 SelectionDAG &DAG) const;
251 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
253 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
254 unsigned SrcAlign, bool IsZeroVal,
256 MachineFunction &MF) const;
258 /// isFPImmLegal - Returns true if the target can instruction select the
259 /// specified FP immediate natively. If false, the legalizer will
260 /// materialize the FP immediate as a load from a constant pool.
261 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
263 virtual unsigned getJumpTableEncoding() const;
265 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
266 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
267 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
268 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
269 bool Nand = false) const;
270 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
271 MachineBasicBlock *BB, unsigned Size) const;
272 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
273 MachineBasicBlock *BB, unsigned Size) const;
277 #endif // MipsISELLOWERING_H