1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Mips FPU instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Floating Point Instructions
16 // ------------------------
18 // - 32 64-bit registers (default mode)
19 // - 16 even 32-bit registers (32-bit compatible mode) for
20 // single and double access.
22 // - 16 even 32-bit registers - single and double (aliased)
23 // - 32 32-bit registers (within single-only mode)
24 //===----------------------------------------------------------------------===//
26 // Floating Point Compare and Branch
27 def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>,
29 SDTCisVT<2, OtherVT>]>;
30 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
32 def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>,
34 def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
35 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
38 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
42 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
43 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
44 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
45 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
46 [SDNPHasChain, SDNPOptInGlue]>;
47 def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>;
48 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
49 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
50 SDT_MipsExtractElementF64>;
52 // Operand for printing out a condition code.
53 let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
54 def condcode : Operand<i32>;
56 //===----------------------------------------------------------------------===//
57 // Feature predicates.
58 //===----------------------------------------------------------------------===//
60 def IsFP64bit : Predicate<"Subtarget->isFP64bit()">,
61 AssemblerPredicate<"FeatureFP64Bit">;
62 def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">,
63 AssemblerPredicate<"!FeatureFP64Bit">;
64 def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">,
65 AssemblerPredicate<"FeatureSingleFloat">;
66 def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">,
67 AssemblerPredicate<"!FeatureSingleFloat">;
69 //===----------------------------------------------------------------------===//
70 // Mips FGR size adjectives.
71 // They are mutually exclusive.
72 //===----------------------------------------------------------------------===//
74 class FGR_32 { list<Predicate> FGRPredicates = [NotFP64bit]; }
75 class FGR_64 { list<Predicate> FGRPredicates = [IsFP64bit]; }
77 //===----------------------------------------------------------------------===//
79 // FP immediate patterns.
80 def fpimm0 : PatLeaf<(fpimm), [{
81 return N->isExactlyValue(+0.0);
84 def fpimm0neg : PatLeaf<(fpimm), [{
85 return N->isExactlyValue(-0.0);
88 //===----------------------------------------------------------------------===//
89 // Instruction Class Templates
91 // A set of multiclasses is used to address the register usage.
93 // S32 - single precision in 16 32bit even fp registers
94 // single precision in 32 32bit fp registers in SingleOnly mode
95 // S64 - single precision in 32 64bit fp registers (In64BitMode)
96 // D32 - double precision in 16 32bit even fp registers
97 // D64 - double precision in 32 64bit fp registers (In64BitMode)
99 // Only S32 and D32 are supported right now.
100 //===----------------------------------------------------------------------===//
102 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
103 SDPatternOperator OpNode= null_frag> :
104 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
105 !strconcat(opstr, "\t$fd, $fs, $ft"),
106 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr> {
107 let isCommutable = IsComm;
110 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
111 SDPatternOperator OpNode = null_frag> {
112 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
113 AdditionalRequires<[NotFP64bit]>;
114 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin,
116 AdditionalRequires<[IsFP64bit]> {
117 string DecoderNamespace = "Mips64";
121 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
122 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
123 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
127 multiclass ABSS_M<string opstr, InstrItinClass Itin,
128 SDPatternOperator OpNode= null_frag> {
129 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
130 AdditionalRequires<[NotFP64bit]>;
131 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
132 AdditionalRequires<[IsFP64bit]> {
133 string DecoderNamespace = "Mips64";
137 multiclass ROUND_M<string opstr, InstrItinClass Itin> {
138 def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>,
139 AdditionalRequires<[NotFP64bit]>;
140 def _D64 : ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>,
141 AdditionalRequires<[IsFP64bit]> {
142 let DecoderNamespace = "Mips64";
146 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
147 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
148 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
149 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>;
151 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
152 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
153 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
154 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>;
156 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
157 InstrItinClass Itin> :
158 InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt),
159 !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr> {
160 // $fs_in is part of a white lie to work around a widespread bug in the FPU
161 // implementation. See expandBuildPairF64 for details.
162 let Constraints = "$fs = $fs_in";
165 class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
166 SDPatternOperator OpNode= null_frag> :
167 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
168 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
169 let DecoderMethod = "DecodeFMem";
173 class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
174 SDPatternOperator OpNode= null_frag> :
175 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
176 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
177 let DecoderMethod = "DecodeFMem";
181 class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
182 SDPatternOperator OpNode = null_frag> :
183 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
184 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
185 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin,
188 class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
189 SDPatternOperator OpNode = null_frag> :
190 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
191 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
192 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
195 class LWXC1_FT<string opstr, RegisterOperand DRC,
196 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
197 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index),
198 !strconcat(opstr, "\t$fd, ${index}(${base})"),
199 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,
201 let AddedComplexity = 20;
204 class SWXC1_FT<string opstr, RegisterOperand DRC,
205 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
206 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
207 !strconcat(opstr, "\t$fs, ${index}(${base})"),
208 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
210 let AddedComplexity = 20;
213 class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
214 SDPatternOperator Op = null_frag> :
215 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
216 !strconcat(opstr, "\t$fcc, $offset"),
217 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,
220 let isTerminator = 1;
221 let hasDelaySlot = 1;
225 class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
226 SDPatternOperator OpNode = null_frag> :
227 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
228 !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
229 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR,
230 !strconcat("c.$cond.", typestr)> {
232 let isCodeGenOnly = 1;
235 class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC,
236 InstrItinClass itin> :
237 InstSE<(outs), (ins RC:$fs, RC:$ft),
238 !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], itin,
241 multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt,
242 InstrItinClass itin> {
243 def C_F_#NAME : C_COND_FT<"f", TypeStr, RC, itin>, C_COND_FM<fmt, 0>;
244 def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC, itin>, C_COND_FM<fmt, 1>;
245 def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC, itin>, C_COND_FM<fmt, 2>;
246 def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC, itin>, C_COND_FM<fmt, 3>;
247 def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC, itin>, C_COND_FM<fmt, 4>;
248 def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC, itin>, C_COND_FM<fmt, 5>;
249 def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC, itin>, C_COND_FM<fmt, 6>;
250 def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC, itin>, C_COND_FM<fmt, 7>;
251 def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC, itin>, C_COND_FM<fmt, 8>;
252 def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC, itin>, C_COND_FM<fmt, 9>;
253 def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC, itin>, C_COND_FM<fmt, 10>;
254 def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC, itin>, C_COND_FM<fmt, 11>;
255 def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC, itin>, C_COND_FM<fmt, 12>;
256 def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC, itin>, C_COND_FM<fmt, 13>;
257 def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC, itin>, C_COND_FM<fmt, 14>;
258 def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC, itin>, C_COND_FM<fmt, 15>;
261 defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6;
262 defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
263 AdditionalRequires<[NotFP64bit]>;
264 let DecoderNamespace = "Mips64" in
265 defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
266 AdditionalRequires<[IsFP64bit]>;
268 //===----------------------------------------------------------------------===//
269 // Floating Point Instructions
270 //===----------------------------------------------------------------------===//
271 def ROUND_W_S : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
272 ABSS_FM<0xc, 16>, ISA_MIPS2;
273 def TRUNC_W_S : MMRel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
274 ABSS_FM<0xd, 16>, ISA_MIPS2;
275 def CEIL_W_S : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
276 ABSS_FM<0xe, 16>, ISA_MIPS2;
277 def FLOOR_W_S : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
278 ABSS_FM<0xf, 16>, ISA_MIPS2;
279 def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
282 defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2;
283 defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2;
284 defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;
285 defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;
286 defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
288 let DecoderNamespace = "Mips64" in {
289 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
290 ABSS_FM<0x8, 16>, FGR_64;
291 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,
292 ABSS_FM<0x8, 17>, FGR_64;
293 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>,
294 ABSS_FM<0x9, 16>, FGR_64;
295 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>,
296 ABSS_FM<0x9, 17>, FGR_64;
297 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>,
298 ABSS_FM<0xa, 16>, FGR_64;
299 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>,
300 ABSS_FM<0xa, 17>, FGR_64;
301 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>,
302 ABSS_FM<0xb, 16>, FGR_64;
303 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>,
304 ABSS_FM<0xb, 17>, FGR_64;
307 def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
309 def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
310 ABSS_FM<0x25, 16>, INSN_MIPS3_32R2;
311 def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
312 ABSS_FM<0x25, 17>, INSN_MIPS3_32R2;
314 def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
315 ABSS_FM<0x20, 17>, FGR_32;
316 def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
317 ABSS_FM<0x21, 20>, FGR_32;
318 def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
319 ABSS_FM<0x21, 16>, FGR_32;
321 let DecoderNamespace = "Mips64" in {
322 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
323 ABSS_FM<0x20, 17>, FGR_64;
324 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
325 ABSS_FM<0x20, 21>, FGR_64;
326 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
327 ABSS_FM<0x21, 20>, FGR_64;
328 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,
329 ABSS_FM<0x21, 16>, FGR_64;
330 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>,
331 ABSS_FM<0x21, 21>, FGR_64;
334 let isPseudo = 1, isCodeGenOnly = 1 in {
335 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>;
336 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>;
337 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
338 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>;
339 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
342 def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
344 def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
346 defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
347 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>;
349 def FSQRT_S : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, fsqrt>,
350 ABSS_FM<0x4, 16>, ISA_MIPS2;
351 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
353 // The odd-numbered registers are only referenced when doing loads,
354 // stores, and moves between floating-point and integer registers.
355 // When defining instructions, we reference all 32-bit registers,
356 // regardless of register aliasing.
358 /// Move Control Registers From/To CPU Registers
359 def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>;
360 def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>;
361 def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
362 bitconvert>, MFC1_FM<0>;
363 def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
364 bitconvert>, MFC1_FM<4>;
365 def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
366 MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>;
367 def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
368 MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> {
369 let DecoderNamespace = "Mips64";
371 def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
372 MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>;
373 def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
374 MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> {
375 let DecoderNamespace = "Mips64";
377 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
378 bitconvert>, MFC1_FM<1>, ISA_MIPS3;
379 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
380 bitconvert>, MFC1_FM<5>, ISA_MIPS3;
382 def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
384 def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
385 ABSS_FM<0x6, 17>, AdditionalRequires<[NotFP64bit]>;
386 def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
387 ABSS_FM<0x6, 17>, AdditionalRequires<[IsFP64bit]> {
388 let DecoderNamespace = "Mips64";
391 /// Floating Point Memory Instructions
392 def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>;
393 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>;
395 let DecoderNamespace = "Mips64" in {
396 def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>, ISA_MIPS2,
398 def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, ISA_MIPS2,
402 def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>,
404 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>,
407 // Cop2 Memory Instructions
408 // FIXME: These aren't really FPU instructions and as such don't belong in this
410 def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
411 ISA_MIPS1_NOT_32R6_64R6;
412 def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
413 ISA_MIPS1_NOT_32R6_64R6;
414 def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
415 ISA_MIPS2_NOT_32R6_64R6;
416 def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
417 ISA_MIPS2_NOT_32R6_64R6;
419 // Cop3 Memory Instructions
420 // FIXME: These aren't really FPU instructions and as such don't belong in this
422 let DecoderNamespace = "COP3_" in {
423 def LWC3 : LW_FT<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
424 def SWC3 : SW_FT<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
425 def LDC3 : LW_FT<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
427 def SDC3 : SW_FT<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
431 // Indexed loads and stores.
432 // Base register + offset register addressing mode (indicated by "x" in the
433 // instruction mnemonic) is disallowed under NaCl.
434 let AdditionalPredicates = [IsNotNaCl] in {
435 def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>,
436 INSN_MIPS4_32R2_NOT_32R6_64R6;
437 def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>,
438 INSN_MIPS4_32R2_NOT_32R6_64R6;
441 let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in {
442 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
443 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
444 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
445 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
448 let DecoderNamespace="Mips64" in {
449 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
450 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
451 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
452 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
455 // Load/store doubleword indexed unaligned.
456 let AdditionalPredicates = [IsNotNaCl] in {
457 def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
458 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
459 def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
460 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
463 let DecoderNamespace="Mips64" in {
464 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
465 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
466 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
467 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
470 /// Floating-point Aritmetic
471 def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
473 defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>;
474 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
476 defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>;
477 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
479 defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>;
480 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
482 defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
484 def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
485 MADDS_FM<4, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
486 def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
487 MADDS_FM<5, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
489 let AdditionalPredicates = [NoNaNsFPMath] in {
490 def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
491 MADDS_FM<6, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
492 def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
493 MADDS_FM<7, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
496 def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
497 MADDS_FM<4, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
498 def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
499 MADDS_FM<5, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
501 let AdditionalPredicates = [NoNaNsFPMath] in {
502 def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
503 MADDS_FM<6, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
504 def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
505 MADDS_FM<7, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
508 let isCodeGenOnly=1 in {
509 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
510 MADDS_FM<4, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
511 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
512 MADDS_FM<5, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
515 let AdditionalPredicates = [NoNaNsFPMath],
517 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
518 MADDS_FM<6, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
519 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
520 MADDS_FM<7, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
523 //===----------------------------------------------------------------------===//
524 // Floating Point Branch Codes
525 //===----------------------------------------------------------------------===//
526 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
527 // They must be kept in synch.
528 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
529 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
531 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, IIBranch, MIPS_BRANCH_F>,
532 BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
533 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, IIBranch, MIPS_BRANCH_T>,
534 BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
536 //===----------------------------------------------------------------------===//
537 // Floating Point Flag Conditions
538 //===----------------------------------------------------------------------===//
539 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
540 // They must be kept in synch.
541 def MIPS_FCOND_F : PatLeaf<(i32 0)>;
542 def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
543 def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>;
544 def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
545 def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
546 def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
547 def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
548 def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
549 def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
550 def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
551 def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
552 def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
553 def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
554 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
555 def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
556 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
558 /// Floating Point Compare
559 def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>,
560 ISA_MIPS1_NOT_32R6_64R6;
561 def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
562 ISA_MIPS1_NOT_32R6_64R6, AdditionalRequires<[NotFP64bit]>;
563 let DecoderNamespace = "Mips64" in
564 def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
565 ISA_MIPS1_NOT_32R6_64R6, AdditionalRequires<[IsFP64bit]>;
567 //===----------------------------------------------------------------------===//
568 // Floating Point Pseudo-Instructions
569 //===----------------------------------------------------------------------===//
571 // This pseudo instr gets expanded into 2 mtc1 instrs after register
573 class BuildPairF64Base<RegisterOperand RO> :
574 PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi),
575 [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>;
577 def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>,
578 AdditionalRequires<[NotFP64bit]>;
579 def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>,
580 AdditionalRequires<[IsFP64bit]>;
582 // This pseudo instr gets expanded into 2 mfc1 instrs after register
584 // if n is 0, lower part of src is extracted.
585 // if n is 1, higher part of src is extracted.
586 class ExtractElementF64Base<RegisterOperand RO> :
587 PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n),
588 [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>;
590 def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>,
591 AdditionalRequires<[NotFP64bit]>;
592 def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>,
593 AdditionalRequires<[IsFP64bit]>;
595 //===----------------------------------------------------------------------===//
597 //===----------------------------------------------------------------------===//
598 def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>,
599 ISA_MIPS1_NOT_32R6_64R6;
600 def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>,
601 ISA_MIPS1_NOT_32R6_64R6;
603 //===----------------------------------------------------------------------===//
604 // Floating Point Patterns
605 //===----------------------------------------------------------------------===//
606 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
607 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
609 def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)),
610 (PseudoCVT_S_W GPR32Opnd:$src)>;
611 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
612 (TRUNC_W_S FGR32Opnd:$src)>;
614 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
615 (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32;
616 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
617 (TRUNC_W_D32 AFGR64Opnd:$src)>, FGR_32;
618 def : MipsPat<(f32 (fround AFGR64Opnd:$src)),
619 (CVT_S_D32 AFGR64Opnd:$src)>, FGR_32;
620 def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
621 (CVT_D32_S FGR32Opnd:$src)>, FGR_32;
623 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64;
624 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, FGR_64;
626 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
627 (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64;
628 def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)),
629 (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64;
630 def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)),
631 (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64;
633 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
634 (TRUNC_W_D64 FGR64Opnd:$src)>, FGR_64;
635 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
636 (TRUNC_L_S FGR32Opnd:$src)>, FGR_64;
637 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
638 (TRUNC_L_D64 FGR64Opnd:$src)>, FGR_64;
640 def : MipsPat<(f32 (fround FGR64Opnd:$src)),
641 (CVT_S_D64 FGR64Opnd:$src)>, FGR_64;
642 def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
643 (CVT_D64_S FGR32Opnd:$src)>, FGR_64;
645 // Patterns for loads/stores with a reg+imm operand.
646 let AddedComplexity = 40 in {
647 def : LoadRegImmPat<LWC1, f32, load>;
648 def : StoreRegImmPat<SWC1, f32>;
650 def : LoadRegImmPat<LDC164, f64, load>, FGR_64;
651 def : StoreRegImmPat<SDC164, f64>, FGR_64;
653 def : LoadRegImmPat<LDC1, f64, load>, FGR_32;
654 def : StoreRegImmPat<SDC1, f64>, FGR_32;