1 //===- MipsInstrFPU.td - Mips FPU Instruction Information --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Floating Point Instructions
16 // ------------------------
18 // - 32 64-bit registers (default mode)
19 // - 16 even 32-bit registers (32-bit compatible mode) for
20 // single and double access.
22 // - 16 even 32-bit registers - single and double (aliased)
23 // - 32 32-bit registers (within single-only mode)
24 //===----------------------------------------------------------------------===//
26 // Floating Point Compare and Branch
27 def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
28 SDTCisVT<1, OtherVT>]>;
29 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
31 def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
33 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
36 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
40 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
41 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
42 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
43 def MipsFPRound : SDNode<"MipsISD::FPRound", SDTFPRoundOp, [SDNPOptInGlue]>;
44 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
45 [SDNPHasChain, SDNPOptInGlue]>;
46 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
47 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
48 SDT_MipsExtractElementF64>;
50 // Operand for printing out a condition code.
51 let PrintMethod = "printFCCOperand" in
52 def condcode : Operand<i32>;
54 //===----------------------------------------------------------------------===//
55 // Feature predicates.
56 //===----------------------------------------------------------------------===//
58 def In32BitMode : Predicate<"!Subtarget.isFP64bit()">;
59 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">;
60 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
61 def IsNotMipsI : Predicate<"!Subtarget.isMips1()">;
63 //===----------------------------------------------------------------------===//
64 // Instruction Class Templates
66 // A set of multiclasses is used to address the register usage.
68 // S32 - single precision in 16 32bit even fp registers
69 // single precision in 32 32bit fp registers in SingleOnly mode
70 // S64 - single precision in 32 64bit fp registers (In64BitMode)
71 // D32 - double precision in 16 32bit even fp registers
72 // D64 - double precision in 32 64bit fp registers (In64BitMode)
74 // Only S32 and D32 are supported right now.
75 //===----------------------------------------------------------------------===//
77 multiclass FFR1_1<bits<6> funct, string asmstr>
79 def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
80 !strconcat(asmstr, ".s $fd, $fs"), []>;
82 def _D32 : FFR<0x11, funct, 0x1, (outs FGR32:$fd), (ins AFGR64:$fs),
83 !strconcat(asmstr, ".d $fd, $fs"), []>, Requires<[In32BitMode]>;
86 multiclass FFR1_2<bits<6> funct, string asmstr, SDNode FOp>
88 def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
89 !strconcat(asmstr, ".s $fd, $fs"),
90 [(set FGR32:$fd, (FOp FGR32:$fs))]>;
92 def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
93 !strconcat(asmstr, ".d $fd, $fs"),
94 [(set AFGR64:$fd, (FOp AFGR64:$fs))]>, Requires<[In32BitMode]>;
97 class FFR1_3<bits<6> funct, bits<5> fmt, RegisterClass RcSrc,
98 RegisterClass RcDst, string asmstr>:
99 FFR<0x11, funct, fmt, (outs RcSrc:$fd), (ins RcDst:$fs),
100 !strconcat(asmstr, " $fd, $fs"), []>;
103 multiclass FFR1_4<bits<6> funct, string asmstr, SDNode FOp> {
104 def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd),
105 (ins FGR32:$fs, FGR32:$ft),
106 !strconcat(asmstr, ".s $fd, $fs, $ft"),
107 [(set FGR32:$fd, (FOp FGR32:$fs, FGR32:$ft))]>;
109 def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd),
110 (ins AFGR64:$fs, AFGR64:$ft),
111 !strconcat(asmstr, ".d $fd, $fs, $ft"),
112 [(set AFGR64:$fd, (FOp AFGR64:$fs, AFGR64:$ft))]>,
113 Requires<[In32BitMode]>;
116 //===----------------------------------------------------------------------===//
117 // Floating Point Instructions
118 //===----------------------------------------------------------------------===//
121 defm FLOOR_W : FFR1_1<0b001111, "floor.w">;
122 defm CEIL_W : FFR1_1<0b001110, "ceil.w">;
123 defm ROUND_W : FFR1_1<0b001100, "round.w">;
124 defm TRUNC_W : FFR1_1<0b001101, "trunc.w">;
125 defm CVTW : FFR1_1<0b100100, "cvt.w">;
127 defm FABS : FFR1_2<0b000101, "abs", fabs>;
128 defm FNEG : FFR1_2<0b000111, "neg", fneg>;
129 defm FSQRT : FFR1_2<0b000100, "sqrt", fsqrt>;
131 /// Convert to Single Precison
132 def CVTS_W32 : FFR1_3<0b100000, 0x2, FGR32, FGR32, "cvt.s.w">;
134 let Predicates = [IsNotSingleFloat] in {
135 /// Ceil to long signed integer
136 def CEIL_LS : FFR1_3<0b001010, 0x0, FGR32, FGR32, "ceil.l">;
137 def CEIL_LD : FFR1_3<0b001010, 0x1, AFGR64, AFGR64, "ceil.l">;
139 /// Round to long signed integer
140 def ROUND_LS : FFR1_3<0b001000, 0x0, FGR32, FGR32, "round.l">;
141 def ROUND_LD : FFR1_3<0b001000, 0x1, AFGR64, AFGR64, "round.l">;
143 /// Floor to long signed integer
144 def FLOOR_LS : FFR1_3<0b001011, 0x0, FGR32, FGR32, "floor.l">;
145 def FLOOR_LD : FFR1_3<0b001011, 0x1, AFGR64, AFGR64, "floor.l">;
147 /// Trunc to long signed integer
148 def TRUNC_LS : FFR1_3<0b001001, 0x0, FGR32, FGR32, "trunc.l">;
149 def TRUNC_LD : FFR1_3<0b001001, 0x1, AFGR64, AFGR64, "trunc.l">;
151 /// Convert to long signed integer
152 def CVTL_S : FFR1_3<0b100101, 0x0, FGR32, FGR32, "cvt.l">;
153 def CVTL_D : FFR1_3<0b100101, 0x1, AFGR64, AFGR64, "cvt.l">;
155 /// Convert to Double Precison
156 def CVTD_S32 : FFR1_3<0b100001, 0x0, AFGR64, FGR32, "cvt.d.s">;
157 def CVTD_W32 : FFR1_3<0b100001, 0x2, AFGR64, FGR32, "cvt.d.w">;
158 def CVTD_L32 : FFR1_3<0b100001, 0x3, AFGR64, AFGR64, "cvt.d.l">;
160 /// Convert to Single Precison
161 def CVTS_D32 : FFR1_3<0b100000, 0x1, FGR32, AFGR64, "cvt.s.d">;
162 def CVTS_L32 : FFR1_3<0b100000, 0x3, FGR32, AFGR64, "cvt.s.l">;
166 // The odd-numbered registers are only referenced when doing loads,
167 // stores, and moves between floating-point and integer registers.
168 // When defining instructions, we reference all 32-bit registers,
169 // regardless of register aliasing.
171 /// Move Control Registers From/To CPU Registers
172 def CFC1 : FFR<0x11, 0x0, 0x2, (outs CPURegs:$rt), (ins CCR:$fs),
173 "cfc1 $rt, $fs", []>;
175 def CTC1 : FFR<0x11, 0x0, 0x6, (outs CCR:$rt), (ins CPURegs:$fs),
176 "ctc1 $fs, $rt", []>;
178 def MFC1 : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
179 "mfc1 $rt, $fs", []>;
181 def MTC1 : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
182 "mtc1 $rt, $fs", []>;
185 def FMOV_S32 : FFR<0x11, 0b000110, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
186 "mov.s $fd, $fs", []>;
187 def FMOV_D32 : FFR<0x11, 0b000110, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
188 "mov.d $fd, $fs", []>;
190 /// Floating Point Memory Instructions
191 let Predicates = [IsNotSingleFloat, IsNotMipsI] in {
192 def LDC1 : FFI<0b110101, (outs AFGR64:$ft), (ins mem:$addr),
193 "ldc1 $ft, $addr", [(set AFGR64:$ft, (load addr:$addr))]>;
195 def SDC1 : FFI<0b111101, (outs), (ins AFGR64:$ft, mem:$addr),
196 "sdc1 $ft, $addr", [(store AFGR64:$ft, addr:$addr)]>;
199 // LWC1 and SWC1 can always be emitted with odd registers.
200 def LWC1 : FFI<0b110001, (outs FGR32:$ft), (ins mem:$addr), "lwc1 $ft, $addr",
201 [(set FGR32:$ft, (load addr:$addr))]>;
202 def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr), "swc1 $ft, $addr",
203 [(store FGR32:$ft, addr:$addr)]>;
205 /// Floating-point Aritmetic
206 defm FADD : FFR1_4<0x10, "add", fadd>;
207 defm FDIV : FFR1_4<0x03, "div", fdiv>;
208 defm FMUL : FFR1_4<0x02, "mul", fmul>;
209 defm FSUB : FFR1_4<0x01, "sub", fsub>;
211 //===----------------------------------------------------------------------===//
212 // Floating Point Branch Codes
213 //===----------------------------------------------------------------------===//
214 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
215 // They must be kept in synch.
216 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
217 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
218 def MIPS_BRANCH_FL : PatLeaf<(i32 2)>;
219 def MIPS_BRANCH_TL : PatLeaf<(i32 3)>;
221 /// Floating Point Branch of False/True (Likely)
222 let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in
223 class FBRANCH<PatLeaf op, string asmstr> : FFI<0x11, (outs),
224 (ins brtarget:$dst), !strconcat(asmstr, " $dst"),
225 [(MipsFPBrcond op, bb:$dst)]>;
227 def BC1F : FBRANCH<MIPS_BRANCH_F, "bc1f">;
228 def BC1T : FBRANCH<MIPS_BRANCH_T, "bc1t">;
229 def BC1FL : FBRANCH<MIPS_BRANCH_FL, "bc1fl">;
230 def BC1TL : FBRANCH<MIPS_BRANCH_TL, "bc1tl">;
232 //===----------------------------------------------------------------------===//
233 // Floating Point Flag Conditions
234 //===----------------------------------------------------------------------===//
235 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
236 // They must be kept in synch.
237 def MIPS_FCOND_F : PatLeaf<(i32 0)>;
238 def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
239 def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>;
240 def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
241 def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
242 def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
243 def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
244 def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
245 def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
246 def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
247 def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
248 def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
249 def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
250 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
251 def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
252 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
254 /// Floating Point Compare
255 let hasDelaySlot = 1, Defs=[FCR31] in {
256 def FCMP_S32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
258 [(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc)]>;
260 def FCMP_D32 : FCC<0x1, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc),
262 [(MipsFPCmp AFGR64:$fs, AFGR64:$ft, imm:$cc)]>,
263 Requires<[In32BitMode]>;
267 // Conditional moves:
268 // These instructions are expanded in MipsISelLowering::EmitInstrWithCustomInserter
269 // if target does not have conditional move instructions.
270 // flag:int, data:float
271 let usesCustomInserter = 1, Constraints = "$F = $dst" in
272 class CondMovIntFP<RegisterClass RC, bits<5> fmt, bits<6> func,
274 FFR<0x11, func, fmt, (outs RC:$dst), (ins RC:$T, CPURegs:$cond, RC:$F),
275 !strconcat(instr_asm, "\t$dst, $T, $cond"), []>;
277 def MOVZ_S : CondMovIntFP<FGR32, 16, 18, "movz.s">;
278 def MOVN_S : CondMovIntFP<FGR32, 16, 19, "movn.s">;
280 let Predicates = [In32BitMode] in {
281 def MOVZ_D : CondMovIntFP<AFGR64, 17, 18, "movz.d">;
282 def MOVN_D : CondMovIntFP<AFGR64, 17, 19, "movn.d">;
285 defm : MovzPats<FGR32, MOVZ_S>;
286 defm : MovnPats<FGR32, MOVN_S>;
288 let Predicates = [In32BitMode] in {
289 defm : MovzPats<AFGR64, MOVZ_D>;
290 defm : MovnPats<AFGR64, MOVN_D>;
293 let usesCustomInserter = 1, Uses = [FCR31], Constraints = "$F = $dst" in {
294 // flag:float, data:int
295 class CondMovFPInt<SDNode cmov, bits<1> tf, string instr_asm> :
296 FCMOV<tf, (outs CPURegs:$dst), (ins CPURegs:$T, CPURegs:$F),
297 !strconcat(instr_asm, "\t$dst, $T, $$fcc0"),
298 [(set CPURegs:$dst, (cmov CPURegs:$T, CPURegs:$F))]>;
300 // flag:float, data:float
301 class CondMovFPFP<RegisterClass RC, SDNode cmov, bits<5> fmt, bits<1> tf,
303 FFCMOV<fmt, tf, (outs RC:$dst), (ins RC:$T, RC:$F),
304 !strconcat(instr_asm, "\t$dst, $T, $$fcc0"),
305 [(set RC:$dst, (cmov RC:$T, RC:$F))]>;
308 def MOVT : CondMovFPInt<MipsCMovFP_T, 1, "movt">;
309 def MOVF : CondMovFPInt<MipsCMovFP_F, 0, "movf">;
310 def MOVT_S : CondMovFPFP<FGR32, MipsCMovFP_T, 16, 1, "movt.s">;
311 def MOVF_S : CondMovFPFP<FGR32, MipsCMovFP_F, 16, 0, "movf.s">;
313 let Predicates = [In32BitMode] in {
314 def MOVT_D : CondMovFPFP<AFGR64, MipsCMovFP_T, 17, 1, "movt.d">;
315 def MOVF_D : CondMovFPFP<AFGR64, MipsCMovFP_F, 17, 0, "movf.d">;
318 //===----------------------------------------------------------------------===//
319 // Floating Point Pseudo-Instructions
320 //===----------------------------------------------------------------------===//
321 def MOVCCRToCCR : MipsPseudo<(outs CCR:$dst), (ins CCR:$src),
322 "# MOVCCRToCCR", []>;
324 // This pseudo instr gets expanded into 2 mtc1 instrs after register
327 MipsPseudo<(outs AFGR64:$dst),
328 (ins CPURegs:$lo, CPURegs:$hi), "",
329 [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>;
331 // This pseudo instr gets expanded into 2 mfc1 instrs after register
333 // if n is 0, lower part of src is extracted.
334 // if n is 1, higher part of src is extracted.
335 def ExtractElementF64 :
336 MipsPseudo<(outs CPURegs:$dst),
337 (ins AFGR64:$src, i32imm:$n), "",
339 (MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
341 //===----------------------------------------------------------------------===//
342 // Floating Point Patterns
343 //===----------------------------------------------------------------------===//
344 def fpimm0 : PatLeaf<(fpimm), [{
345 return N->isExactlyValue(+0.0);
348 def fpimm0neg : PatLeaf<(fpimm), [{
349 return N->isExactlyValue(-0.0);
352 def : Pat<(f32 fpimm0), (MTC1 ZERO)>;
353 def : Pat<(f32 fpimm0neg), (FNEG_S32 (MTC1 ZERO))>;
355 def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVTS_W32 (MTC1 CPURegs:$src))>;
356 def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVTD_W32 (MTC1 CPURegs:$src))>;
358 def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S32 FGR32:$src))>;
360 def : Pat<(i32 (bitconvert FGR32:$src)), (MFC1 FGR32:$src)>;
361 def : Pat<(f32 (bitconvert CPURegs:$src)), (MTC1 CPURegs:$src)>;
363 let Predicates = [In32BitMode] in {
364 def : Pat<(f32 (fround AFGR64:$src)), (CVTS_D32 AFGR64:$src)>;
365 def : Pat<(f64 (fextend FGR32:$src)), (CVTD_S32 FGR32:$src)>;
368 // MipsFPRound is only emitted for MipsI targets.
369 def : Pat<(f32 (MipsFPRound AFGR64:$src)), (CVTW_D32 AFGR64:$src)>;