1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Mips FPU instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Floating Point Instructions
16 // ------------------------
18 // - 32 64-bit registers (default mode)
19 // - 16 even 32-bit registers (32-bit compatible mode) for
20 // single and double access.
22 // - 16 even 32-bit registers - single and double (aliased)
23 // - 32 32-bit registers (within single-only mode)
24 //===----------------------------------------------------------------------===//
26 // Floating Point Compare and Branch
27 def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
28 SDTCisVT<1, OtherVT>]>;
29 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
31 def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
33 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
36 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
40 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
41 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
42 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
43 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
44 [SDNPHasChain, SDNPOptInGlue]>;
45 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
46 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
47 SDT_MipsExtractElementF64>;
49 // Operand for printing out a condition code.
50 let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
51 def condcode : Operand<i32>;
53 //===----------------------------------------------------------------------===//
54 // Feature predicates.
55 //===----------------------------------------------------------------------===//
57 def IsFP64bit : Predicate<"Subtarget.isFP64bit()">, AssemblerPredicate<"FeatureFP64Bit">;
58 def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">, AssemblerPredicate<"!FeatureFP64Bit">;
59 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">, AssemblerPredicate<"FeatureSingleFloat">;
60 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">, AssemblerPredicate<"!FeatureSingleFloat">;
62 // FP immediate patterns.
63 def fpimm0 : PatLeaf<(fpimm), [{
64 return N->isExactlyValue(+0.0);
67 def fpimm0neg : PatLeaf<(fpimm), [{
68 return N->isExactlyValue(-0.0);
71 //===----------------------------------------------------------------------===//
72 // Instruction Class Templates
74 // A set of multiclasses is used to address the register usage.
76 // S32 - single precision in 16 32bit even fp registers
77 // single precision in 32 32bit fp registers in SingleOnly mode
78 // S64 - single precision in 32 64bit fp registers (In64BitMode)
79 // D32 - double precision in 16 32bit even fp registers
80 // D64 - double precision in 32 64bit fp registers (In64BitMode)
82 // Only S32 and D32 are supported right now.
83 //===----------------------------------------------------------------------===//
86 let DecoderMethod = "DecodeFMem" in {
87 class FPLoad<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
88 FMem<op, (outs RC:$ft), (ins MemOpnd:$addr),
89 !strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (load_a addr:$addr))],
93 class FPStore<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
94 FMem<op, (outs), (ins RC:$ft, MemOpnd:$addr),
95 !strconcat(opstr, "\t$ft, $addr"), [(store_a RC:$ft, addr:$addr)],
99 class FPIdxLoad<bits<6> funct, string opstr, RegisterClass DRC,
100 RegisterClass PRC, PatFrag FOp>:
101 FFMemIdx<funct, (outs DRC:$fd), (ins PRC:$base, PRC:$index),
102 !strconcat(opstr, "\t$fd, $index($base)"),
103 [(set DRC:$fd, (FOp (add PRC:$base, PRC:$index)))]> {
108 class FPIdxStore<bits<6> funct, string opstr, RegisterClass DRC,
109 RegisterClass PRC, PatFrag FOp>:
110 FFMemIdx<funct, (outs), (ins DRC:$fs, PRC:$base, PRC:$index),
111 !strconcat(opstr, "\t$fs, $index($base)"),
112 [(FOp DRC:$fs, (add PRC:$base, PRC:$index))]> {
116 // Instructions that convert an FP value to 32-bit fixed point.
117 multiclass FFR1_W_M<bits<6> funct, string opstr> {
118 def _S : FFR1<funct, 16, opstr, "w.s", FGR32, FGR32>;
119 def _D32 : FFR1<funct, 17, opstr, "w.d", FGR32, AFGR64>,
120 Requires<[NotFP64bit]>;
121 def _D64 : FFR1<funct, 17, opstr, "w.d", FGR32, FGR64>,
122 Requires<[IsFP64bit]> {
123 let DecoderNamespace = "Mips64";
127 // Instructions that convert an FP value to 64-bit fixed point.
128 let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in
129 multiclass FFR1_L_M<bits<6> funct, string opstr> {
130 def _S : FFR1<funct, 16, opstr, "l.s", FGR64, FGR32>;
131 def _D64 : FFR1<funct, 17, opstr, "l.d", FGR64, FGR64>;
134 // FP-to-FP conversion instructions.
135 multiclass FFR1P_M<bits<6> funct, string opstr, SDNode OpNode> {
136 def _S : FFR1P<funct, 16, opstr, "s", FGR32, FGR32, OpNode>;
137 def _D32 : FFR1P<funct, 17, opstr, "d", AFGR64, AFGR64, OpNode>,
138 Requires<[NotFP64bit]>;
139 def _D64 : FFR1P<funct, 17, opstr, "d", FGR64, FGR64, OpNode>,
140 Requires<[IsFP64bit]> {
141 let DecoderNamespace = "Mips64";
145 multiclass FFR2P_M<bits<6> funct, string opstr, SDNode OpNode, bit isComm = 0> {
146 let isCommutable = isComm in {
147 def _S : FFR2P<funct, 16, opstr, "s", FGR32, OpNode>;
148 def _D32 : FFR2P<funct, 17, opstr, "d", AFGR64, OpNode>,
149 Requires<[NotFP64bit]>;
150 def _D64 : FFR2P<funct, 17, opstr, "d", FGR64, OpNode>,
151 Requires<[IsFP64bit]> {
152 let DecoderNamespace = "Mips64";
157 // FP madd/msub/nmadd/nmsub instruction classes.
158 class FMADDSUB<bits<3> funct, bits<3> fmt, string opstr, string fmtstr,
159 SDNode OpNode, RegisterClass RC> :
160 FFMADDSUB<funct, fmt, (outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
161 !strconcat(opstr, ".", fmtstr, "\t$fd, $fr, $fs, $ft"),
162 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))]>;
164 class FNMADDSUB<bits<3> funct, bits<3> fmt, string opstr, string fmtstr,
165 SDNode OpNode, RegisterClass RC> :
166 FFMADDSUB<funct, fmt, (outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
167 !strconcat(opstr, ".", fmtstr, "\t$fd, $fr, $fs, $ft"),
168 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))]>;
170 //===----------------------------------------------------------------------===//
171 // Floating Point Instructions
172 //===----------------------------------------------------------------------===//
173 defm ROUND_W : FFR1_W_M<0xc, "round">;
174 defm ROUND_L : FFR1_L_M<0x8, "round">;
175 defm TRUNC_W : FFR1_W_M<0xd, "trunc">;
176 defm TRUNC_L : FFR1_L_M<0x9, "trunc">;
177 defm CEIL_W : FFR1_W_M<0xe, "ceil">;
178 defm CEIL_L : FFR1_L_M<0xa, "ceil">;
179 defm FLOOR_W : FFR1_W_M<0xf, "floor">;
180 defm FLOOR_L : FFR1_L_M<0xb, "floor">;
181 defm CVT_W : FFR1_W_M<0x24, "cvt">;
182 //defm CVT_L : FFR1_L_M<0x25, "cvt">;
184 def CVT_S_W : FFR1<0x20, 20, "cvt", "s.w", FGR32, FGR32>;
185 def CVT_L_S : FFR1<0x25, 16, "cvt", "l.s", FGR64, FGR32>;
186 def CVT_L_D64: FFR1<0x25, 17, "cvt", "l.d", FGR64, FGR64>;
188 let Predicates = [NotFP64bit] in {
189 def CVT_S_D32 : FFR1<0x20, 17, "cvt", "s.d", FGR32, AFGR64>;
190 def CVT_D32_W : FFR1<0x21, 20, "cvt", "d.w", AFGR64, FGR32>;
191 def CVT_D32_S : FFR1<0x21, 16, "cvt", "d.s", AFGR64, FGR32>;
194 let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
195 def CVT_S_D64 : FFR1<0x20, 17, "cvt", "s.d", FGR32, FGR64>;
196 def CVT_S_L : FFR1<0x20, 21, "cvt", "s.l", FGR32, FGR64>;
197 def CVT_D64_W : FFR1<0x21, 20, "cvt", "d.w", FGR64, FGR32>;
198 def CVT_D64_S : FFR1<0x21, 16, "cvt", "d.s", FGR64, FGR32>;
199 def CVT_D64_L : FFR1<0x21, 21, "cvt", "d.l", FGR64, FGR64>;
202 defm FABS : FFR1P_M<0x5, "abs", fabs>;
203 defm FNEG : FFR1P_M<0x7, "neg", fneg>;
204 defm FSQRT : FFR1P_M<0x4, "sqrt", fsqrt>;
206 // The odd-numbered registers are only referenced when doing loads,
207 // stores, and moves between floating-point and integer registers.
208 // When defining instructions, we reference all 32-bit registers,
209 // regardless of register aliasing.
211 class FFRGPR<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern>:
212 FFR<0x11, 0x0, _fmt, outs, ins, asmstr, pattern> {
218 /// Move Control Registers From/To CPU Registers
219 def CFC1 : FFRGPR<0x2, (outs CPURegs:$rt), (ins CCR:$fs),
220 "cfc1\t$rt, $fs", []>;
222 def CTC1 : FFRGPR<0x6, (outs CCR:$fs), (ins CPURegs:$rt),
223 "ctc1\t$rt, $fs", []>;
225 def MFC1 : FFRGPR<0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
227 [(set CPURegs:$rt, (bitconvert FGR32:$fs))]>;
229 def MTC1 : FFRGPR<0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
231 [(set FGR32:$fs, (bitconvert CPURegs:$rt))]>;
233 def DMFC1 : FFRGPR<0x01, (outs CPU64Regs:$rt), (ins FGR64:$fs),
235 [(set CPU64Regs:$rt, (bitconvert FGR64:$fs))]>;
237 def DMTC1 : FFRGPR<0x05, (outs FGR64:$fs), (ins CPU64Regs:$rt),
239 [(set FGR64:$fs, (bitconvert CPU64Regs:$rt))]>;
241 def FMOV_S : FFR1<0x6, 16, "mov", "s", FGR32, FGR32>;
242 def FMOV_D32 : FFR1<0x6, 17, "mov", "d", AFGR64, AFGR64>,
243 Requires<[NotFP64bit]>;
244 def FMOV_D64 : FFR1<0x6, 17, "mov", "d", FGR64, FGR64>,
245 Requires<[IsFP64bit]> {
246 let DecoderNamespace = "Mips64";
249 /// Floating Point Memory Instructions
250 let Predicates = [IsN64], DecoderNamespace = "Mips64" in {
251 def LWC1_P8 : FPLoad<0x31, "lwc1", FGR32, mem64>;
252 def SWC1_P8 : FPStore<0x39, "swc1", FGR32, mem64>;
253 def LDC164_P8 : FPLoad<0x35, "ldc1", FGR64, mem64> {
254 let isCodeGenOnly =1;
256 def SDC164_P8 : FPStore<0x3d, "sdc1", FGR64, mem64> {
257 let isCodeGenOnly =1;
261 let Predicates = [NotN64] in {
262 def LWC1 : FPLoad<0x31, "lwc1", FGR32, mem>;
263 def SWC1 : FPStore<0x39, "swc1", FGR32, mem>;
266 let Predicates = [NotN64, HasMips64], DecoderNamespace = "Mips64" in {
267 def LDC164 : FPLoad<0x35, "ldc1", FGR64, mem>;
268 def SDC164 : FPStore<0x3d, "sdc1", FGR64, mem>;
271 let Predicates = [NotN64, NotMips64] in {
272 def LDC1 : FPLoad<0x35, "ldc1", AFGR64, mem>;
273 def SDC1 : FPStore<0x3d, "sdc1", AFGR64, mem>;
276 // Indexed loads and stores.
277 let Predicates = [HasMips32r2Or64] in {
278 def LWXC1 : FPIdxLoad<0x0, "lwxc1", FGR32, CPURegs, load_a>;
279 def LUXC1 : FPIdxLoad<0x5, "luxc1", FGR32, CPURegs, load_u>;
280 def SWXC1 : FPIdxStore<0x8, "swxc1", FGR32, CPURegs, store_a>;
281 def SUXC1 : FPIdxStore<0xd, "suxc1", FGR32, CPURegs, store_u>;
284 let Predicates = [HasMips32r2, NotMips64] in {
285 def LDXC1 : FPIdxLoad<0x1, "ldxc1", AFGR64, CPURegs, load_a>;
286 def SDXC1 : FPIdxStore<0x9, "sdxc1", AFGR64, CPURegs, store_a>;
289 let Predicates = [HasMips64, NotN64], DecoderNamespace="Mips64" in {
290 def LDXC164 : FPIdxLoad<0x1, "ldxc1", FGR64, CPURegs, load_a>;
291 def SDXC164 : FPIdxStore<0x9, "sdxc1", FGR64, CPURegs, store_a>;
295 let Predicates = [IsN64], isCodeGenOnly=1 in {
296 def LWXC1_P8 : FPIdxLoad<0x0, "lwxc1", FGR32, CPU64Regs, load_a>;
297 def LUXC1_P8 : FPIdxLoad<0x5, "luxc1", FGR32, CPU64Regs, load_u>;
298 def LDXC164_P8 : FPIdxLoad<0x1, "ldxc1", FGR64, CPU64Regs, load_a>;
299 def SWXC1_P8 : FPIdxStore<0x8, "swxc1", FGR32, CPU64Regs, store_a>;
300 def SUXC1_P8 : FPIdxStore<0xd, "suxc1", FGR32, CPU64Regs, store_u>;
301 def SDXC164_P8 : FPIdxStore<0x9, "sdxc1", FGR64, CPU64Regs, store_a>;
304 /// Floating-point Aritmetic
305 defm FADD : FFR2P_M<0x00, "add", fadd, 1>;
306 defm FDIV : FFR2P_M<0x03, "div", fdiv>;
307 defm FMUL : FFR2P_M<0x02, "mul", fmul, 1>;
308 defm FSUB : FFR2P_M<0x01, "sub", fsub>;
310 let Predicates = [HasMips32r2] in {
311 def MADD_S : FMADDSUB<0x4, 0, "madd", "s", fadd, FGR32>;
312 def MSUB_S : FMADDSUB<0x5, 0, "msub", "s", fsub, FGR32>;
315 let Predicates = [HasMips32r2, NoNaNsFPMath] in {
316 def NMADD_S : FNMADDSUB<0x6, 0, "nmadd", "s", fadd, FGR32>;
317 def NMSUB_S : FNMADDSUB<0x7, 0, "nmsub", "s", fsub, FGR32>;
320 let Predicates = [HasMips32r2, NotFP64bit] in {
321 def MADD_D32 : FMADDSUB<0x4, 1, "madd", "d", fadd, AFGR64>;
322 def MSUB_D32 : FMADDSUB<0x5, 1, "msub", "d", fsub, AFGR64>;
325 let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath] in {
326 def NMADD_D32 : FNMADDSUB<0x6, 1, "nmadd", "d", fadd, AFGR64>;
327 def NMSUB_D32 : FNMADDSUB<0x7, 1, "nmsub", "d", fsub, AFGR64>;
330 let Predicates = [HasMips32r2, IsFP64bit], isCodeGenOnly=1 in {
331 def MADD_D64 : FMADDSUB<0x4, 1, "madd", "d", fadd, FGR64>;
332 def MSUB_D64 : FMADDSUB<0x5, 1, "msub", "d", fsub, FGR64>;
335 let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath], isCodeGenOnly=1 in {
336 def NMADD_D64 : FNMADDSUB<0x6, 1, "nmadd", "d", fadd, FGR64>;
337 def NMSUB_D64 : FNMADDSUB<0x7, 1, "nmsub", "d", fsub, FGR64>;
340 //===----------------------------------------------------------------------===//
341 // Floating Point Branch Codes
342 //===----------------------------------------------------------------------===//
343 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
344 // They must be kept in synch.
345 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
346 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
348 /// Floating Point Branch of False/True (Likely)
349 let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in
350 class FBRANCH<bits<1> nd, bits<1> tf, PatLeaf op, string asmstr> :
351 FFI<0x11, (outs), (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"),
352 [(MipsFPBrcond op, bb:$dst)]> {
358 let DecoderMethod = "DecodeBC1" in {
359 def BC1F : FBRANCH<0, 0, MIPS_BRANCH_F, "bc1f">;
360 def BC1T : FBRANCH<0, 1, MIPS_BRANCH_T, "bc1t">;
362 //===----------------------------------------------------------------------===//
363 // Floating Point Flag Conditions
364 //===----------------------------------------------------------------------===//
365 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
366 // They must be kept in synch.
367 def MIPS_FCOND_F : PatLeaf<(i32 0)>;
368 def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
369 def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>;
370 def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
371 def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
372 def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
373 def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
374 def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
375 def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
376 def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
377 def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
378 def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
379 def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
380 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
381 def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
382 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
384 class FCMP<bits<5> fmt, RegisterClass RC, string typestr> :
385 FCC<fmt, (outs), (ins RC:$fs, RC:$ft, condcode:$cc),
386 !strconcat("c.$cc.", typestr, "\t$fs, $ft"),
387 [(MipsFPCmp RC:$fs, RC:$ft, imm:$cc)]>;
389 /// Floating Point Compare
390 let Defs=[FCR31] in {
391 def FCMP_S32 : FCMP<0x10, FGR32, "s">;
392 def FCMP_D32 : FCMP<0x11, AFGR64, "d">, Requires<[NotFP64bit]>;
393 def FCMP_D64 : FCMP<0x11, FGR64, "d">, Requires<[IsFP64bit]> {
394 let DecoderNamespace = "Mips64";
398 //===----------------------------------------------------------------------===//
399 // Floating Point Pseudo-Instructions
400 //===----------------------------------------------------------------------===//
401 def MOVCCRToCCR : MipsPseudo<(outs CCR:$dst), (ins CCR:$src),
402 "# MOVCCRToCCR", []>;
404 // This pseudo instr gets expanded into 2 mtc1 instrs after register
407 MipsPseudo<(outs AFGR64:$dst),
408 (ins CPURegs:$lo, CPURegs:$hi), "",
409 [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>;
411 // This pseudo instr gets expanded into 2 mfc1 instrs after register
413 // if n is 0, lower part of src is extracted.
414 // if n is 1, higher part of src is extracted.
415 def ExtractElementF64 :
416 MipsPseudo<(outs CPURegs:$dst),
417 (ins AFGR64:$src, i32imm:$n), "",
419 (MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
421 //===----------------------------------------------------------------------===//
422 // Floating Point Patterns
423 //===----------------------------------------------------------------------===//
424 def : Pat<(f32 fpimm0), (MTC1 ZERO)>;
425 def : Pat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
427 def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
428 def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>;
430 let Predicates = [NotFP64bit] in {
431 def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D32_W (MTC1 CPURegs:$src))>;
432 def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
433 def : Pat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
434 def : Pat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;
437 let Predicates = [IsFP64bit] in {
438 def : Pat<(f64 fpimm0), (DMTC1 ZERO_64)>;
439 def : Pat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
441 def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D64_W (MTC1 CPURegs:$src))>;
442 def : Pat<(f32 (sint_to_fp CPU64Regs:$src)),
443 (CVT_S_L (DMTC1 CPU64Regs:$src))>;
444 def : Pat<(f64 (sint_to_fp CPU64Regs:$src)),
445 (CVT_D64_L (DMTC1 CPU64Regs:$src))>;
447 def : Pat<(i32 (fp_to_sint FGR64:$src)), (MFC1 (TRUNC_W_D64 FGR64:$src))>;
448 def : Pat<(i64 (fp_to_sint FGR32:$src)), (DMFC1 (TRUNC_L_S FGR32:$src))>;
449 def : Pat<(i64 (fp_to_sint FGR64:$src)), (DMFC1 (TRUNC_L_D64 FGR64:$src))>;
451 def : Pat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
452 def : Pat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;
455 // Patterns for unaligned floating point loads and stores.
456 let Predicates = [HasMips32r2Or64, NotN64] in {
457 def : Pat<(f32 (load_u CPURegs:$addr)), (LUXC1 CPURegs:$addr, ZERO)>;
458 def : Pat<(store_u FGR32:$src, CPURegs:$addr),
459 (SUXC1 FGR32:$src, CPURegs:$addr, ZERO)>;
462 let Predicates = [IsN64] in {
463 def : Pat<(f32 (load_u CPU64Regs:$addr)), (LUXC1_P8 CPU64Regs:$addr, ZERO_64)>;
464 def : Pat<(store_u FGR32:$src, CPU64Regs:$addr),
465 (SUXC1_P8 FGR32:$src, CPU64Regs:$addr, ZERO_64)>;