1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Mips FPU instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Floating Point Instructions
16 // ------------------------
18 // - 32 64-bit registers (default mode)
19 // - 16 even 32-bit registers (32-bit compatible mode) for
20 // single and double access.
22 // - 16 even 32-bit registers - single and double (aliased)
23 // - 32 32-bit registers (within single-only mode)
24 //===----------------------------------------------------------------------===//
26 // Floating Point Compare and Branch
27 def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
28 SDTCisVT<1, OtherVT>]>;
29 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
31 def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
33 def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
34 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
37 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
41 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
42 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
43 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
44 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
45 [SDNPHasChain, SDNPOptInGlue]>;
46 def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>;
47 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
48 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
49 SDT_MipsExtractElementF64>;
51 // Operand for printing out a condition code.
52 let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
53 def condcode : Operand<i32>;
55 //===----------------------------------------------------------------------===//
56 // Feature predicates.
57 //===----------------------------------------------------------------------===//
59 def IsFP64bit : Predicate<"Subtarget.isFP64bit()">,
60 AssemblerPredicate<"FeatureFP64Bit">;
61 def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">,
62 AssemblerPredicate<"!FeatureFP64Bit">;
63 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">,
64 AssemblerPredicate<"FeatureSingleFloat">;
65 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">,
66 AssemblerPredicate<"!FeatureSingleFloat">;
68 // FP immediate patterns.
69 def fpimm0 : PatLeaf<(fpimm), [{
70 return N->isExactlyValue(+0.0);
73 def fpimm0neg : PatLeaf<(fpimm), [{
74 return N->isExactlyValue(-0.0);
77 //===----------------------------------------------------------------------===//
78 // Instruction Class Templates
80 // A set of multiclasses is used to address the register usage.
82 // S32 - single precision in 16 32bit even fp registers
83 // single precision in 32 32bit fp registers in SingleOnly mode
84 // S64 - single precision in 32 64bit fp registers (In64BitMode)
85 // D32 - double precision in 16 32bit even fp registers
86 // D64 - double precision in 32 64bit fp registers (In64BitMode)
88 // Only S32 and D32 are supported right now.
89 //===----------------------------------------------------------------------===//
91 class ADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin, bit IsComm,
92 SDPatternOperator OpNode= null_frag> :
93 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
94 !strconcat(opstr, "\t$fd, $fs, $ft"),
95 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> {
96 let isCommutable = IsComm;
99 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
100 SDPatternOperator OpNode = null_frag> {
101 def _D32 : ADDS_FT<opstr, AFGR64, Itin, IsComm, OpNode>,
102 Requires<[NotFP64bit, HasStdEnc]>;
103 def _D64 : ADDS_FT<opstr, FGR64, Itin, IsComm, OpNode>,
104 Requires<[IsFP64bit, HasStdEnc]> {
105 string DecoderNamespace = "Mips64";
109 class ABSS_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
110 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
111 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
112 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>,
115 multiclass ABSS_M<string opstr, InstrItinClass Itin,
116 SDPatternOperator OpNode= null_frag> {
117 def _D32 : ABSS_FT<opstr, AFGR64, AFGR64, Itin, OpNode>,
118 Requires<[NotFP64bit, HasStdEnc]>;
119 def _D64 : ABSS_FT<opstr, FGR64, FGR64, Itin, OpNode>,
120 Requires<[IsFP64bit, HasStdEnc]> {
121 string DecoderNamespace = "Mips64";
125 multiclass ROUND_M<string opstr, InstrItinClass Itin> {
126 def _D32 : ABSS_FT<opstr, FGR32, AFGR64, Itin>,
127 Requires<[NotFP64bit, HasStdEnc]>;
128 def _D64 : ABSS_FT<opstr, FGR32, FGR64, Itin>,
129 Requires<[IsFP64bit, HasStdEnc]> {
130 let DecoderNamespace = "Mips64";
134 class MFC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
135 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
136 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
137 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
139 class MTC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
140 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
141 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
142 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
144 class MFC1_FT_CCR<string opstr, RegisterClass DstRC, RegisterOperand SrcRC,
145 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
146 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
147 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
149 class MTC1_FT_CCR<string opstr, RegisterOperand DstRC, RegisterClass SrcRC,
150 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
151 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
152 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
154 class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
155 Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
156 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
157 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI> {
158 let DecoderMethod = "DecodeFMem";
162 class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
163 Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
164 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
165 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI> {
166 let DecoderMethod = "DecodeFMem";
170 class MADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
171 SDPatternOperator OpNode = null_frag> :
172 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
173 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
174 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, FrmFR>;
176 class NMADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
177 SDPatternOperator OpNode = null_frag> :
178 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
179 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
180 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
183 class LWXC1_FT<string opstr, RegisterOperand DRC, RegisterOperand PRC,
184 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
185 InstSE<(outs DRC:$fd), (ins PRC:$base, PRC:$index),
186 !strconcat(opstr, "\t$fd, ${index}(${base})"),
187 [(set DRC:$fd, (OpNode (add PRC:$base, PRC:$index)))], Itin, FrmFI> {
188 let AddedComplexity = 20;
191 class SWXC1_FT<string opstr, RegisterOperand DRC, RegisterOperand PRC,
192 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
193 InstSE<(outs), (ins DRC:$fs, PRC:$base, PRC:$index),
194 !strconcat(opstr, "\t$fs, ${index}(${base})"),
195 [(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI> {
196 let AddedComplexity = 20;
199 class BC1F_FT<string opstr, InstrItinClass Itin,
200 SDPatternOperator Op = null_frag> :
201 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
202 [(MipsFPBrcond Op, bb:$offset)], Itin, FrmFI> {
204 let isTerminator = 1;
205 let hasDelaySlot = 1;
210 class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
211 SDPatternOperator OpNode = null_frag> :
212 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
213 !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
214 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR> {
218 //===----------------------------------------------------------------------===//
219 // Floating Point Instructions
220 //===----------------------------------------------------------------------===//
221 def ROUND_W_S : ABSS_FT<"round.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xc, 16>;
222 def TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xd, 16>;
223 def CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xe, 16>;
224 def FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xf, 16>;
225 def CVT_W_S : ABSS_FT<"cvt.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0x24, 16>;
227 defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>;
228 defm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>;
229 defm CEIL_W : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>;
230 defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>;
231 defm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>;
233 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
234 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x8, 16>;
235 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64, FGR64, IIFcvt>,
237 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x9, 16>;
238 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64, FGR64, IIFcvt>,
240 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xa, 16>;
241 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0xa, 17>;
242 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xb, 16>;
243 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64, FGR64, IIFcvt>,
247 def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32, FGR32, IIFcvt>, ABSS_FM<0x20, 20>;
248 def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x25, 16>;
249 def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0x25, 17>;
251 let Predicates = [NotFP64bit, HasStdEnc] in {
252 def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32, AFGR64, IIFcvt>, ABSS_FM<0x20, 17>;
253 def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
254 def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
257 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
258 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 17>;
259 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 21>;
260 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
261 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
262 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64, FGR64, IIFcvt>, ABSS_FM<0x21, 21>;
265 let isPseudo = 1, isCodeGenOnly = 1 in {
266 def PseudoCVT_S_W : ABSS_FT<"", FGR32, CPURegs, IIFcvt>;
267 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64, CPURegs, IIFcvt>;
268 def PseudoCVT_S_L : ABSS_FT<"", FGR64, CPU64Regs, IIFcvt>;
269 def PseudoCVT_D64_W : ABSS_FT<"", FGR64, CPURegs, IIFcvt>;
270 def PseudoCVT_D64_L : ABSS_FT<"", FGR64, CPU64Regs, IIFcvt>;
273 let Predicates = [NoNaNsFPMath, HasStdEnc] in {
274 def FABS_S : ABSS_FT<"abs.s", FGR32, FGR32, IIFcvt, fabs>, ABSS_FM<0x5, 16>;
275 def FNEG_S : ABSS_FT<"neg.s", FGR32, FGR32, IIFcvt, fneg>, ABSS_FM<0x7, 16>;
276 defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>;
277 defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>;
280 def FSQRT_S : ABSS_FT<"sqrt.s", FGR32, FGR32, IIFsqrtSingle, fsqrt>,
282 defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
284 // The odd-numbered registers are only referenced when doing loads,
285 // stores, and moves between floating-point and integer registers.
286 // When defining instructions, we reference all 32-bit registers,
287 // regardless of register aliasing.
289 /// Move Control Registers From/To CPU Registers
290 def CFC1 : MFC1_FT_CCR<"cfc1", CPURegs, CCROpnd, IIFmove>, MFC1_FM<2>;
291 def CTC1 : MTC1_FT_CCR<"ctc1", CCROpnd, CPURegs, IIFmove>, MFC1_FM<6>;
292 def MFC1 : MFC1_FT<"mfc1", CPURegs, FGR32, IIFmove, bitconvert>, MFC1_FM<0>;
293 def MTC1 : MTC1_FT<"mtc1", FGR32, CPURegs, IIFmove, bitconvert>, MFC1_FM<4>;
294 def DMFC1 : MFC1_FT<"dmfc1", CPU64Regs, FGR64, IIFmove, bitconvert>, MFC1_FM<1>;
295 def DMTC1 : MTC1_FT<"dmtc1", FGR64, CPU64Regs, IIFmove, bitconvert>, MFC1_FM<5>;
297 def FMOV_S : ABSS_FT<"mov.s", FGR32, FGR32, IIFmove>, ABSS_FM<0x6, 16>;
298 def FMOV_D32 : ABSS_FT<"mov.d", AFGR64, AFGR64, IIFmove>, ABSS_FM<0x6, 17>,
299 Requires<[NotFP64bit, HasStdEnc]>;
300 def FMOV_D64 : ABSS_FT<"mov.d", FGR64, FGR64, IIFmove>, ABSS_FM<0x6, 17>,
301 Requires<[IsFP64bit, HasStdEnc]> {
302 let DecoderNamespace = "Mips64";
305 /// Floating Point Memory Instructions
306 let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
307 def LWC1_P8 : LW_FT<"lwc1", FGR32RegsOpnd, IILoad, mem64, load>, LW_FM<0x31>;
308 def SWC1_P8 : SW_FT<"swc1", FGR32RegsOpnd, IIStore, mem64, store>,
310 def LDC164_P8 : LW_FT<"ldc1", FGR64RegsOpnd, IILoad, mem64, load>,
312 let isCodeGenOnly =1;
314 def SDC164_P8 : SW_FT<"sdc1", FGR64RegsOpnd, IIStore, mem64, store>,
316 let isCodeGenOnly =1;
320 let Predicates = [NotN64, HasStdEnc] in {
321 def LWC1 : LW_FT<"lwc1", FGR32RegsOpnd, IILoad, mem, load>, LW_FM<0x31>;
322 def SWC1 : SW_FT<"swc1", FGR32RegsOpnd, IIStore, mem, store>, LW_FM<0x39>;
325 let Predicates = [NotN64, HasMips64, HasStdEnc],
326 DecoderNamespace = "Mips64" in {
327 def LDC164 : LW_FT<"ldc1", FGR64RegsOpnd, IILoad, mem, load>, LW_FM<0x35>;
328 def SDC164 : SW_FT<"sdc1", FGR64RegsOpnd, IIStore, mem, store>, LW_FM<0x3d>;
331 let Predicates = [NotN64, NotMips64, HasStdEnc] in {
332 let isPseudo = 1, isCodeGenOnly = 1 in {
333 def PseudoLDC1 : LW_FT<"", AFGR64RegsOpnd, IILoad, mem, load>;
334 def PseudoSDC1 : SW_FT<"", AFGR64RegsOpnd, IIStore, mem, store>;
336 def LDC1 : LW_FT<"ldc1", AFGR64RegsOpnd, IILoad, mem>, LW_FM<0x35>;
337 def SDC1 : SW_FT<"sdc1", AFGR64RegsOpnd, IIStore, mem>, LW_FM<0x3d>;
340 // Indexed loads and stores.
341 let Predicates = [HasFPIdx, HasStdEnc] in {
342 def LWXC1 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, CPURegsOpnd, IILoad, load>,
344 def SWXC1 : SWXC1_FT<"swxc1", FGR32RegsOpnd, CPURegsOpnd, IIStore, store>,
348 let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in {
349 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64RegsOpnd, CPURegsOpnd, IILoad, load>,
351 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64RegsOpnd, CPURegsOpnd, IIStore, store>,
355 let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in {
356 def LDXC164 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, CPURegsOpnd, IILoad, load>,
358 def SDXC164 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, CPURegsOpnd, IIStore, store>,
363 let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in {
364 def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, CPU64RegsOpnd, IILoad, load>,
366 def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, CPU64RegsOpnd, IILoad,
368 def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32RegsOpnd, CPU64RegsOpnd, IIStore,
370 def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, CPU64RegsOpnd, IIStore,
374 // Load/store doubleword indexed unaligned.
375 let Predicates = [NotMips64, HasStdEnc] in {
376 def LUXC1 : LWXC1_FT<"luxc1", AFGR64RegsOpnd, CPURegsOpnd, IILoad>,
378 def SUXC1 : SWXC1_FT<"suxc1", AFGR64RegsOpnd, CPURegsOpnd, IIStore>,
382 let Predicates = [HasMips64, HasStdEnc],
383 DecoderNamespace="Mips64" in {
384 def LUXC164 : LWXC1_FT<"luxc1", FGR64RegsOpnd, CPURegsOpnd, IILoad>,
386 def SUXC164 : SWXC1_FT<"suxc1", FGR64RegsOpnd, CPURegsOpnd, IIStore>,
390 /// Floating-point Aritmetic
391 def FADD_S : ADDS_FT<"add.s", FGR32, IIFadd, 1, fadd>, ADDS_FM<0x00, 16>;
392 defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>;
393 def FDIV_S : ADDS_FT<"div.s", FGR32, IIFdivSingle, 0, fdiv>, ADDS_FM<0x03, 16>;
394 defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>;
395 def FMUL_S : ADDS_FT<"mul.s", FGR32, IIFmulSingle, 1, fmul>, ADDS_FM<0x02, 16>;
396 defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>;
397 def FSUB_S : ADDS_FT<"sub.s", FGR32, IIFadd, 0, fsub>, ADDS_FM<0x01, 16>;
398 defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>;
400 let Predicates = [HasMips32r2, HasStdEnc] in {
401 def MADD_S : MADDS_FT<"madd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<4, 0>;
402 def MSUB_S : MADDS_FT<"msub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<5, 0>;
405 let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in {
406 def NMADD_S : NMADDS_FT<"nmadd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<6, 0>;
407 def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<7, 0>;
410 let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in {
411 def MADD_D32 : MADDS_FT<"madd.d", AFGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>;
412 def MSUB_D32 : MADDS_FT<"msub.d", AFGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>;
415 let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in {
416 def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64, IIFmulDouble, fadd>,
418 def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64, IIFmulDouble, fsub>,
422 let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in {
423 def MADD_D64 : MADDS_FT<"madd.d", FGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>;
424 def MSUB_D64 : MADDS_FT<"msub.d", FGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>;
427 let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
429 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64, IIFmulDouble, fadd>,
431 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64, IIFmulDouble, fsub>,
435 //===----------------------------------------------------------------------===//
436 // Floating Point Branch Codes
437 //===----------------------------------------------------------------------===//
438 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
439 // They must be kept in synch.
440 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
441 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
443 let DecoderMethod = "DecodeBC1" in {
444 def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>;
445 def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>;
447 //===----------------------------------------------------------------------===//
448 // Floating Point Flag Conditions
449 //===----------------------------------------------------------------------===//
450 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
451 // They must be kept in synch.
452 def MIPS_FCOND_F : PatLeaf<(i32 0)>;
453 def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
454 def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>;
455 def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
456 def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
457 def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
458 def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
459 def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
460 def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
461 def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
462 def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
463 def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
464 def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
465 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
466 def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
467 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
469 /// Floating Point Compare
470 def FCMP_S32 : CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>;
471 def FCMP_D32 : CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
472 Requires<[NotFP64bit, HasStdEnc]>;
473 let DecoderNamespace = "Mips64" in
474 def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
475 Requires<[IsFP64bit, HasStdEnc]>;
477 //===----------------------------------------------------------------------===//
478 // Floating Point Pseudo-Instructions
479 //===----------------------------------------------------------------------===//
480 def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCROpnd:$src), []>;
482 // This pseudo instr gets expanded into 2 mtc1 instrs after register
485 PseudoSE<(outs AFGR64:$dst),
486 (ins CPURegs:$lo, CPURegs:$hi),
487 [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>;
489 // This pseudo instr gets expanded into 2 mfc1 instrs after register
491 // if n is 0, lower part of src is extracted.
492 // if n is 1, higher part of src is extracted.
493 def ExtractElementF64 :
494 PseudoSE<(outs CPURegs:$dst), (ins AFGR64:$src, i32imm:$n),
495 [(set CPURegs:$dst, (MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
497 //===----------------------------------------------------------------------===//
498 // Floating Point Patterns
499 //===----------------------------------------------------------------------===//
500 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
501 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
503 def : MipsPat<(f32 (sint_to_fp CPURegs:$src)), (PseudoCVT_S_W CPURegs:$src)>;
504 def : MipsPat<(MipsTruncIntFP FGR32:$src), (TRUNC_W_S FGR32:$src)>;
506 let Predicates = [NotFP64bit, HasStdEnc] in {
507 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
508 (PseudoCVT_D32_W CPURegs:$src)>;
509 def : MipsPat<(MipsTruncIntFP AFGR64:$src), (TRUNC_W_D32 AFGR64:$src)>;
510 def : MipsPat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
511 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;
514 let Predicates = [IsFP64bit, HasStdEnc] in {
515 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>;
516 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
518 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
519 (PseudoCVT_D64_W CPURegs:$src)>;
520 def : MipsPat<(f32 (sint_to_fp CPU64Regs:$src)),
521 (EXTRACT_SUBREG (PseudoCVT_S_L CPU64Regs:$src), sub_32)>;
522 def : MipsPat<(f64 (sint_to_fp CPU64Regs:$src)),
523 (PseudoCVT_D64_L CPU64Regs:$src)>;
525 def : MipsPat<(MipsTruncIntFP FGR64:$src), (TRUNC_W_D64 FGR64:$src)>;
526 def : MipsPat<(MipsTruncIntFP FGR32:$src), (TRUNC_L_S FGR32:$src)>;
527 def : MipsPat<(MipsTruncIntFP FGR64:$src), (TRUNC_L_D64 FGR64:$src)>;
529 def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
530 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;
533 // Patterns for loads/stores with a reg+imm operand.
534 let AddedComplexity = 40 in {
535 let Predicates = [IsN64, HasStdEnc] in {
536 def : LoadRegImmPat<LWC1_P8, f32, load>;
537 def : StoreRegImmPat<SWC1_P8, f32>;
538 def : LoadRegImmPat<LDC164_P8, f64, load>;
539 def : StoreRegImmPat<SDC164_P8, f64>;
542 let Predicates = [NotN64, HasStdEnc] in {
543 def : LoadRegImmPat<LWC1, f32, load>;
544 def : StoreRegImmPat<SWC1, f32>;
547 let Predicates = [NotN64, HasMips64, HasStdEnc] in {
548 def : LoadRegImmPat<LDC164, f64, load>;
549 def : StoreRegImmPat<SDC164, f64>;
552 let Predicates = [NotN64, NotMips64, HasStdEnc] in {
553 def : LoadRegImmPat<PseudoLDC1, f64, load>;
554 def : StoreRegImmPat<PseudoSDC1, f64>;